START = start.o
SOBJS = irq.o
-COBJS = cpu.o interrupts.o cache.o exception.o timer.o hw_watchdog.o
+COBJS = cpu.o interrupts.o cache.o exception.o timer.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+++ /dev/null
-/******************************************************************************
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-* (c) Copyright 2011 Xilinx Inc.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-
-#include <common.h>
-#include <asm/io.h>
-#include <watchdog.h>
-
-#ifdef CONFIG_HW_WATCHDOG
-
- #define XWT_TWCSR0_OFFSET 0x0 /**< Control/Status Register 0 Offset */
- #define XWT_TWCSR1_OFFSET 0x4 /**< Control/Status Register 1 Offset */
- #define XWT_TBR_OFFSET 0x8 /**< Timebase Register Offset */
-
- #define XWT_CSR0_WRS_MASK 0x00000008 /**< Reset status Mask */
- #define XWT_CSR0_WDS_MASK 0x00000004 /**< Timer state Mask */
- #define XWT_CSR0_EWDT1_MASK 0x00000002 /**< Enable bit 1 Mask*/
- #define XWT_CSRX_EWDT2_MASK 0x00000001 /**< Enable bit 2 Mask */
-
-void hw_watchdog_reset(void)
-{
- unsigned int CSRRegister;
-
-#ifdef XPAR_MICROBLAZE_USE_DCACHE
- microblaze_invalidate_dcache_range(WATCHDOG_BASEADDR, 4);
-#endif
-
- /* Read the current contents of TCSR0 */
- CSRRegister = inl(WATCHDOG_BASEADDR + XWT_TWCSR0_OFFSET);
-
- /* Clear the watchdog WDS bit */
- if (CSRRegister & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
- {
- outl(CSRRegister | XWT_CSR0_WDS_MASK, WATCHDOG_BASEADDR + XWT_TWCSR0_OFFSET);
-#ifdef XPAR_MICROBLAZE_USE_DCACHE
- microblaze_flush_dcache_range(WATCHDOG_BASEADDR, 4);
-#endif
- }
-}
-
-void hw_watchdog_init(void)
-{
- outl((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK), WATCHDOG_BASEADDR + XWT_TWCSR0_OFFSET);
- outl(XWT_CSRX_EWDT2_MASK, WATCHDOG_BASEADDR + XWT_TWCSR1_OFFSET);
-
-#ifdef XPAR_MICROBLAZE_USE_DCACHE
- microblaze_flush_dcache_range(WATCHDOG_BASEADDR, 8);
-#endif
-}
-
-void hw_watchdog_disable(void)
-{
- unsigned int CSRRegister;
-
-#ifdef XPAR_MICROBLAZE_USE_DCACHE
- microblaze_invalidate_dcache_range(WATCHDOG_BASEADDR, 4);
-#endif
-
- /* Read the current contents of TCSR0 */
- CSRRegister = inl(WATCHDOG_BASEADDR + XWT_TWCSR0_OFFSET);
-
- outl(CSRRegister & ~XWT_CSR0_EWDT1_MASK, WATCHDOG_BASEADDR + XWT_TWCSR0_OFFSET);
- outl(~XWT_CSRX_EWDT2_MASK, WATCHDOG_BASEADDR + XWT_TWCSR1_OFFSET);
-#ifdef XPAR_MICROBLAZE_USE_DCACHE
- microblaze_flush_dcache_range(WATCHDOG_BASEADDR, 8);
-#endif
-
-}
-
-#endif
/* Microblaze board initialization function */
void board_init(void);
+/* Watchdog functions */
+int hw_watchdog_init(void);
+void hw_watchdog_disable(void);
+
#endif /* __ASM_MICROBLAZE_PROCESSOR_H */
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_HW_WATCHDOG)
-extern int hw_watchdog_init(void);
-#endif /* CONFIG_WATCHDOG */
-
/*
* All attempts to come up with a "common" initialization sequence
* that works for all boards and architectures failed: some of the
serial_init,
console_init_f,
interrupts_init,
+#ifdef CONFIG_XILINX_TB_WATCHDOG
+ hw_watchdog_init,
+#endif
timer_init,
NULL,
};
serial_initialize();
-#if defined(CONFIG_HW_WATCHDOG)
- hw_watchdog_init();
-#endif
-
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET ();
if ((*init_fnc_ptr) () != 0) {
++(*((u32 volatile *)(CONFIG_SYS_GPIO_0_ADDR)));
#endif
+#ifdef CONFIG_XILINX_TB_WATCHDOG
+ hw_watchdog_disable();
+#endif
+
puts ("Reseting board\n");
__asm__ __volatile__ (" mts rmsr, r0;" \
"bra r0");
Available for i.mx31/35/5x/6x to service the watchdog. This is not
automatically set because some boards (vision2) still need to define
their own hw_watchdog_reset routine.
+
+CONFIG_XILINX_TB_WATCHDOG
+ Available for Xilinx Axi platforms to service timebase watchdog timer.
endif
COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
COBJS-$(CONFIG_S5P) += s5p_wdt.o
+COBJS-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * Copyright (c) 2011-2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/microblaze_intc.h>
+#include <asm/processor.h>
+#include <watchdog.h>
+
+#define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status Mask */
+#define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state Mask */
+#define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 Mask*/
+#define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 Mask */
+
+struct watchdog_regs {
+ u32 twcsr0; /* 0x0 */
+ u32 twcsr1; /* 0x4 */
+ u32 tbr; /* 0x8 */
+};
+
+#define watchdog_base ((struct watchdog_regs *) CONFIG_WATCHDOG_BASEADDR)
+
+void hw_watchdog_reset(void)
+{
+ u32 reg;
+
+ /* Read the current contents of TCSR0 */
+ reg = readl(&watchdog_base->twcsr0);
+
+ /* Clear the watchdog WDS bit */
+ if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK)) {
+ writel(reg | XWT_CSR0_WDS_MASK, &watchdog_base->twcsr0);
+ }
+}
+
+void hw_watchdog_disable(void)
+{
+ u32 reg;
+
+ /* Read the current contents of TCSR0 */
+ reg = readl(&watchdog_base->twcsr0);
+
+ writel(reg & ~XWT_CSR0_EWDT1_MASK, &watchdog_base->twcsr0);
+ writel(~XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
+
+ puts("Watchdog disabled!\n");
+}
+
+static void hw_watchdog_isr(void *arg)
+{
+ hw_watchdog_reset();
+}
+
+int hw_watchdog_init(void)
+{
+ int ret;
+
+ writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
+ &watchdog_base->twcsr0);
+ writel(XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
+
+ ret = install_interrupt_handler(CONFIG_WATCHDOG_IRQ,
+ hw_watchdog_isr, NULL);
+ if (ret)
+ return 1;
+
+ return 0;
+}
# error Please setup TIMER in BSP
#endif
+#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
+# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
+# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
+# define CONFIG_HW_WATCHDOG 1
+# define CONFIG_XILINX_TB_WATCHDOG 1
+#endif
+
/*
* memory layout - Example
* TEXT_BASE = 0x1200_0000;
projects / thirdparty / u-boot.git / commitdiff
