arm64: dts: imx8mp-evk: Add usdhc1 for SDIO WiFi support

Add usdhc1 to support M.2 SDIO WiFi on i.MX8MP EVK board.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 70897289680c7482b7898363fc54db507451146c..aedc099377161bc21239486e6363c4af0617ac41 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -134,7 +134,7 @@
                enable-active-high;
        };
 
-       reg_pcie0: regulator-pcie {
+       reg_m2_wlan: reg_pcie0: regulator-pcie {
                compatible = "regulator-fixed";
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_pcie0_reg>;
@@ -250,6 +250,13 @@
                };
        };
 
+       usdhc1_pwrseq: usdhc1_pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_usdhc1_pwrseq>;
+               reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+       };
+
        reserved-memory {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -862,6 +869,19 @@
        status = "okay";
 };
 
+&usdhc1 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+       keep-power-in-suspend;
+       non-removable;
+       wakeup-source;
+       mmc-pwrseq = <&usdhc1_pwrseq>;
+       vmmc-supply = <&reg_m2_wlan>;
+       status = "okay";
+};
+
 &usdhc2 {
        assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
        assigned-clock-rates = <400000000>;
@@ -1168,6 +1188,45 @@
                >;
        };
 
+       pinctrl_usdhc1: usdhc1grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK        0x190
+                       MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD        0x1d0
+                       MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0    0x1d0
+                       MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1    0x1d0
+                       MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2    0x1d0
+                       MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3    0x1d0
+               >;
+       };
+
+       pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK        0x194
+                       MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD        0x1d4
+                       MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0    0x1d4
+                       MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1    0x1d4
+                       MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2    0x1d4
+                       MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3    0x1d4
+               >;
+       };
+
+       pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK        0x196
+                       MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD        0x1d6
+                       MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0    0x1d6
+                       MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1    0x1d6
+                       MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2    0x1d6
+                       MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3    0x1d6
+               >;
+       };
+
+       pinctrl_usdhc1_pwrseq: usdhc1pwrseqgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10    0x140
+               >;
+       };
+
        pinctrl_usdhc2: usdhc2grp {
                fsl,pins = <
                        MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x190