perf: imx_perf: fix counter start and config sequence

[ Upstream commit ac9aa295f7a89d38656739628796f086f0b160e2 ]

In current driver, the counter will start firstly and then be configured.
This sequence is not correct for AXI filter events since the correct
AXI_MASK and AXI_ID are not set yet. Then the results may be inaccurate.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Fixes: 55691f99d417 ("drivers/perf: imx_ddr: Add support for NXP i.MX9 SoC DDRC PMU driver")
cc: stable@vger.kernel.org
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Link: https://lore.kernel.org/r/20240529080358.703784-5-xu.yang_2@nxp.com
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
index 72c2d3074cded0698667cdc1c96a8fd687eb1d22..98af97750a6e3ba0d40c03ad5a9cd9e590e7ff6e 100644 (file)
--- a/drivers/perf/fsl_imx9_ddr_perf.c
+++ b/drivers/perf/fsl_imx9_ddr_perf.c
@@ -476,12 +476,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
        hwc->idx = counter;
        hwc->state |= PERF_HES_STOPPED;
 
-       if (flags & PERF_EF_START)
-               ddr_perf_event_start(event, flags);
-
        /* read trans, write trans, read beat */
        ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2);
 
+       if (flags & PERF_EF_START)
+               ddr_perf_event_start(event, flags);
+
        return 0;
 }