select CPU_V7
select SUPPORT_SPL
-config TARGET_XILINX_ZYNQMP
+config ARCH_ZYNQMP
bool "Support Xilinx ZynqMP Platform"
select ARM64
obj-y += transition.o
obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
-obj-$(CONFIG_TARGET_XILINX_ZYNQMP) += zynqmp/
+obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
-if TARGET_XILINX_ZYNQMP
+if ARCH_ZYNQMP
+
+choice
+ prompt "Xilinx ZynqMP board select"
+
+config TARGET_ZYNQMP_EP
+ bool "ZynqMP EP Board"
+
+endchoice
config SYS_BOARD
default "zynqmp"
default "zynqmp"
config SYS_CONFIG_NAME
- default "xilinx_zynqmp"
+ default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP
endif
-XILINX_ZYNQMP BOARD
+XILINX_ZYNQMP_EP BOARD
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
F: board/xilinx/zynqmp/
F: include/configs/xilinx_zynqmp.h
-F: configs/xilinx_zynqmp_defconfig
+F: include/configs/xilinx_zynqmp_ep.h
+F: configs/xilinx_zynqmp_ep_defconfig
CONFIG_ARM=y
-CONFIG_TARGET_XILINX_ZYNQMP=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep"
CONFIG_CMD_BDI=y
CONFIG_CMD_BOOTD=y
CONFIG_CMD_RUN=y
CONFIG_CMD_TIME=y
CONFIG_CMD_MISC=y
CONFIG_CMD_TIMER=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp"
{"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
{"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
{"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
-#ifdef CONFIG_TARGET_XILINX_ZYNQMP
+#ifdef CONFIG_ARCH_ZYNQMP
{"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR},
#else
{"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
-#ifdef CONFIG_TARGET_XILINX_ZYNQMP
+#ifdef CONFIG_ARM64
#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0001C0000 /* Div pclk by 224, 540MHz */
#else
#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
#endif
#define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
-#ifdef CONFIG_TARGET_XILINX_ZYNQMP
+#ifdef CONFIG_ARM64
# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
#else
# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
priv->init++;
}
-#ifdef CONFIG_TARGET_XILINX_ZYNQMP
+#ifdef CONFIG_ARM64
if (!priv->init) {
#endif
phy_detection(dev);
clk_rate = ZYNQ_GEM_FREQUENCY_10;
break;
}
-#ifdef CONFIG_TARGET_XILINX_ZYNQMP
+#ifdef CONFIG_ARM64
}
#endif
-#ifndef CONFIG_TARGET_XILINX_ZYNQMP
+#ifndef CONFIG_ARM64
/* Change the rclk and clk only not using EMIO interface */
if (!priv->emio)
zynq_slcr_gem_clk_setup(dev->iobase !=
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x800000)
/* Serial setup */
-#define CONFIG_ZYNQ_SERIAL_UART0
#define CONFIG_ZYNQ_SERIAL
#define CONFIG_CONS_INDEX 0
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 4800, 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_ZYNQMP_QSPI
-#define CONFIG_ZYNQ_SDHCI0
-#define CONFIG_NAND_ARASAN
-
/* Command line configuration */
#define CONFIG_CMD_ENV
#define CONFIG_CMD_EXT2
/* max command args */
#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_ZYNQ_GEM0
-#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
-
/* Ethernet driver */
#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) || \
defined(CONFIG_ZYNQ_GEM2) || defined(CONFIG_ZYNQ_GEM3)
# define CONFIG_PHY_MARVELL
#endif
-#define CONFIG_ZYNQ_I2C0
-#define CONFIG_SYS_I2C_ZYNQ
-
/* I2C */
#if defined(CONFIG_SYS_I2C_ZYNQ)
# define CONFIG_CMD_I2C
# define CONFIG_SYS_I2C_ZYNQ_SLAVE 0
#endif
-#define CONFIG_ZYNQMP_EEPROM
-
/* EEPROM */
#ifdef CONFIG_ZYNQMP_EEPROM
# define CONFIG_CMD_EEPROM
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_CLOCKS
-#define CONFIG_AHCI
#ifdef CONFIG_AHCI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
--- /dev/null
+/*
+ * Configuration for Xilinx ZynqMP emulation
+ * platforms. See zynqmp-common.h for ZynqMP
+ * common configs
+ *
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ *
+ * Based on Configuration for Versatile Express
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_EP_H
+#define __CONFIG_ZYNQMP_EP_H
+
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
+
+#define CONFIG_ZYNQ_SERIAL_UART0
+#define CONFIG_ZYNQMP_QSPI
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_SYS_I2C_ZYNQ
+#define CONFIG_ZYNQ_EEPROM
+#define CONFIG_AHCI
+#define CONFIG_NAND_ARASAN
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_EP_H */