5.10-stable patches

added patches:
	drm-msm-dpu-always-use-mdp-device-to-scale-bandwidth.patch

diff --git a/queue-5.10/drm-msm-dpu-always-use-mdp-device-to-scale-bandwidth.patch b/queue-5.10/drm-msm-dpu-always-use-mdp-device-to-scale-bandwidth.patch
new file mode 100644 (file)
index 0000000..717d6d3
--- /dev/null
+++ b/queue-5.10/drm-msm-dpu-always-use-mdp-device-to-scale-bandwidth.patch
@@ -0,0 +1,148 @@
+From a670ff578f1fb855fedc7931fa5bbc06b567af22 Mon Sep 17 00:00:00 2001
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Date: Thu, 1 Apr 2021 05:05:33 +0300
+Subject: drm/msm/dpu: always use mdp device to scale bandwidth
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+commit a670ff578f1fb855fedc7931fa5bbc06b567af22 upstream.
+
+Currently DPU driver scales bandwidth and core clock for sc7180 only,
+while the rest of chips get static bandwidth votes. Make all chipsets
+scale bandwidth and clock per composition requirements like sc7180 does.
+Drop old voting path completely.
+
+Tested on RB3 (SDM845) and RB5 (SM8250).
+
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20210401020533.3956787-2-dmitry.baryshkov@linaro.org
+Signed-off-by: Rob Clark <robdclark@chromium.org>
+Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  |    3 -
+ drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c |   51 -------------------------------
+ 2 files changed, 2 insertions(+), 52 deletions(-)
+
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+@@ -931,8 +931,7 @@ static int dpu_kms_hw_init(struct msm_km
+               DPU_DEBUG("REG_DMA is not defined");
+       }
+ 
+-      if (of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss"))
+-              dpu_kms_parse_data_bus_icc_path(dpu_kms);
++      dpu_kms_parse_data_bus_icc_path(dpu_kms);
+ 
+       pm_runtime_get_sync(&dpu_kms->pdev->dev);
+ 
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+@@ -31,40 +31,8 @@ struct dpu_mdss {
+       void __iomem *mmio;
+       struct dss_module_power mp;
+       struct dpu_irq_controller irq_controller;
+-      struct icc_path *path[2];
+-      u32 num_paths;
+ };
+ 
+-static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev,
+-                                              struct dpu_mdss *dpu_mdss)
+-{
+-      struct icc_path *path0 = of_icc_get(dev->dev, "mdp0-mem");
+-      struct icc_path *path1 = of_icc_get(dev->dev, "mdp1-mem");
+-
+-      if (IS_ERR_OR_NULL(path0))
+-              return PTR_ERR_OR_ZERO(path0);
+-
+-      dpu_mdss->path[0] = path0;
+-      dpu_mdss->num_paths = 1;
+-
+-      if (!IS_ERR_OR_NULL(path1)) {
+-              dpu_mdss->path[1] = path1;
+-              dpu_mdss->num_paths++;
+-      }
+-
+-      return 0;
+-}
+-
+-static void dpu_mdss_icc_request_bw(struct msm_mdss *mdss)
+-{
+-      struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
+-      int i;
+-      u64 avg_bw = dpu_mdss->num_paths ? MAX_BW / dpu_mdss->num_paths : 0;
+-
+-      for (i = 0; i < dpu_mdss->num_paths; i++)
+-              icc_set_bw(dpu_mdss->path[i], avg_bw, kBps_to_icc(MAX_BW));
+-}
+-
+ static void dpu_mdss_irq(struct irq_desc *desc)
+ {
+       struct dpu_mdss *dpu_mdss = irq_desc_get_handler_data(desc);
+@@ -178,8 +146,6 @@ static int dpu_mdss_enable(struct msm_md
+       struct dss_module_power *mp = &dpu_mdss->mp;
+       int ret;
+ 
+-      dpu_mdss_icc_request_bw(mdss);
+-
+       ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
+       if (ret) {
+               DPU_ERROR("clock enable failed, ret:%d\n", ret);
+@@ -213,15 +179,12 @@ static int dpu_mdss_disable(struct msm_m
+ {
+       struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
+       struct dss_module_power *mp = &dpu_mdss->mp;
+-      int ret, i;
++      int ret;
+ 
+       ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
+       if (ret)
+               DPU_ERROR("clock disable failed, ret:%d\n", ret);
+ 
+-      for (i = 0; i < dpu_mdss->num_paths; i++)
+-              icc_set_bw(dpu_mdss->path[i], 0, 0);
+-
+       return ret;
+ }
+ 
+@@ -232,7 +195,6 @@ static void dpu_mdss_destroy(struct drm_
+       struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss);
+       struct dss_module_power *mp = &dpu_mdss->mp;
+       int irq;
+-      int i;
+ 
+       pm_runtime_suspend(dev->dev);
+       pm_runtime_disable(dev->dev);
+@@ -242,9 +204,6 @@ static void dpu_mdss_destroy(struct drm_
+       msm_dss_put_clk(mp->clk_config, mp->num_clk);
+       devm_kfree(&pdev->dev, mp->clk_config);
+ 
+-      for (i = 0; i < dpu_mdss->num_paths; i++)
+-              icc_put(dpu_mdss->path[i]);
+-
+       if (dpu_mdss->mmio)
+               devm_iounmap(&pdev->dev, dpu_mdss->mmio);
+       dpu_mdss->mmio = NULL;
+@@ -276,12 +235,6 @@ int dpu_mdss_init(struct drm_device *dev
+ 
+       DRM_DEBUG("mapped mdss address space @%pK\n", dpu_mdss->mmio);
+ 
+-      if (!of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss")) {
+-              ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss);
+-              if (ret)
+-                      return ret;
+-      }
+-
+       mp = &dpu_mdss->mp;
+       ret = msm_dss_parse_clock(pdev, mp);
+       if (ret) {
+@@ -307,8 +260,6 @@ int dpu_mdss_init(struct drm_device *dev
+ 
+       pm_runtime_enable(dev->dev);
+ 
+-      dpu_mdss_icc_request_bw(priv->mdss);
+-
+       return ret;
+ 
+ irq_error:

diff --git a/queue-5.10/series b/queue-5.10/series
index bb3e4db822399f52aa3dc3ac38dababd45eaa0c8..1f72e9f841e7e6cb7b6bf99361ab5613cf47f61d 100644 (file)
--- a/queue-5.10/series
+++ b/queue-5.10/series
@@ -123,3 +123,4 @@ btrfs-fixup-error-handling-in-fixup_inode_link_counts.patch
 btrfs-abort-in-rename_exchange-if-we-fail-to-insert-the-second-ref.patch
 btrfs-fix-deadlock-when-cloning-inline-extents-and-low-on-available-space.patch
 mm-hugetlb-fix-simple-resv_huge_pages-underflow-on-u.patch
+drm-msm-dpu-always-use-mdp-device-to-scale-bandwidth.patch