clk: meson-g12a: add missing fclk_div2 to spicc

commit daf004f87c3520c414992893e2eadd5db5f86a5a upstream.

SPICC is missing fclk_div2, which means fclk_div5 and fclk_div7 indexes
are wrong on this clock. This causes the spicc module to output sclk at
2.5x the expected rate when clock index 3 is picked.

Adding the missing fclk_div2 resolves this.

[jbrunet: amended commit description]
Fixes: a18c8e0b7697 ("clk: meson: g12a: add support for the SPICC SCLK Source clocks")
Cc: stable@vger.kernel.org # 6.1
Signed-off-by: Da Xue <da@libre.computer>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20250512142617.2175291-1-da@libre.computer
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 3280b7410a13f05c2e8935d3284a513d7c7afaeb..d6b42cd9c9135b1b979f347323fcec231b55ac3d 100644 (file)
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -3906,6 +3906,7 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = {
        { .hw = &g12a_clk81.hw },
        { .hw = &g12a_fclk_div4.hw },
        { .hw = &g12a_fclk_div3.hw },
+       { .hw = &g12a_fclk_div2.hw },
        { .hw = &g12a_fclk_div5.hw },
        { .hw = &g12a_fclk_div7.hw },
 };