From: Greg Kroah-Hartman Date: Fri, 21 Jul 2023 04:45:40 +0000 (+0200) Subject: 6.1-stable patches X-Git-Tag: v5.15.121~77 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=01d61d3e5c11ef43d9e24d8cd83e33a1d365f335;p=thirdparty%2Fkernel%2Fstable-queue.git 6.1-stable patches added patches: kasan-add-kasan_tag_mismatch-prototype.patch mtd-rawnand-meson-fix-unaligned-dma-buffers-handling.patch net-bcmgenet-ensure-mdio-unregistration-has-clocks-enabled.patch net-phy-dp83td510-fix-kernel-stall-during-netboot-in-dp83td510e-phy-driver.patch pinctrl-amd-add-fields-for-interrupt-status-and-wake-status.patch pinctrl-amd-adjust-debugfs-output.patch pinctrl-amd-detect-and-mask-spurious-interrupts.patch pinctrl-amd-detect-internal-gpio0-debounce-handling.patch pinctrl-amd-drop-pull-up-select-configuration.patch pinctrl-amd-fix-mistake-in-handling-clearing-pins-at-startup.patch pinctrl-amd-only-use-special-debounce-behavior-for-gpio-0.patch pinctrl-amd-revert-pinctrl-amd-disable-and-mask-interrupts-on-probe.patch pinctrl-amd-unify-debounce-handling-into-amd_pinconf_set.patch pinctrl-amd-use-amd_pinconf_set-for-all-config-options.patch tpm-do-not-remap-from-acpi-resources-again-for-pluton-tpm.patch tpm-return-false-from-tpm_amd_is_rng_defective-on-non-x86-platforms.patch tpm-tis_i2c-limit-read-bursts-to-i2c_smbus_block_max-32-bytes.patch tpm-tis_i2c-limit-write-bursts-to-i2c_smbus_block_max-32-bytes.patch tpm-tpm_vtpm_proxy-fix-a-race-condition-in-dev-vtpmx-creation.patch tracing-user_events-fix-incorrect-return-value-for-writing-operation-when-events-are-disabled.patch --- diff --git a/queue-6.1/kasan-add-kasan_tag_mismatch-prototype.patch b/queue-6.1/kasan-add-kasan_tag_mismatch-prototype.patch new file mode 100644 index 00000000000..2155008a390 --- /dev/null +++ b/queue-6.1/kasan-add-kasan_tag_mismatch-prototype.patch @@ -0,0 +1,43 @@ +From fb646a4cd3f0ff27d19911bef7b6622263723df6 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Tue, 9 May 2023 16:57:20 +0200 +Subject: kasan: add kasan_tag_mismatch prototype + +From: Arnd Bergmann + +commit fb646a4cd3f0ff27d19911bef7b6622263723df6 upstream. + +The kasan sw-tags implementation contains one function that is only called +from assembler and has no prototype in a header. This causes a W=1 +warning: + +mm/kasan/sw_tags.c:171:6: warning: no previous prototype for 'kasan_tag_mismatch' [-Wmissing-prototypes] + 171 | void kasan_tag_mismatch(unsigned long addr, unsigned long access_info, + +Add a prototype in the local header to get a clean build. + +Link: https://lkml.kernel.org/r/20230509145735.9263-1-arnd@kernel.org +Signed-off-by: Arnd Bergmann +Cc: Alexander Potapenko +Cc: Andrey Konovalov +Cc: Andrey Ryabinin +Cc: Dmitry Vyukov +Cc: Marco Elver +Cc: Vincenzo Frascino +Cc: +Signed-off-by: Andrew Morton +Signed-off-by: Greg Kroah-Hartman +--- + mm/kasan/kasan.h | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/mm/kasan/kasan.h ++++ b/mm/kasan/kasan.h +@@ -629,4 +629,7 @@ void __hwasan_storeN_noabort(unsigned lo + + void __hwasan_tag_memory(unsigned long addr, u8 tag, unsigned long size); + ++void kasan_tag_mismatch(unsigned long addr, unsigned long access_info, ++ unsigned long ret_ip); ++ + #endif /* __MM_KASAN_KASAN_H */ diff --git a/queue-6.1/mtd-rawnand-meson-fix-unaligned-dma-buffers-handling.patch b/queue-6.1/mtd-rawnand-meson-fix-unaligned-dma-buffers-handling.patch new file mode 100644 index 00000000000..51761fbfe6c --- /dev/null +++ b/queue-6.1/mtd-rawnand-meson-fix-unaligned-dma-buffers-handling.patch @@ -0,0 +1,44 @@ +From 98480a181a08ceeede417e5b28f6d0429d8ae156 Mon Sep 17 00:00:00 2001 +From: Arseniy Krasnov +Date: Thu, 15 Jun 2023 11:08:15 +0300 +Subject: mtd: rawnand: meson: fix unaligned DMA buffers handling + +From: Arseniy Krasnov + +commit 98480a181a08ceeede417e5b28f6d0429d8ae156 upstream. + +Meson NAND controller requires 8 bytes alignment for DMA addresses, +otherwise it "aligns" passed address by itself thus accessing invalid +location in the provided buffer. This patch makes unaligned buffers to +be reallocated to become valid. + +Fixes: 8fae856c5350 ("mtd: rawnand: meson: add support for Amlogic NAND flash controller") +Cc: +Signed-off-by: Arseniy Krasnov +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20230615080815.3291006-1-AVKrasnov@sberdevices.ru +Signed-off-by: Greg Kroah-Hartman +--- + drivers/mtd/nand/raw/meson_nand.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/mtd/nand/raw/meson_nand.c ++++ b/drivers/mtd/nand/raw/meson_nand.c +@@ -76,6 +76,7 @@ + #define GENCMDIADDRH(aih, addr) ((aih) | (((addr) >> 16) & 0xffff)) + + #define DMA_DIR(dir) ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N) ++#define DMA_ADDR_ALIGN 8 + + #define ECC_CHECK_RETURN_FF (-1) + +@@ -842,6 +843,9 @@ static int meson_nfc_read_oob(struct nan + + static bool meson_nfc_is_buffer_dma_safe(const void *buffer) + { ++ if ((uintptr_t)buffer % DMA_ADDR_ALIGN) ++ return false; ++ + if (virt_addr_valid(buffer) && (!object_is_on_stack(buffer))) + return true; + return false; diff --git a/queue-6.1/net-bcmgenet-ensure-mdio-unregistration-has-clocks-enabled.patch b/queue-6.1/net-bcmgenet-ensure-mdio-unregistration-has-clocks-enabled.patch new file mode 100644 index 00000000000..334a16791b0 --- /dev/null +++ b/queue-6.1/net-bcmgenet-ensure-mdio-unregistration-has-clocks-enabled.patch @@ -0,0 +1,39 @@ +From 1b5ea7ffb7a3bdfffb4b7f40ce0d20a3372ee405 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Thu, 22 Jun 2023 03:31:07 -0700 +Subject: net: bcmgenet: Ensure MDIO unregistration has clocks enabled + +From: Florian Fainelli + +commit 1b5ea7ffb7a3bdfffb4b7f40ce0d20a3372ee405 upstream. + +With support for Ethernet PHY LEDs having been added, while +unregistering a MDIO bus and its child device liks PHYs there may be +"late" accesses to the MDIO bus. One typical use case is setting the PHY +LEDs brightness to OFF for instance. + +We need to ensure that the MDIO bus controller remains entirely +functional since it runs off the main GENET adapter clock. + +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/all/20230617155500.4005881-1-andrew@lunn.ch/ +Fixes: 9a4e79697009 ("net: bcmgenet: utilize generic Broadcom UniMAC MDIO controller driver") +Signed-off-by: Florian Fainelli +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/20230622103107.1760280-1-florian.fainelli@broadcom.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Greg Kroah-Hartman +--- + drivers/net/ethernet/broadcom/genet/bcmmii.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/net/ethernet/broadcom/genet/bcmmii.c ++++ b/drivers/net/ethernet/broadcom/genet/bcmmii.c +@@ -664,5 +664,7 @@ void bcmgenet_mii_exit(struct net_device + if (of_phy_is_fixed_link(dn)) + of_phy_deregister_fixed_link(dn); + of_node_put(priv->phy_dn); ++ clk_prepare_enable(priv->clk); + platform_device_unregister(priv->mii_pdev); ++ clk_disable_unprepare(priv->clk); + } diff --git a/queue-6.1/net-phy-dp83td510-fix-kernel-stall-during-netboot-in-dp83td510e-phy-driver.patch b/queue-6.1/net-phy-dp83td510-fix-kernel-stall-during-netboot-in-dp83td510e-phy-driver.patch new file mode 100644 index 00000000000..49c0dfc44c0 --- /dev/null +++ b/queue-6.1/net-phy-dp83td510-fix-kernel-stall-during-netboot-in-dp83td510e-phy-driver.patch @@ -0,0 +1,99 @@ +From fc0649395dca81f2b3b02d9b248acb38cbcee55c Mon Sep 17 00:00:00 2001 +From: Oleksij Rempel +Date: Wed, 21 Jun 2023 06:38:48 +0200 +Subject: net: phy: dp83td510: fix kernel stall during netboot in DP83TD510E PHY driver + +From: Oleksij Rempel + +commit fc0649395dca81f2b3b02d9b248acb38cbcee55c upstream. + +Fix an issue where the kernel would stall during netboot, showing the +"sched: RT throttling activated" message. This stall was triggered by +the behavior of the mii_interrupt bit (Bit 7 - DP83TD510E_STS_MII_INT) +in the DP83TD510E's PHY_STS Register (Address = 0x10). The DP83TD510E +datasheet (2020) states that the bit clears on write, however, in +practice, the bit clears on read. + +This discrepancy had significant implications on the driver's interrupt +handling. The PHY_STS Register was used by handle_interrupt() to check +for pending interrupts and by read_status() to get the current link +status. The call to read_status() was unintentionally clearing the +mii_interrupt status bit without deasserting the IRQ pin, causing +handle_interrupt() to miss other pending interrupts. This issue was most +apparent during netboot. + +The fix refrains from using the PHY_STS Register for interrupt handling. +Instead, we now solely rely on the INTERRUPT_REG_1 Register (Address = +0x12) and INTERRUPT_REG_2 Register (Address = 0x13) for this purpose. +These registers directly influence the IRQ pin state and are latched +high until read. + +Note: The INTERRUPT_REG_2 Register (Address = 0x13) exists and can also +be used for interrupt handling, specifically for "Aneg page received +interrupt" and "Polarity change interrupt". However, these features are +currently not supported by this driver. + +Fixes: 165cd04fe253 ("net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY") +Cc: +Signed-off-by: Oleksij Rempel +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/20230621043848.3806124-1-o.rempel@pengutronix.de +Signed-off-by: Jakub Kicinski +Signed-off-by: Greg Kroah-Hartman +--- + drivers/net/phy/dp83td510.c | 23 +++++------------------ + 1 file changed, 5 insertions(+), 18 deletions(-) + +--- a/drivers/net/phy/dp83td510.c ++++ b/drivers/net/phy/dp83td510.c +@@ -12,6 +12,11 @@ + + /* MDIO_MMD_VEND2 registers */ + #define DP83TD510E_PHY_STS 0x10 ++/* Bit 7 - mii_interrupt, active high. Clears on read. ++ * Note: Clearing does not necessarily deactivate IRQ pin if interrupts pending. ++ * This differs from the DP83TD510E datasheet (2020) which states this bit ++ * clears on write 0. ++ */ + #define DP83TD510E_STS_MII_INT BIT(7) + #define DP83TD510E_LINK_STATUS BIT(0) + +@@ -53,12 +58,6 @@ static int dp83td510_config_intr(struct + int ret; + + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { +- /* Clear any pending interrupts */ +- ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PHY_STS, +- 0x0); +- if (ret) +- return ret; +- + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, + DP83TD510E_INTERRUPT_REG_1, + DP83TD510E_INT1_LINK_EN); +@@ -81,10 +80,6 @@ static int dp83td510_config_intr(struct + DP83TD510E_GENCFG_INT_EN); + if (ret) + return ret; +- +- /* Clear any pending interrupts */ +- ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PHY_STS, +- 0x0); + } + + return ret; +@@ -94,14 +89,6 @@ static irqreturn_t dp83td510_handle_inte + { + int ret; + +- ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PHY_STS); +- if (ret < 0) { +- phy_error(phydev); +- return IRQ_NONE; +- } else if (!(ret & DP83TD510E_STS_MII_INT)) { +- return IRQ_NONE; +- } +- + /* Read the current enabled interrupts */ + ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_INTERRUPT_REG_1); + if (ret < 0) { diff --git a/queue-6.1/pinctrl-amd-add-fields-for-interrupt-status-and-wake-status.patch b/queue-6.1/pinctrl-amd-add-fields-for-interrupt-status-and-wake-status.patch new file mode 100644 index 00000000000..d8f3f965585 --- /dev/null +++ b/queue-6.1/pinctrl-amd-add-fields-for-interrupt-status-and-wake-status.patch @@ -0,0 +1,75 @@ +From 010f493d90ee1dbc32fa1ce51398f20d494c20c2 Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Tue, 28 Mar 2023 12:42:31 -0500 +Subject: pinctrl: amd: Add fields for interrupt status and wake status + +From: Mario Limonciello + +commit 010f493d90ee1dbc32fa1ce51398f20d494c20c2 upstream. + +If the firmware has misconfigured a GPIO it may cause interrupt +status or wake status bits to be set and not asserted. Add these +to debug output to catch this case. + +Signed-off-by: Mario Limonciello +Link: https://lore.kernel.org/r/20230328174231.8924-3-mario.limonciello@amd.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/pinctrl-amd.c | 20 +++++++++++++++++--- + 1 file changed, 17 insertions(+), 3 deletions(-) + +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -211,6 +211,8 @@ static void amd_gpio_dbg_show(struct seq + char *wake_cntrl1; + char *wake_cntrl2; + char *pin_sts; ++ char *interrupt_sts; ++ char *wake_sts; + char *pull_up_sel; + char *orientation; + char debounce_value[40]; +@@ -243,7 +245,7 @@ static void amd_gpio_dbg_show(struct seq + continue; + } + seq_printf(s, "GPIO bank%d\n", bank); +- seq_puts(s, "gpio\tint|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n"); ++ seq_puts(s, "gpio\t int|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n"); + for (; i < pin_num; i++) { + seq_printf(s, "#%d\t", i); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); +@@ -274,12 +276,18 @@ static void amd_gpio_dbg_show(struct seq + else + interrupt_mask = "😷"; + +- seq_printf(s, "%s| %s| %s|", ++ if (pin_reg & BIT(INTERRUPT_STS_OFF)) ++ interrupt_sts = "🔥"; ++ else ++ interrupt_sts = " "; ++ ++ seq_printf(s, "%s %s| %s| %s|", ++ interrupt_sts, + interrupt_mask, + active_level, + level_trig); + } else +- seq_puts(s, " ∅| | |"); ++ seq_puts(s, " ∅| | |"); + + if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) + wake_cntrl0 = "⏰"; +@@ -305,6 +313,12 @@ static void amd_gpio_dbg_show(struct seq + wake_cntrlz = " "; + seq_printf(s, "%s|", wake_cntrlz); + ++ if (pin_reg & BIT(WAKE_STS_OFF)) ++ wake_sts = "🔥"; ++ else ++ wake_sts = " "; ++ seq_printf(s, " %s|", wake_sts); ++ + if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { + if (pin_reg & BIT(PULL_UP_SEL_OFF)) + pull_up_sel = "8k"; diff --git a/queue-6.1/pinctrl-amd-adjust-debugfs-output.patch b/queue-6.1/pinctrl-amd-adjust-debugfs-output.patch new file mode 100644 index 00000000000..b4cb7fa90c9 --- /dev/null +++ b/queue-6.1/pinctrl-amd-adjust-debugfs-output.patch @@ -0,0 +1,181 @@ +From 75358cf3319d5fed595946019deda5c2c26a203d Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Tue, 28 Mar 2023 12:42:30 -0500 +Subject: pinctrl: amd: Adjust debugfs output + +From: Mario Limonciello + +commit 75358cf3319d5fed595946019deda5c2c26a203d upstream. + +More fields are to be added, so to keep the display from being +too busy, adjust it. + +1) Add a header to all columns +2) Except for interrupt, when fields have no data show empty +3) Remove otherwise blank whitespace + +Signed-off-by: Mario Limonciello +Link: https://lore.kernel.org/r/20230328174231.8924-2-mario.limonciello@amd.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/pinctrl-amd.c | 76 ++++++++++++++++-------------------------- + 1 file changed, 30 insertions(+), 46 deletions(-) + +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -206,15 +206,12 @@ static void amd_gpio_dbg_show(struct seq + + char *level_trig; + char *active_level; +- char *interrupt_enable; + char *interrupt_mask; + char *wake_cntrl0; + char *wake_cntrl1; + char *wake_cntrl2; + char *pin_sts; + char *pull_up_sel; +- char *pull_up_enable; +- char *pull_down_enable; + char *orientation; + char debounce_value[40]; + char *debounce_enable; +@@ -246,6 +243,7 @@ static void amd_gpio_dbg_show(struct seq + continue; + } + seq_printf(s, "GPIO bank%d\n", bank); ++ seq_puts(s, "gpio\tint|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n"); + for (; i < pin_num; i++) { + seq_printf(s, "#%d\t", i); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); +@@ -255,7 +253,6 @@ static void amd_gpio_dbg_show(struct seq + if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { + u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & + ACTIVE_LEVEL_MASK; +- interrupt_enable = "+"; + + if (level == ACTIVE_LEVEL_HIGH) + active_level = "↑"; +@@ -272,65 +269,54 @@ static void amd_gpio_dbg_show(struct seq + else + level_trig = " edge"; + +- } else { +- interrupt_enable = "∅"; +- active_level = "∅"; +- level_trig = " ∅"; +- } ++ if (pin_reg & BIT(INTERRUPT_MASK_OFF)) ++ interrupt_mask = "😛"; ++ else ++ interrupt_mask = "😷"; + +- if (pin_reg & BIT(INTERRUPT_MASK_OFF)) +- interrupt_mask = "😛"; +- else +- interrupt_mask = "😷"; +- seq_printf(s, "int %s (%s)| active-%s| %s-⚡| ", +- interrupt_enable, ++ seq_printf(s, "%s| %s| %s|", + interrupt_mask, + active_level, + level_trig); ++ } else ++ seq_puts(s, " ∅| | |"); + + if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) + wake_cntrl0 = "⏰"; + else +- wake_cntrl0 = " ∅"; +- seq_printf(s, "S0i3 %s| ", wake_cntrl0); ++ wake_cntrl0 = " "; ++ seq_printf(s, " %s| ", wake_cntrl0); + + if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) + wake_cntrl1 = "⏰"; + else +- wake_cntrl1 = " ∅"; +- seq_printf(s, "S3 %s| ", wake_cntrl1); ++ wake_cntrl1 = " "; ++ seq_printf(s, "%s|", wake_cntrl1); + + if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) + wake_cntrl2 = "⏰"; + else +- wake_cntrl2 = " ∅"; +- seq_printf(s, "S4/S5 %s| ", wake_cntrl2); ++ wake_cntrl2 = " "; ++ seq_printf(s, " %s|", wake_cntrl2); + + if (pin_reg & BIT(WAKECNTRL_Z_OFF)) + wake_cntrlz = "⏰"; + else +- wake_cntrlz = " ∅"; +- seq_printf(s, "Z %s| ", wake_cntrlz); ++ wake_cntrlz = " "; ++ seq_printf(s, "%s|", wake_cntrlz); + + if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { +- pull_up_enable = "+"; + if (pin_reg & BIT(PULL_UP_SEL_OFF)) + pull_up_sel = "8k"; + else + pull_up_sel = "4k"; +- } else { +- pull_up_enable = "∅"; +- pull_up_sel = " "; ++ seq_printf(s, "%s ↑|", ++ pull_up_sel); ++ } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) { ++ seq_puts(s, " ↓|"); ++ } else { ++ seq_puts(s, " |"); + } +- seq_printf(s, "pull-↑ %s (%s)| ", +- pull_up_enable, +- pull_up_sel); +- +- if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) +- pull_down_enable = "+"; +- else +- pull_down_enable = "∅"; +- seq_printf(s, "pull-↓ %s| ", pull_down_enable); + + if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { + pin_sts = "output"; +@@ -345,7 +331,7 @@ static void amd_gpio_dbg_show(struct seq + else + orientation = "↓"; + } +- seq_printf(s, "%s %s| ", pin_sts, orientation); ++ seq_printf(s, "%s %s|", pin_sts, orientation); + + db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; + if (db_cntrl) { +@@ -364,19 +350,17 @@ static void amd_gpio_dbg_show(struct seq + unit = 61; + } + if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) +- debounce_enable = "b +"; ++ debounce_enable = "b"; + else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) +- debounce_enable = "↓ +"; ++ debounce_enable = "↓"; + else +- debounce_enable = "↑ +"; +- ++ debounce_enable = "↑"; ++ snprintf(debounce_value, sizeof(debounce_value), "%06u", time * unit); ++ seq_printf(s, "%s (🕑 %sus)|", debounce_enable, debounce_value); + } else { +- debounce_enable = " ∅"; +- time = 0; ++ seq_puts(s, " |"); + } +- snprintf(debounce_value, sizeof(debounce_value), "%u", time * unit); +- seq_printf(s, "debounce %s (🕑 %sus)| ", debounce_enable, debounce_value); +- seq_printf(s, " 0x%x\n", pin_reg); ++ seq_printf(s, "0x%x\n", pin_reg); + } + } + } diff --git a/queue-6.1/pinctrl-amd-detect-and-mask-spurious-interrupts.patch b/queue-6.1/pinctrl-amd-detect-and-mask-spurious-interrupts.patch new file mode 100644 index 00000000000..e860ab1c3d3 --- /dev/null +++ b/queue-6.1/pinctrl-amd-detect-and-mask-spurious-interrupts.patch @@ -0,0 +1,62 @@ +From 0cf9e48ff22e15f3f0882991f33d23ccc5ae1d01 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Kornel=20Dul=C4=99ba?= +Date: Fri, 21 Apr 2023 07:06:23 -0500 +Subject: pinctrl: amd: Detect and mask spurious interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Kornel Dulęba + +commit 0cf9e48ff22e15f3f0882991f33d23ccc5ae1d01 upstream. + +Leverage gpiochip_line_is_irq to check whether a pin has an irq +associated with it. The previous check ("irq == 0") didn't make much +sense. The irq variable refers to the pinctrl irq, and has nothing do to +with an individual pin. + +On some systems, during suspend/resume cycle, the firmware leaves +an interrupt enabled on a pin that is not used by the kernel. +Without this patch that caused an interrupt storm. + +Cc: stable@vger.kernel.org +Link: https://bugzilla.kernel.org/show_bug.cgi?id=217315 +Signed-off-by: Kornel Dulęba +Reviewed-by: Mario Limonciello +Link: https://lore.kernel.org/r/20230421120625.3366-4-mario.limonciello@amd.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/pinctrl-amd.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -660,21 +660,21 @@ static bool do_amd_gpio_irq_handler(int + * We must read the pin register again, in case the + * value was changed while executing + * generic_handle_domain_irq() above. +- * If we didn't find a mapping for the interrupt, +- * disable it in order to avoid a system hang caused +- * by an interrupt storm. ++ * If the line is not an irq, disable it in order to ++ * avoid a system hang caused by an interrupt storm. + */ + raw_spin_lock_irqsave(&gpio_dev->lock, flags); + regval = readl(regs + i); +- if (irq == 0) { +- regval &= ~BIT(INTERRUPT_ENABLE_OFF); ++ if (!gpiochip_line_is_irq(gc, irqnr + i)) { ++ regval &= ~BIT(INTERRUPT_MASK_OFF); + dev_dbg(&gpio_dev->pdev->dev, + "Disabling spurious GPIO IRQ %d\n", + irqnr + i); ++ } else { ++ ret = true; + } + writel(regval, regs + i); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); +- ret = true; + } + } + /* did not cause wake on resume context for shared IRQ */ diff --git a/queue-6.1/pinctrl-amd-detect-internal-gpio0-debounce-handling.patch b/queue-6.1/pinctrl-amd-detect-internal-gpio0-debounce-handling.patch new file mode 100644 index 00000000000..7a3f970f000 --- /dev/null +++ b/queue-6.1/pinctrl-amd-detect-internal-gpio0-debounce-handling.patch @@ -0,0 +1,77 @@ +From 968ab9261627fa305307e3935ca1a32fcddd36cb Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Fri, 21 Apr 2023 07:06:21 -0500 +Subject: pinctrl: amd: Detect internal GPIO0 debounce handling + +From: Mario Limonciello + +commit 968ab9261627fa305307e3935ca1a32fcddd36cb upstream. + +commit 4e5a04be88fe ("pinctrl: amd: disable and mask interrupts on probe") +had a mistake in loop iteration 63 that it would clear offset 0xFC instead +of 0x100. Offset 0xFC is actually `WAKE_INT_MASTER_REG`. This was +clearing bits 13 and 15 from the register which significantly changed the +expected handling for some platforms for GPIO0. + +commit b26cd9325be4 ("pinctrl: amd: Disable and mask interrupts on resume") +actually fixed this bug, but lead to regressions on Lenovo Z13 and some +other systems. This is because there was no handling in the driver for bit +15 debounce behavior. + +Quoting a public BKDG: +``` +EnWinBlueBtn. Read-write. Reset: 0. 0=GPIO0 detect debounced power button; +Power button override is 4 seconds. 1=GPIO0 detect debounced power button +in S3/S5/S0i3, and detect "pressed less than 2 seconds" and "pressed 2~10 +seconds" in S0; Power button override is 10 seconds +``` + +Cross referencing the same master register in Windows it's obvious that +Windows doesn't use debounce values in this configuration. So align the +Linux driver to do this as well. This fixes wake on lid when +WAKE_INT_MASTER_REG is properly programmed. + +Cc: stable@vger.kernel.org +Link: https://bugzilla.kernel.org/show_bug.cgi?id=217315 +Signed-off-by: Mario Limonciello +Link: https://lore.kernel.org/r/20230421120625.3366-2-mario.limonciello@amd.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/pinctrl-amd.c | 7 +++++++ + drivers/pinctrl/pinctrl-amd.h | 1 + + 2 files changed, 8 insertions(+) + +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -125,6 +125,12 @@ static int amd_gpio_set_debounce(struct + struct amd_gpio *gpio_dev = gpiochip_get_data(gc); + + raw_spin_lock_irqsave(&gpio_dev->lock, flags); ++ ++ /* Use special handling for Pin0 debounce */ ++ pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); ++ if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) ++ debounce = 0; ++ + pin_reg = readl(gpio_dev->base + offset * 4); + + if (debounce) { +@@ -219,6 +225,7 @@ static void amd_gpio_dbg_show(struct seq + char *debounce_enable; + char *wake_cntrlz; + ++ seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG)); + for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { + unsigned int time = 0; + unsigned int unit = 0; +--- a/drivers/pinctrl/pinctrl-amd.h ++++ b/drivers/pinctrl/pinctrl-amd.h +@@ -17,6 +17,7 @@ + #define AMD_GPIO_PINS_BANK3 32 + + #define WAKE_INT_MASTER_REG 0xfc ++#define INTERNAL_GPIO0_DEBOUNCE (1 << 15) + #define EOI_MASK (1 << 29) + + #define WAKE_INT_STATUS_REG0 0x2f8 diff --git a/queue-6.1/pinctrl-amd-drop-pull-up-select-configuration.patch b/queue-6.1/pinctrl-amd-drop-pull-up-select-configuration.patch new file mode 100644 index 00000000000..4d1b89bfe32 --- /dev/null +++ b/queue-6.1/pinctrl-amd-drop-pull-up-select-configuration.patch @@ -0,0 +1,86 @@ +From 3f62312d04d4c68aace9cd06fc135e09573325f3 Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Wed, 5 Jul 2023 08:30:04 -0500 +Subject: pinctrl: amd: Drop pull up select configuration +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Mario Limonciello + +commit 3f62312d04d4c68aace9cd06fc135e09573325f3 upstream. + +pinctrl-amd currently tries to program bit 19 of all GPIOs to select +either a 4kΩ or 8hΩ pull up, but this isn't what bit 19 does. Bit +19 is marked as reserved, even in the latest platforms documentation. + +Drop this programming functionality. + +Tested-by: Jan Visser +Signed-off-by: Mario Limonciello +Link: https://lore.kernel.org/r/20230705133005.577-4-mario.limonciello@amd.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/pinctrl-amd.c | 16 ++++------------ + drivers/pinctrl/pinctrl-amd.h | 1 - + 2 files changed, 4 insertions(+), 13 deletions(-) + +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -209,7 +209,6 @@ static void amd_gpio_dbg_show(struct seq + char *pin_sts; + char *interrupt_sts; + char *wake_sts; +- char *pull_up_sel; + char *orientation; + char debounce_value[40]; + char *debounce_enable; +@@ -317,14 +316,9 @@ static void amd_gpio_dbg_show(struct seq + seq_printf(s, " %s|", wake_sts); + + if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { +- if (pin_reg & BIT(PULL_UP_SEL_OFF)) +- pull_up_sel = "8k"; +- else +- pull_up_sel = "4k"; +- seq_printf(s, "%s ↑|", +- pull_up_sel); ++ seq_puts(s, " ↑ |"); + } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) { +- seq_puts(s, " ↓|"); ++ seq_puts(s, " ↓ |"); + } else { + seq_puts(s, " |"); + } +@@ -751,7 +745,7 @@ static int amd_pinconf_get(struct pinctr + break; + + case PIN_CONFIG_BIAS_PULL_UP: +- arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); ++ arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: +@@ -798,10 +792,8 @@ static int amd_pinconf_set(struct pinctr + break; + + case PIN_CONFIG_BIAS_PULL_UP: +- pin_reg &= ~BIT(PULL_UP_SEL_OFF); +- pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; + pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); +- pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; ++ pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF; + break; + + case PIN_CONFIG_DRIVE_STRENGTH: +--- a/drivers/pinctrl/pinctrl-amd.h ++++ b/drivers/pinctrl/pinctrl-amd.h +@@ -36,7 +36,6 @@ + #define WAKE_CNTRL_OFF_S4 15 + #define PIN_STS_OFF 16 + #define DRV_STRENGTH_SEL_OFF 17 +-#define PULL_UP_SEL_OFF 19 + #define PULL_UP_ENABLE_OFF 20 + #define PULL_DOWN_ENABLE_OFF 21 + #define OUTPUT_VALUE_OFF 22 diff --git a/queue-6.1/pinctrl-amd-fix-mistake-in-handling-clearing-pins-at-startup.patch b/queue-6.1/pinctrl-amd-fix-mistake-in-handling-clearing-pins-at-startup.patch new file mode 100644 index 00000000000..8f98b75ec63 --- /dev/null +++ b/queue-6.1/pinctrl-amd-fix-mistake-in-handling-clearing-pins-at-startup.patch @@ -0,0 +1,39 @@ +From a855724dc08b8cb0c13ab1e065a4922f1e5a7552 Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Fri, 21 Apr 2023 07:06:22 -0500 +Subject: pinctrl: amd: Fix mistake in handling clearing pins at startup + +From: Mario Limonciello + +commit a855724dc08b8cb0c13ab1e065a4922f1e5a7552 upstream. + +commit 4e5a04be88fe ("pinctrl: amd: disable and mask interrupts on probe") +had a mistake in loop iteration 63 that it would clear offset 0xFC instead +of 0x100. Offset 0xFC is actually `WAKE_INT_MASTER_REG`. This was +clearing bits 13 and 15 from the register which significantly changed the +expected handling for some platforms for GPIO0. + +Cc: stable@vger.kernel.org +Link: https://bugzilla.kernel.org/show_bug.cgi?id=217315 +Signed-off-by: Mario Limonciello +Link: https://lore.kernel.org/r/20230421120625.3366-3-mario.limonciello@amd.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/pinctrl-amd.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -897,9 +897,9 @@ static void amd_gpio_irq_init(struct amd + + raw_spin_lock_irqsave(&gpio_dev->lock, flags); + +- pin_reg = readl(gpio_dev->base + i * 4); ++ pin_reg = readl(gpio_dev->base + pin * 4); + pin_reg &= ~mask; +- writel(pin_reg, gpio_dev->base + i * 4); ++ writel(pin_reg, gpio_dev->base + pin * 4); + + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); + } diff --git a/queue-6.1/pinctrl-amd-only-use-special-debounce-behavior-for-gpio-0.patch b/queue-6.1/pinctrl-amd-only-use-special-debounce-behavior-for-gpio-0.patch new file mode 100644 index 00000000000..63649896c2d --- /dev/null +++ b/queue-6.1/pinctrl-amd-only-use-special-debounce-behavior-for-gpio-0.patch @@ -0,0 +1,40 @@ +From 0d5ace1a07f7e846d0f6d972af60d05515599d0b Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Wed, 5 Jul 2023 08:30:02 -0500 +Subject: pinctrl: amd: Only use special debounce behavior for GPIO 0 + +From: Mario Limonciello + +commit 0d5ace1a07f7e846d0f6d972af60d05515599d0b upstream. + +It's uncommon to use debounce on any other pin, but technically +we should only set debounce to 0 when working off GPIO0. + +Cc: stable@vger.kernel.org +Tested-by: Jan Visser +Fixes: 968ab9261627 ("pinctrl: amd: Detect internal GPIO0 debounce handling") +Signed-off-by: Mario Limonciello +Link: https://lore.kernel.org/r/20230705133005.577-2-mario.limonciello@amd.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/pinctrl-amd.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -127,9 +127,11 @@ static int amd_gpio_set_debounce(struct + raw_spin_lock_irqsave(&gpio_dev->lock, flags); + + /* Use special handling for Pin0 debounce */ +- pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); +- if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) +- debounce = 0; ++ if (offset == 0) { ++ pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); ++ if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) ++ debounce = 0; ++ } + + pin_reg = readl(gpio_dev->base + offset * 4); + diff --git a/queue-6.1/pinctrl-amd-revert-pinctrl-amd-disable-and-mask-interrupts-on-probe.patch b/queue-6.1/pinctrl-amd-revert-pinctrl-amd-disable-and-mask-interrupts-on-probe.patch new file mode 100644 index 00000000000..2966af52d17 --- /dev/null +++ b/queue-6.1/pinctrl-amd-revert-pinctrl-amd-disable-and-mask-interrupts-on-probe.patch @@ -0,0 +1,79 @@ +From 65f6c7c91cb2ebacbf155e0f881f81e79f90d138 Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Fri, 21 Apr 2023 07:06:24 -0500 +Subject: pinctrl: amd: Revert "pinctrl: amd: disable and mask interrupts on probe" + +From: Mario Limonciello + +commit 65f6c7c91cb2ebacbf155e0f881f81e79f90d138 upstream. + +commit 4e5a04be88fe ("pinctrl: amd: disable and mask interrupts on probe") +was well intentioned to mask a firmware issue on a surface laptop, but it +has a few problems: +1. It had a bug in the loop handling for iteration 63 that lead to other + problems with GPIO0 handling. +2. It disables interrupts that are used internally by the SOC but masked + by default. +3. It masked a real firmware problem in some chromebooks that should have + been caught during development but wasn't. + +There has been a lot of other development around s2idle; particularly +around handling of the spurious wakeups. If there is still a problem on +the original reported surface laptop it should be avoided by adding a quirk +to gpiolib-acpi for that system instead. + +Signed-off-by: Mario Limonciello +Link: https://lore.kernel.org/r/20230421120625.3366-5-mario.limonciello@amd.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/pinctrl-amd.c | 31 ------------------------------- + 1 file changed, 31 deletions(-) + +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -877,34 +877,6 @@ static const struct pinconf_ops amd_pinc + .pin_config_group_set = amd_pinconf_group_set, + }; + +-static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) +-{ +- struct pinctrl_desc *desc = gpio_dev->pctrl->desc; +- unsigned long flags; +- u32 pin_reg, mask; +- int i; +- +- mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | +- BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | +- BIT(WAKE_CNTRL_OFF_S4); +- +- for (i = 0; i < desc->npins; i++) { +- int pin = desc->pins[i].number; +- const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); +- +- if (!pd) +- continue; +- +- raw_spin_lock_irqsave(&gpio_dev->lock, flags); +- +- pin_reg = readl(gpio_dev->base + pin * 4); +- pin_reg &= ~mask; +- writel(pin_reg, gpio_dev->base + pin * 4); +- +- raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); +- } +-} +- + #ifdef CONFIG_PM_SLEEP + static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) + { +@@ -1142,9 +1114,6 @@ static int amd_gpio_probe(struct platfor + return PTR_ERR(gpio_dev->pctrl); + } + +- /* Disable and mask interrupts */ +- amd_gpio_irq_init(gpio_dev); +- + girq = &gpio_dev->gc.irq; + gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); + /* This will let us handle the parent IRQ in the driver */ diff --git a/queue-6.1/pinctrl-amd-unify-debounce-handling-into-amd_pinconf_set.patch b/queue-6.1/pinctrl-amd-unify-debounce-handling-into-amd_pinconf_set.patch new file mode 100644 index 00000000000..4f9e8b6ed7b --- /dev/null +++ b/queue-6.1/pinctrl-amd-unify-debounce-handling-into-amd_pinconf_set.patch @@ -0,0 +1,83 @@ +From 283c5ce7da0a676f46539094d40067ad17c4f294 Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Wed, 5 Jul 2023 08:30:05 -0500 +Subject: pinctrl: amd: Unify debounce handling into amd_pinconf_set() + +From: Mario Limonciello + +commit 283c5ce7da0a676f46539094d40067ad17c4f294 upstream. + +Debounce handling is done in two different entry points in the driver. +Unify this to make sure that it's always handled the same. + +Tested-by: Jan Visser +Signed-off-by: Mario Limonciello +Link: https://lore.kernel.org/r/20230705133005.577-5-mario.limonciello@amd.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/pinctrl-amd.c | 21 +++++---------------- + 1 file changed, 5 insertions(+), 16 deletions(-) + +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -115,16 +115,12 @@ static void amd_gpio_set_value(struct gp + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); + } + +-static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, +- unsigned debounce) ++static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset, ++ unsigned int debounce) + { + u32 time; + u32 pin_reg; + int ret = 0; +- unsigned long flags; +- struct amd_gpio *gpio_dev = gpiochip_get_data(gc); +- +- raw_spin_lock_irqsave(&gpio_dev->lock, flags); + + /* Use special handling for Pin0 debounce */ + if (offset == 0) { +@@ -183,7 +179,6 @@ static int amd_gpio_set_debounce(struct + pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); + } + writel(pin_reg, gpio_dev->base + offset * 4); +- raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); + + return ret; + } +@@ -782,9 +777,8 @@ static int amd_pinconf_set(struct pinctr + + switch (param) { + case PIN_CONFIG_INPUT_DEBOUNCE: +- pin_reg &= ~DB_TMR_OUT_MASK; +- pin_reg |= arg & DB_TMR_OUT_MASK; +- break; ++ ret = amd_gpio_set_debounce(gpio_dev, pin, arg); ++ goto out_unlock; + + case PIN_CONFIG_BIAS_PULL_DOWN: + pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); +@@ -811,6 +805,7 @@ static int amd_pinconf_set(struct pinctr + + writel(pin_reg, gpio_dev->base + pin*4); + } ++out_unlock: + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); + + return ret; +@@ -857,12 +852,6 @@ static int amd_gpio_set_config(struct gp + { + struct amd_gpio *gpio_dev = gpiochip_get_data(gc); + +- if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) { +- u32 debounce = pinconf_to_config_argument(config); +- +- return amd_gpio_set_debounce(gc, pin, debounce); +- } +- + return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1); + } + diff --git a/queue-6.1/pinctrl-amd-use-amd_pinconf_set-for-all-config-options.patch b/queue-6.1/pinctrl-amd-use-amd_pinconf_set-for-all-config-options.patch new file mode 100644 index 00000000000..84d4d253fa3 --- /dev/null +++ b/queue-6.1/pinctrl-amd-use-amd_pinconf_set-for-all-config-options.patch @@ -0,0 +1,103 @@ +From 635a750d958e158e17af0f524bedc484b27fbb93 Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Wed, 5 Jul 2023 08:30:03 -0500 +Subject: pinctrl: amd: Use amd_pinconf_set() for all config options + +From: Mario Limonciello + +commit 635a750d958e158e17af0f524bedc484b27fbb93 upstream. + +On ASUS TUF A16 it is reported that the ITE5570 ACPI device connected to +GPIO 7 is causing an interrupt storm. This issue doesn't happen on +Windows. + +Comparing the GPIO register configuration between Windows and Linux +bit 20 has been configured as a pull up on Windows, but not on Linux. +Checking GPIO declaration from the firmware it is clear it *should* have +been a pull up on Linux as well. + +``` +GpioInt (Level, ActiveLow, Exclusive, PullUp, 0x0000, + "\\_SB.GPIO", 0x00, ResourceConsumer, ,) +{ // Pin list +0x0007 +} +``` + +On Linux amd_gpio_set_config() is currently only used for programming +the debounce. Actually the GPIO core calls it with all the arguments +that are supported by a GPIO, pinctrl-amd just responds `-ENOTSUPP`. + +To solve this issue expand amd_gpio_set_config() to support the other +arguments amd_pinconf_set() supports, namely `PIN_CONFIG_BIAS_PULL_DOWN`, +`PIN_CONFIG_BIAS_PULL_UP`, and `PIN_CONFIG_DRIVE_STRENGTH`. + +Reported-by: Nik P +Reported-by: Nathan Schulte +Reported-by: Friedrich Vock +Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217336 +Reported-by: dridri85@gmail.com +Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217493 +Link: https://lore.kernel.org/linux-input/20230530154058.17594-1-friedrich.vock@gmx.de/ +Tested-by: Jan Visser +Fixes: 2956b5d94a76 ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips") +Signed-off-by: Mario Limonciello +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20230705133005.577-3-mario.limonciello@amd.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/pinctrl-amd.c | 28 +++++++++++++++------------- + 1 file changed, 15 insertions(+), 13 deletions(-) + +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -188,18 +188,6 @@ static int amd_gpio_set_debounce(struct + return ret; + } + +-static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, +- unsigned long config) +-{ +- u32 debounce; +- +- if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) +- return -ENOTSUPP; +- +- debounce = pinconf_to_config_argument(config); +- return amd_gpio_set_debounce(gc, offset, debounce); +-} +- + #ifdef CONFIG_DEBUG_FS + static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) + { +@@ -782,7 +770,7 @@ static int amd_pinconf_get(struct pinctr + } + + static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, +- unsigned long *configs, unsigned num_configs) ++ unsigned long *configs, unsigned int num_configs) + { + int i; + u32 arg; +@@ -872,6 +860,20 @@ static int amd_pinconf_group_set(struct + return 0; + } + ++static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin, ++ unsigned long config) ++{ ++ struct amd_gpio *gpio_dev = gpiochip_get_data(gc); ++ ++ if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) { ++ u32 debounce = pinconf_to_config_argument(config); ++ ++ return amd_gpio_set_debounce(gc, pin, debounce); ++ } ++ ++ return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1); ++} ++ + static const struct pinconf_ops amd_pinconf_ops = { + .pin_config_get = amd_pinconf_get, + .pin_config_set = amd_pinconf_set, diff --git a/queue-6.1/series b/queue-6.1/series index cb4d4d84e15..d2253cd8552 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -75,3 +75,23 @@ drm-amd-pm-add-abnormal-fan-detection-for-smu-13.0.0.patch f2fs-fix-the-wrong-condition-to-determine-atomic-context.patch f2fs-fix-deadlock-in-i_xattr_sem-and-inode-page-lock.patch pinctrl-amd-add-z-state-wake-control-bits.patch +pinctrl-amd-adjust-debugfs-output.patch +pinctrl-amd-add-fields-for-interrupt-status-and-wake-status.patch +pinctrl-amd-detect-internal-gpio0-debounce-handling.patch +pinctrl-amd-fix-mistake-in-handling-clearing-pins-at-startup.patch +pinctrl-amd-detect-and-mask-spurious-interrupts.patch +pinctrl-amd-revert-pinctrl-amd-disable-and-mask-interrupts-on-probe.patch +pinctrl-amd-only-use-special-debounce-behavior-for-gpio-0.patch +pinctrl-amd-use-amd_pinconf_set-for-all-config-options.patch +pinctrl-amd-drop-pull-up-select-configuration.patch +pinctrl-amd-unify-debounce-handling-into-amd_pinconf_set.patch +tpm-do-not-remap-from-acpi-resources-again-for-pluton-tpm.patch +tpm-tpm_vtpm_proxy-fix-a-race-condition-in-dev-vtpmx-creation.patch +tpm-tis_i2c-limit-read-bursts-to-i2c_smbus_block_max-32-bytes.patch +tpm-tis_i2c-limit-write-bursts-to-i2c_smbus_block_max-32-bytes.patch +tpm-return-false-from-tpm_amd_is_rng_defective-on-non-x86-platforms.patch +mtd-rawnand-meson-fix-unaligned-dma-buffers-handling.patch +net-bcmgenet-ensure-mdio-unregistration-has-clocks-enabled.patch +net-phy-dp83td510-fix-kernel-stall-during-netboot-in-dp83td510e-phy-driver.patch +kasan-add-kasan_tag_mismatch-prototype.patch +tracing-user_events-fix-incorrect-return-value-for-writing-operation-when-events-are-disabled.patch diff --git a/queue-6.1/tpm-do-not-remap-from-acpi-resources-again-for-pluton-tpm.patch b/queue-6.1/tpm-do-not-remap-from-acpi-resources-again-for-pluton-tpm.patch new file mode 100644 index 00000000000..8cffa1067fc --- /dev/null +++ b/queue-6.1/tpm-do-not-remap-from-acpi-resources-again-for-pluton-tpm.patch @@ -0,0 +1,63 @@ +From b1c1b98962d17a922989aa3b2822946bbb5c091f Mon Sep 17 00:00:00 2001 +From: Valentin David +Date: Mon, 10 Jul 2023 22:27:49 +0200 +Subject: tpm: Do not remap from ACPI resources again for Pluton TPM + +From: Valentin David + +commit b1c1b98962d17a922989aa3b2822946bbb5c091f upstream. + +For Pluton TPM devices, it was assumed that there was no ACPI memory +regions. This is not true for ASUS ROG Ally. ACPI advertises +0xfd500000-0xfd5fffff. + +Since remapping is already done in `crb_map_pluton`, remapping again +in `crb_map_io` causes EBUSY error: + +[ 3.510453] tpm_crb MSFT0101:00: can't request region for resource [mem 0xfd500000-0xfd5fffff] +[ 3.510463] tpm_crb: probe of MSFT0101:00 failed with error -16 + +Cc: stable@vger.kernel.org # v6.3+ +Fixes: 4d2732882703 ("tpm_crb: Add support for CRB devices based on Pluton") +Signed-off-by: Valentin David +Reviewed-by: Jarkko Sakkinen +Signed-off-by: Jarkko Sakkinen +Signed-off-by: Greg Kroah-Hartman +--- + drivers/char/tpm/tpm_crb.c | 19 +++++++++++-------- + 1 file changed, 11 insertions(+), 8 deletions(-) + +diff --git a/drivers/char/tpm/tpm_crb.c b/drivers/char/tpm/tpm_crb.c +index d43a0d7b97a8..1a5d09b18513 100644 +--- a/drivers/char/tpm/tpm_crb.c ++++ b/drivers/char/tpm/tpm_crb.c +@@ -563,15 +563,18 @@ static int crb_map_io(struct acpi_device *device, struct crb_priv *priv, + u32 rsp_size; + int ret; + +- INIT_LIST_HEAD(&acpi_resource_list); +- ret = acpi_dev_get_resources(device, &acpi_resource_list, +- crb_check_resource, iores_array); +- if (ret < 0) +- return ret; +- acpi_dev_free_resource_list(&acpi_resource_list); +- +- /* Pluton doesn't appear to define ACPI memory regions */ ++ /* ++ * Pluton sometimes does not define ACPI memory regions. ++ * Mapping is then done in crb_map_pluton ++ */ + if (priv->sm != ACPI_TPM2_COMMAND_BUFFER_WITH_PLUTON) { ++ INIT_LIST_HEAD(&acpi_resource_list); ++ ret = acpi_dev_get_resources(device, &acpi_resource_list, ++ crb_check_resource, iores_array); ++ if (ret < 0) ++ return ret; ++ acpi_dev_free_resource_list(&acpi_resource_list); ++ + if (resource_type(iores_array) != IORESOURCE_MEM) { + dev_err(dev, FW_BUG "TPM2 ACPI table does not define a memory resource\n"); + return -EINVAL; +-- +2.41.0 + diff --git a/queue-6.1/tpm-return-false-from-tpm_amd_is_rng_defective-on-non-x86-platforms.patch b/queue-6.1/tpm-return-false-from-tpm_amd_is_rng_defective-on-non-x86-platforms.patch new file mode 100644 index 00000000000..fdbbc353948 --- /dev/null +++ b/queue-6.1/tpm-return-false-from-tpm_amd_is_rng_defective-on-non-x86-platforms.patch @@ -0,0 +1,49 @@ +From ecff6813d2bcf0c670881a9ba3f51cb032dd405a Mon Sep 17 00:00:00 2001 +From: Jerry Snitselaar +Date: Thu, 29 Jun 2023 13:41:47 -0700 +Subject: tpm: return false from tpm_amd_is_rng_defective on non-x86 platforms + +From: Jerry Snitselaar + +commit ecff6813d2bcf0c670881a9ba3f51cb032dd405a upstream. + +tpm_amd_is_rng_defective is for dealing with an issue related to the +AMD firmware TPM, so on non-x86 architectures just have it inline and +return false. + +Cc: stable@vger.kernel.org # v6.3+ +Reported-by: Sachin Sant +Reported-by: Aneesh Kumar K. V +Closes: https://lore.kernel.org/lkml/99B81401-DB46-49B9-B321-CF832B50CAC3@linux.ibm.com/ +Fixes: f1324bbc4011 ("tpm: disable hwrng for fTPM on some AMD designs") +Signed-off-by: Jerry Snitselaar +Reviewed-by: Jarkko Sakkinen +Signed-off-by: Jarkko Sakkinen +Signed-off-by: Greg Kroah-Hartman +--- + drivers/char/tpm/tpm-chip.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/char/tpm/tpm-chip.c ++++ b/drivers/char/tpm/tpm-chip.c +@@ -515,6 +515,7 @@ static int tpm_add_legacy_sysfs(struct t + * 6.x.y.z series: 6.0.18.6 + + * 3.x.y.z series: 3.57.y.5 + + */ ++#ifdef CONFIG_X86 + static bool tpm_amd_is_rng_defective(struct tpm_chip *chip) + { + u32 val1, val2; +@@ -563,6 +564,12 @@ release: + + return true; + } ++#else ++static inline bool tpm_amd_is_rng_defective(struct tpm_chip *chip) ++{ ++ return false; ++} ++#endif /* CONFIG_X86 */ + + static int tpm_hwrng_read(struct hwrng *rng, void *data, size_t max, bool wait) + { diff --git a/queue-6.1/tpm-tis_i2c-limit-read-bursts-to-i2c_smbus_block_max-32-bytes.patch b/queue-6.1/tpm-tis_i2c-limit-read-bursts-to-i2c_smbus_block_max-32-bytes.patch new file mode 100644 index 00000000000..5f5ddebd6e5 --- /dev/null +++ b/queue-6.1/tpm-tis_i2c-limit-read-bursts-to-i2c_smbus_block_max-32-bytes.patch @@ -0,0 +1,81 @@ +From f3b70b6e3390bfdf18fdd7d278a72a12784fdcce Mon Sep 17 00:00:00 2001 +From: Alexander Sverdlin +Date: Wed, 24 May 2023 17:40:39 +0200 +Subject: tpm: tis_i2c: Limit read bursts to I2C_SMBUS_BLOCK_MAX (32) bytes + +From: Alexander Sverdlin + +commit f3b70b6e3390bfdf18fdd7d278a72a12784fdcce upstream. + +Underlying I2C bus drivers not always support longer transfers and +imx-lpi2c for instance doesn't. SLB 9673 offers 427-bytes packets. + +Visible symptoms are: + +tpm tpm0: Error left over data +tpm tpm0: tpm_transmit: tpm_recv: error -5 +tpm_tis_i2c: probe of 1-002e failed with error -5 + +Cc: stable@vger.kernel.org # v5.20+ +Fixes: bbc23a07b072 ("tpm: Add tpm_tis_i2c backend for tpm_tis_core") +Tested-by: Michael Haener +Signed-off-by: Alexander Sverdlin +Reviewed-by: Jarkko Sakkinen +Reviewed-by: Jerry Snitselaar +Signed-off-by: Jarkko Sakkinen +Signed-off-by: Greg Kroah-Hartman +--- + drivers/char/tpm/tpm_tis_i2c.c | 37 ++++++++++++++++++++-------------- + 1 file changed, 22 insertions(+), 15 deletions(-) + +diff --git a/drivers/char/tpm/tpm_tis_i2c.c b/drivers/char/tpm/tpm_tis_i2c.c +index c8c34adc14c0..106fd20d94e4 100644 +--- a/drivers/char/tpm/tpm_tis_i2c.c ++++ b/drivers/char/tpm/tpm_tis_i2c.c +@@ -189,21 +189,28 @@ static int tpm_tis_i2c_read_bytes(struct tpm_tis_data *data, u32 addr, u16 len, + int ret; + + for (i = 0; i < TPM_RETRY; i++) { +- /* write register */ +- msg.len = sizeof(reg); +- msg.buf = ® +- msg.flags = 0; +- ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg); +- if (ret < 0) +- return ret; +- +- /* read data */ +- msg.buf = result; +- msg.len = len; +- msg.flags = I2C_M_RD; +- ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg); +- if (ret < 0) +- return ret; ++ u16 read = 0; ++ ++ while (read < len) { ++ /* write register */ ++ msg.len = sizeof(reg); ++ msg.buf = ® ++ msg.flags = 0; ++ ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg); ++ if (ret < 0) ++ return ret; ++ ++ /* read data */ ++ msg.buf = result + read; ++ msg.len = len - read; ++ msg.flags = I2C_M_RD; ++ if (msg.len > I2C_SMBUS_BLOCK_MAX) ++ msg.len = I2C_SMBUS_BLOCK_MAX; ++ ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg); ++ if (ret < 0) ++ return ret; ++ read += msg.len; ++ } + + ret = tpm_tis_i2c_sanity_check_read(reg, len, result); + if (ret == 0) +-- +2.41.0 + diff --git a/queue-6.1/tpm-tis_i2c-limit-write-bursts-to-i2c_smbus_block_max-32-bytes.patch b/queue-6.1/tpm-tis_i2c-limit-write-bursts-to-i2c_smbus_block_max-32-bytes.patch new file mode 100644 index 00000000000..d66a601b22f --- /dev/null +++ b/queue-6.1/tpm-tis_i2c-limit-write-bursts-to-i2c_smbus_block_max-32-bytes.patch @@ -0,0 +1,62 @@ +From 83e7e5d89f04d1c417492940f7922bc8416a8cc4 Mon Sep 17 00:00:00 2001 +From: Alexander Sverdlin +Date: Wed, 24 May 2023 17:40:40 +0200 +Subject: tpm: tis_i2c: Limit write bursts to I2C_SMBUS_BLOCK_MAX (32) bytes + +From: Alexander Sverdlin + +commit 83e7e5d89f04d1c417492940f7922bc8416a8cc4 upstream. + +Underlying I2C bus drivers not always support longer transfers and +imx-lpi2c for instance doesn't. The fix is symmetric to previous patch +which fixed the read direction. + +Cc: stable@vger.kernel.org # v5.20+ +Fixes: bbc23a07b072 ("tpm: Add tpm_tis_i2c backend for tpm_tis_core") +Tested-by: Michael Haener +Signed-off-by: Alexander Sverdlin +Reviewed-by: Jarkko Sakkinen +Reviewed-by: Jerry Snitselaar +Signed-off-by: Jarkko Sakkinen +Signed-off-by: Greg Kroah-Hartman +--- + drivers/char/tpm/tpm_tis_i2c.c | 22 +++++++++++++++------- + 1 file changed, 15 insertions(+), 7 deletions(-) + +--- a/drivers/char/tpm/tpm_tis_i2c.c ++++ b/drivers/char/tpm/tpm_tis_i2c.c +@@ -230,19 +230,27 @@ static int tpm_tis_i2c_write_bytes(struc + struct i2c_msg msg = { .addr = phy->i2c_client->addr }; + u8 reg = tpm_tis_i2c_address_to_register(addr); + int ret; ++ u16 wrote = 0; + + if (len > TPM_BUFSIZE - 1) + return -EIO; + +- /* write register and data in one go */ + phy->io_buf[0] = reg; +- memcpy(phy->io_buf + sizeof(reg), value, len); +- +- msg.len = sizeof(reg) + len; + msg.buf = phy->io_buf; +- ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg); +- if (ret < 0) +- return ret; ++ while (wrote < len) { ++ /* write register and data in one go */ ++ msg.len = sizeof(reg) + len - wrote; ++ if (msg.len > I2C_SMBUS_BLOCK_MAX) ++ msg.len = I2C_SMBUS_BLOCK_MAX; ++ ++ memcpy(phy->io_buf + sizeof(reg), value + wrote, ++ msg.len - sizeof(reg)); ++ ++ ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg); ++ if (ret < 0) ++ return ret; ++ wrote += msg.len - sizeof(reg); ++ } + + return 0; + } diff --git a/queue-6.1/tpm-tpm_vtpm_proxy-fix-a-race-condition-in-dev-vtpmx-creation.patch b/queue-6.1/tpm-tpm_vtpm_proxy-fix-a-race-condition-in-dev-vtpmx-creation.patch new file mode 100644 index 00000000000..7ac9e6786dc --- /dev/null +++ b/queue-6.1/tpm-tpm_vtpm_proxy-fix-a-race-condition-in-dev-vtpmx-creation.patch @@ -0,0 +1,80 @@ +From f4032d615f90970d6c3ac1d9c0bce3351eb4445c Mon Sep 17 00:00:00 2001 +From: Jarkko Sakkinen +Date: Tue, 16 May 2023 01:25:54 +0300 +Subject: tpm: tpm_vtpm_proxy: fix a race condition in /dev/vtpmx creation + +From: Jarkko Sakkinen + +commit f4032d615f90970d6c3ac1d9c0bce3351eb4445c upstream. + +/dev/vtpmx is made visible before 'workqueue' is initialized, which can +lead to a memory corruption in the worst case scenario. + +Address this by initializing 'workqueue' as the very first step of the +driver initialization. + +Cc: stable@vger.kernel.org +Fixes: 6f99612e2500 ("tpm: Proxy driver for supporting multiple emulated TPMs") +Reviewed-by: Stefan Berger +Signed-off-by: Jarkko Sakkinen +Signed-off-by: Jarkko Sakkinen +Signed-off-by: Greg Kroah-Hartman +--- + drivers/char/tpm/tpm_vtpm_proxy.c | 30 +++++++----------------------- + 1 file changed, 7 insertions(+), 23 deletions(-) + +--- a/drivers/char/tpm/tpm_vtpm_proxy.c ++++ b/drivers/char/tpm/tpm_vtpm_proxy.c +@@ -683,37 +683,21 @@ static struct miscdevice vtpmx_miscdev = + .fops = &vtpmx_fops, + }; + +-static int vtpmx_init(void) +-{ +- return misc_register(&vtpmx_miscdev); +-} +- +-static void vtpmx_cleanup(void) +-{ +- misc_deregister(&vtpmx_miscdev); +-} +- + static int __init vtpm_module_init(void) + { + int rc; + +- rc = vtpmx_init(); +- if (rc) { +- pr_err("couldn't create vtpmx device\n"); +- return rc; +- } +- + workqueue = create_workqueue("tpm-vtpm"); + if (!workqueue) { + pr_err("couldn't create workqueue\n"); +- rc = -ENOMEM; +- goto err_vtpmx_cleanup; ++ return -ENOMEM; + } + +- return 0; +- +-err_vtpmx_cleanup: +- vtpmx_cleanup(); ++ rc = misc_register(&vtpmx_miscdev); ++ if (rc) { ++ pr_err("couldn't create vtpmx device\n"); ++ destroy_workqueue(workqueue); ++ } + + return rc; + } +@@ -721,7 +705,7 @@ err_vtpmx_cleanup: + static void __exit vtpm_module_exit(void) + { + destroy_workqueue(workqueue); +- vtpmx_cleanup(); ++ misc_deregister(&vtpmx_miscdev); + } + + module_init(vtpm_module_init); diff --git a/queue-6.1/tracing-user_events-fix-incorrect-return-value-for-writing-operation-when-events-are-disabled.patch b/queue-6.1/tracing-user_events-fix-incorrect-return-value-for-writing-operation-when-events-are-disabled.patch new file mode 100644 index 00000000000..954c54d236b --- /dev/null +++ b/queue-6.1/tracing-user_events-fix-incorrect-return-value-for-writing-operation-when-events-are-disabled.patch @@ -0,0 +1,37 @@ +From f6d026eea390d59787a6cdc2ef5c983d02e029d0 Mon Sep 17 00:00:00 2001 +From: sunliming +Date: Mon, 26 Jun 2023 19:13:42 +0800 +Subject: tracing/user_events: Fix incorrect return value for writing operation when events are disabled + +From: sunliming + +commit f6d026eea390d59787a6cdc2ef5c983d02e029d0 upstream. + +The writing operation return the count of writes regardless of whether events +are enabled or disabled. Switch it to return -EBADF to indicates that the event +is disabled. + +Link: https://lkml.kernel.org/r/20230626111344.19136-2-sunliming@kylinos.cn + +Cc: stable@vger.kernel.org +7f5a08c79df35 ("user_events: Add minimal support for trace_event into ftrace") +Acked-by: Beau Belgrave +Signed-off-by: sunliming +Signed-off-by: Steven Rostedt (Google) +Signed-off-by: Greg Kroah-Hartman +--- + kernel/trace/trace_events_user.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/kernel/trace/trace_events_user.c ++++ b/kernel/trace/trace_events_user.c +@@ -1456,7 +1456,8 @@ static ssize_t user_events_write_core(st + + if (unlikely(faulted)) + return -EFAULT; +- } ++ } else ++ return -EBADF; + + return ret; + }