From: Dmitry Baryshkov Date: Fri, 27 Feb 2026 18:36:44 +0000 (+0200) Subject: drm/msm/dpu: drop vbif_idx from WB configuration X-Git-Tag: v7.1-rc1~167^2~11^2~51 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=021fd8ca0cdcba3bf70601e04ea5aad22d1968b9;p=thirdparty%2Fkernel%2Fstable.git drm/msm/dpu: drop vbif_idx from WB configuration All MDP / DPU implementations except for MSM8996 use VBIF_RT (or the only VBIF) for WB2. Writeback on MSM8996 is not supported (nor planned to be supported). In order to simplify the driver, drop the field form the struct dpu_wb_cfg. Reviewed-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/707778/ Link: https://lore.kernel.org/r/20260227-drop-vbif-nrt-v1-5-2b97d0438182@oss.qualcomm.com [DB: also handled Eliza platform] Signed-off-by: Dmitry Baryshkov --- diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index b31cb6f16f33e..db79f9382f8b4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -322,7 +322,6 @@ static const struct dpu_wb_cfg sm8650_wb[] = { .format_list = wb2_formats_rgb_yuv, .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h index b0c38b2e38c4e..59caa2c2a87c4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h @@ -364,7 +364,6 @@ static const struct dpu_wb_cfg sm8750_wb[] = { .format_list = wb2_formats_rgb_yuv, .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h index f6fd79a485376..5e24309b46748 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h @@ -371,7 +371,6 @@ static const struct dpu_wb_cfg glymur_wb[] = { .format_list = wb2_formats_rgb_yuv, .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h index aeccf6f9095e3..b482a7e4e6c06 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h @@ -235,7 +235,6 @@ static const struct dpu_wb_cfg eliza_wb[] = { .format_list = wb2_formats_rgb_yuv, .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h index 02d2de6073f84..bf1940d9c9e90 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h @@ -362,7 +362,6 @@ static const struct dpu_wb_cfg kaanapali_wb[] = { .format_list = wb2_formats_rgb_yuv, .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 9f43ce8bf31b1..e61e14572affb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -280,7 +280,6 @@ static const struct dpu_wb_cfg sm8150_wb[] = { .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl = DPU_CLK_CTRL_WB2, .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 14611a3443716..fb18de029e80d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -286,7 +286,6 @@ static const struct dpu_wb_cfg sc8180x_wb[] = { .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl = DPU_CLK_CTRL_WB2, .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index 7b97e3b8630ee..ffb89a03cfade 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -246,7 +246,6 @@ static const struct dpu_wb_cfg sm7150_wb[] = { .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl = DPU_CLK_CTRL_WB2, .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index 65fbd006720d9..427ecd4cbf63d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -158,7 +158,6 @@ static const struct dpu_wb_cfg sm6150_wb[] = { .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl = DPU_CLK_CTRL_WB2, .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 2160, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index c7833ca05eb46..64be51e301591 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -137,7 +137,6 @@ static const struct dpu_wb_cfg sm6125_wb[] = { .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl = DPU_CLK_CTRL_WB2, .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 2160, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 09ca22b93e68b..c481e964fca06 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -317,7 +317,6 @@ static const struct dpu_wb_cfg sm8250_wb[] = { .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl = DPU_CLK_CTRL_WB2, .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 3adc3350f05b4..d6f7ee24ca933 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -153,7 +153,6 @@ static const struct dpu_wb_cfg sc7180_wb[] = { .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl = DPU_CLK_CTRL_WB2, .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 7b58e438f597d..dd891703e35f8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -147,7 +147,6 @@ static const struct dpu_wb_cfg sm6350_wb[] = { .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl = DPU_CLK_CTRL_WB2, .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 1920, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index a3fea0ade6888..9afdfdb3be6fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -290,7 +290,6 @@ static const struct dpu_wb_cfg sm8350_wb[] = { .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl = DPU_CLK_CTRL_WB2, .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index ce38e93c0d7e3..99b8a890fddc7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -172,7 +172,6 @@ static const struct dpu_wb_cfg sc7280_wb[] = { .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl = DPU_CLK_CTRL_WB2, .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 0271add0f2b97..bdab0ebfe1028 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -303,7 +303,6 @@ static const struct dpu_wb_cfg sm8450_wb[] = { .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl = DPU_CLK_CTRL_WB2, .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index c9dff42d8ea1a..f3d85d173c56b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -310,7 +310,6 @@ static const struct dpu_wb_cfg sa8775p_wb[] = { .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl = DPU_CLK_CTRL_WB2, .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index c0c133ffd5554..5837e252f5d23 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -298,7 +298,6 @@ static const struct dpu_wb_cfg sm8550_wb[] = { .format_list = wb2_formats_rgb_yuv, .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h index 4e1edf69b2255..9cc0b7ea3a307 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h @@ -298,7 +298,6 @@ static const struct dpu_wb_cfg sar2130p_wb[] = { .format_list = wb2_formats_rgb_yuv, .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index fce95fadefcaf..10443368f6829 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -298,7 +298,6 @@ static const struct dpu_wb_cfg x1e80100_wb[] = { .format_list = wb2_formats_rgb_yuv, .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), .xin_id = 6, - .vbif_idx = VBIF_RT, .maxlinewidth = 4096, .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 6d28f2281c765..73021aaa8d3ff 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -70,7 +70,8 @@ static void dpu_encoder_phys_wb_set_ot_limit( ot_params.height = phys_enc->cached_mode.vdisplay; ot_params.is_wfd = !dpu_encoder_helper_get_cwb_mask(phys_enc); ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode); - ot_params.vbif_idx = hw_wb->caps->vbif_idx; + /* XXX: WB on MSM8996 should use VBIF_NRT */ + ot_params.vbif_idx = VBIF_RT; ot_params.rd = false; if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp, @@ -108,7 +109,8 @@ static void dpu_encoder_phys_wb_set_qos_remap( hw_wb = phys_enc->hw_wb; memset(&qos_params, 0, sizeof(qos_params)); - qos_params.vbif_idx = hw_wb->caps->vbif_idx; + /* XXX: WB on MSM8996 should use VBIF_NRT */ + qos_params.vbif_idx = VBIF_RT; qos_params.xin_id = hw_wb->caps->xin_id; qos_params.num = hw_wb->idx - WB_0; qos_params.is_rt = dpu_encoder_helper_get_cwb_mask(phys_enc); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index c43ee4016db47..ba04ac24d5a9e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -524,7 +524,6 @@ struct dpu_intf_cfg { /** * struct dpu_wb_cfg - information of writeback blocks * @DPU_HW_BLK_INFO: refer to the description above for DPU_HW_BLK_INFO - * @vbif_idx: vbif client index * @maxlinewidth: max line width supported by writeback block * @xin_id: bus client identifier * @intr_wb_done: interrupt index for WB_DONE @@ -535,7 +534,6 @@ struct dpu_intf_cfg { struct dpu_wb_cfg { DPU_HW_BLK_INFO; unsigned long features; - u8 vbif_idx; u32 maxlinewidth; u32 xin_id; unsigned int intr_wb_done;