From: Valentina Fernandez Date: Mon, 8 Sep 2025 11:57:30 +0000 (+0100) Subject: riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes X-Git-Tag: v6.18-rc1~147^2^2~7 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=02428682b2eb5ff1669e256f8f94ee1511d22ee1;p=thirdparty%2Fkernel%2Flinux.git riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes Rename the Clock Conditioning Circuit (CCC) reference clock to match the fixed clock bindings naming recommendation. Update the reserved memory regions in the Icicle Kit common dtsi to use lowercase hex and drop the redundant status properties from the memory regions, as they are not required. Signed-off-by: Valentina Fernandez Signed-off-by: Conor Dooley --- diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi index 5c7a8ffad85bc..e01a216e6c3a8 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi @@ -53,13 +53,11 @@ ddrc_cache_lo: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; - status = "okay"; }; ddrc_cache_hi: memory@1040000000 { device_type = "memory"; reg = <0x10 0x40000000 0x0 0x40000000>; - status = "okay"; }; reserved-memory { @@ -67,8 +65,8 @@ #size-cells = <2>; ranges; - hss_payload: region@BFC00000 { - reg = <0x0 0xBFC00000 0x0 0x400000>; + hss_payload: region@bfc00000 { + reg = <0x0 0xbfc00000 0x0 0x400000>; no-map; }; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index e673b676fd1a2..71f724325578f 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -74,7 +74,7 @@ }; }; - refclk_ccc: cccrefclk { + refclk_ccc: clock-cccref { compatible = "fixed-clock"; #clock-cells = <0>; };