From: George Moussalem Date: Wed, 15 Jul 2026 06:55:24 +0000 (+0400) Subject: qualcommax: backport upstreamed patches for IPQ PWM support X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=0368dc896a2f66f2a409fbc14b68528467449c23;p=thirdparty%2Fopenwrt.git qualcommax: backport upstreamed patches for IPQ PWM support Backport upstreamed patches for IPQ PWM support and refresh following patches. Signed-off-by: George Moussalem Link: https://github.com/openwrt/openwrt/pull/24238 Signed-off-by: Robert Marko --- diff --git a/target/linux/qualcommax/patches-6.12/0140-dt-bindings-pwm-add-IPQ6018-binding.patch b/target/linux/qualcommax/patches-6.12/0076-v7.2-dt-bindings-pwm-add-IPQ6018-binding.patch similarity index 58% rename from target/linux/qualcommax/patches-6.12/0140-dt-bindings-pwm-add-IPQ6018-binding.patch rename to target/linux/qualcommax/patches-6.12/0076-v7.2-dt-bindings-pwm-add-IPQ6018-binding.patch index bba8b3457a9..cdf97724107 100644 --- a/target/linux/qualcommax/patches-6.12/0140-dt-bindings-pwm-add-IPQ6018-binding.patch +++ b/target/linux/qualcommax/patches-6.12/0076-v7.2-dt-bindings-pwm-add-IPQ6018-binding.patch @@ -1,5 +1,6 @@ +From a8cd1a1baadbfed43ac214f0bf3e26c90e3b521e Mon Sep 17 00:00:00 2001 From: Devi Priya -Date: Thu, 5 Oct 2023 21:35:48 +0530 +Date: Mon, 6 Apr 2026 22:24:38 +0200 Subject: [PATCH] dt-bindings: pwm: add IPQ6018 binding DT binding for the PWM block in Qualcomm IPQ6018 SoC. @@ -9,10 +10,17 @@ Reviewed-by: Krzysztof Kozlowski Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya +Signed-off-by: George Moussalem +Link: https://patch.msgid.link/20260406-ipq-pwm-v21-1-6ed1e868e4c2@outlook.com +Signed-off-by: Rob Herring (Arm) --- + .../bindings/pwm/qcom,ipq6018-pwm.yaml | 51 +++++++++++++++++++ + 1 file changed, 51 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml + --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml -@@ -0,0 +1,45 @@ +@@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- @@ -22,21 +30,27 @@ Signed-off-by: Devi Priya +title: Qualcomm IPQ6018 PWM controller + +maintainers: -+ - Baruch Siach ++ - George Moussalem + +properties: + compatible: -+ const: qcom,ipq6018-pwm ++ oneOf: ++ - items: ++ - enum: ++ - qcom,ipq5018-pwm ++ - qcom,ipq5332-pwm ++ - qcom,ipq9574-pwm ++ - const: qcom,ipq6018-pwm ++ - const: qcom,ipq6018-pwm + + reg: -+ description: Offset of PWM register in the TCSR block. + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": -+ const: 2 ++ const: 3 + +required: + - compatible @@ -50,11 +64,11 @@ Signed-off-by: Devi Priya + - | + #include + -+ pwm: pwm@a010 { ++ pwm: pwm@1941010 { + compatible = "qcom,ipq6018-pwm"; -+ reg = <0xa010 0x20>; ++ reg = <0x01941010 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates = <100000000>; -+ #pwm-cells = <2>; ++ #pwm-cells = <3>; + }; diff --git a/target/linux/qualcommax/patches-6.12/0141-pwm-driver-for-qualcomm-ipq6018-pwm-block.patch b/target/linux/qualcommax/patches-6.12/0077-v7.2-pwm-Driver-for-qualcomm-ipq6018-pwm-block.patch similarity index 57% rename from target/linux/qualcommax/patches-6.12/0141-pwm-driver-for-qualcomm-ipq6018-pwm-block.patch rename to target/linux/qualcommax/patches-6.12/0077-v7.2-pwm-Driver-for-qualcomm-ipq6018-pwm-block.patch index c01997a8e19..ba0a65fcbe6 100644 --- a/target/linux/qualcommax/patches-6.12/0141-pwm-driver-for-qualcomm-ipq6018-pwm-block.patch +++ b/target/linux/qualcommax/patches-6.12/0077-v7.2-pwm-Driver-for-qualcomm-ipq6018-pwm-block.patch @@ -1,21 +1,30 @@ +From c436e3e9c265a1f012008ef5da6fd28863f8025c Mon Sep 17 00:00:00 2001 From: Devi Priya -Date: Thu, 5 Oct 2023 21:35:47 +0530 -Subject: [PATCH] pwm: driver for qualcomm ipq6018 pwm block +Date: Mon, 6 Apr 2026 22:24:39 +0200 +Subject: [PATCH] pwm: Driver for qualcomm ipq6018 pwm block +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on driver from downstream Codeaurora kernel tree. Removed support for older (V1) variants because I have no access to that hardware. -Tested on IPQ6010 based hardware. +Tested on IPQ5018 and IPQ6010 based hardware. Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya +Reviewed-by: Bjorn Andersson +Signed-off-by: George Moussalem +Link: https://patch.msgid.link/20260406-ipq-pwm-v21-2-6ed1e868e4c2@outlook.com +[ukleinek: Fixed a few nitpicks as agreed on the mailing list] +Signed-off-by: Uwe Kleine-König --- drivers/pwm/Kconfig | 12 ++ drivers/pwm/Makefile | 1 + - drivers/pwm/pwm-ipq.c | 282 ++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 295 insertions(+) + drivers/pwm/pwm-ipq.c | 263 ++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 276 insertions(+) create mode 100644 drivers/pwm/pwm-ipq.c --- a/drivers/pwm/Kconfig @@ -51,10 +60,26 @@ Signed-off-by: Devi Priya obj-$(CONFIG_PWM_KEEMBAY) += pwm-keembay.o --- /dev/null +++ b/drivers/pwm/pwm-ipq.c -@@ -0,0 +1,261 @@ +@@ -0,0 +1,263 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/* + * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved. ++ * ++ * Limitations: ++ * - The PWM controller has no publicly available datasheet. ++ * - Each of the four channels is programmed via two 32-bit registers ++ * (REG0 and REG1 at 8-byte stride). ++ * - Period and duty-cycle reconfiguration is fully atomic: new divider, ++ * pre-divider, and high-duration values are latched by setting the ++ * UPDATE bit (bit 30 in REG1). The hardware applies the new settings ++ * at the beginning of the next period without disabling the output, ++ * so the currently running period is always completed. ++ * - On disable (clearing the ENABLE bit 31 in REG1), the hardware ++ * finishes the current period before stopping the output. The pin ++ * is then driven to the inactive (low) level. ++ * - Upon disabling, the hardware resets the pre-divider (PRE_DIV) and divider ++ * fields (PWM_DIV) in REG0 and REG1 to 0x0000 and 0x0001 respectively. ++ * - Only normal polarity is supported. + */ + +#include @@ -68,14 +93,9 @@ Signed-off-by: Devi Priya +#include +#include + -+/* The frequency range supported is 1 Hz to clock rate */ ++/* The frequency range supported is 1 Hz to 100 Mhz (clock rate) */ +#define IPQ_PWM_MAX_PERIOD_NS ((u64)NSEC_PER_SEC) -+ -+/* -+ * The max value specified for each field is based on the number of bits -+ * in the pwm control register for that field -+ */ -+#define IPQ_PWM_MAX_DIV 0xFFFF ++#define IPQ_PWM_MIN_PERIOD_NS 10 + +/* + * Two 32-bit registers for each PWM: REG0, and REG1. @@ -89,15 +109,21 @@ Signed-off-by: Devi Priya +#define IPQ_PWM_REG1_PRE_DIV GENMASK(15, 0) +/* + * Enable bit is set to enable output toggling in pwm device. -+ * Update bit is set to reflect the changed divider and high duration -+ * values in register. ++ * Update bit is set to trigger the change and is unset automatically ++ * to reflect the changed divider and high duration values in register. + */ +#define IPQ_PWM_REG1_UPDATE BIT(30) +#define IPQ_PWM_REG1_ENABLE BIT(31) + ++/* ++ * The max value specified for each field is based on the number of bits ++ * in the pwm control register for that field (16-bit) ++ */ ++#define IPQ_PWM_MAX_DIV FIELD_MAX(IPQ_PWM_REG0_PWM_DIV) ++ +struct ipq_pwm_chip { -+ struct clk *clk; + void __iomem *mem; ++ unsigned long clk_rate; +}; + +static struct ipq_pwm_chip *ipq_pwm_from_chip(struct pwm_chip *chip) @@ -122,111 +148,73 @@ Signed-off-by: Devi Priya + writel(val, ipq_chip->mem + off); +} + -+static void config_div_and_duty(struct pwm_device *pwm, unsigned int pre_div, -+ unsigned int pwm_div, unsigned long rate, u64 duty_ns, -+ bool enable) -+{ -+ unsigned long hi_dur; -+ unsigned long val = 0; -+ -+ /* -+ * high duration = pwm duty * (pwm div + 1) -+ * pwm duty = duty_ns / period_ns -+ */ -+ hi_dur = div64_u64(duty_ns * rate, (pre_div + 1) * NSEC_PER_SEC); -+ -+ val = FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) | -+ FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div); -+ ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val); -+ -+ val = FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div); -+ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); -+ -+ /* PWM enable toggle needs a separate write to REG1 */ -+ val |= IPQ_PWM_REG1_UPDATE; -+ if (enable) -+ val |= IPQ_PWM_REG1_ENABLE; -+ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); -+} -+ +static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(chip); -+ unsigned int pre_div, pwm_div, best_pre_div, best_pwm_div; -+ unsigned long rate = clk_get_rate(ipq_chip->clk); -+ u64 period_ns, duty_ns, period_rate; -+ u64 min_diff; ++ unsigned int pre_div, pwm_div; ++ u64 period_ns, duty_ns; ++ unsigned long val = 0; ++ unsigned long hi_dur; ++ ++ if (!state->enabled) { ++ /* clear IPQ_PWM_REG1_ENABLE */ ++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, IPQ_PWM_REG1_UPDATE); ++ return 0; ++ } + + if (state->polarity != PWM_POLARITY_NORMAL) + return -EINVAL; + -+ if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC, rate)) ++ /* ++ * Check the upper and lower bounds for the period as per ++ * hardware limits ++ */ ++ if (state->period < IPQ_PWM_MIN_PERIOD_NS) + return -ERANGE; -+ + period_ns = min(state->period, IPQ_PWM_MAX_PERIOD_NS); + duty_ns = min(state->duty_cycle, period_ns); + + /* -+ * period_ns is 1G or less. As long as rate is less than 16 GHz, -+ * period_rate does not overflow. Make that explicit. ++ * Pick the maximal value for PWM_DIV that still allows a ++ * 100% relative duty cycle. This allows a fine grained ++ * selection of duty cycles. + */ -+ if ((unsigned long long)rate > 16ULL * GIGA) -+ return -EINVAL; -+ period_rate = period_ns * rate; -+ best_pre_div = IPQ_PWM_MAX_DIV; -+ best_pwm_div = IPQ_PWM_MAX_DIV; ++ pwm_div = IPQ_PWM_MAX_DIV - 1; ++ + /* -+ * We don't need to consider pre_div values smaller than -+ * -+ * period_rate -+ * pre_div_min := ------------------------------------ -+ * NSEC_PER_SEC * (IPQ_PWM_MAX_DIV + 1) -+ * -+ * because pre_div = pre_div_min results in a better -+ * approximation. ++ * although mul_u64_u64_div_u64 returns a u64, in practice it ++ * won't overflow due to above constraints. Take the max period ++ * of 10^9 (NSEC_PER_SEC) and the pwm_div + 1 (IPQ_PWM_MAX_DIV) ++ * 10^9 * 10^8 ++ * ------------- => which fits well into a 32-bit unsigned int. ++ * 10^9 * 65,535 + */ -+ pre_div = div64_u64(period_rate, -+ (u64)NSEC_PER_SEC * (IPQ_PWM_MAX_DIV + 1)); -+ min_diff = period_rate; -+ -+ for (; pre_div <= IPQ_PWM_MAX_DIV; pre_div++) { -+ u64 remainder; -+ -+ pwm_div = div64_u64_rem(period_rate, -+ (u64)NSEC_PER_SEC * (pre_div + 1), &remainder); -+ /* pwm_div is unsigned; the check below catches underflow */ -+ pwm_div--; -+ -+ /* -+ * Swapping values for pre_div and pwm_div produces the same -+ * period length. So we can skip all settings with pre_div > -+ * pwm_div which results in bigger constraints for selecting -+ * the duty_cycle than with the two values swapped. -+ */ -+ if (pre_div > pwm_div) -+ break; -+ -+ /* -+ * Make sure we can do 100% duty cycle where -+ * hi_dur == pwm_div + 1 -+ */ -+ if (pwm_div > IPQ_PWM_MAX_DIV - 1) -+ continue; -+ -+ if (remainder < min_diff) { -+ best_pre_div = pre_div; -+ best_pwm_div = pwm_div; -+ min_diff = remainder; -+ -+ if (min_diff == 0) /* bingo */ -+ break; -+ } -+ } ++ pre_div = mul_u64_u64_div_u64(period_ns, ipq_chip->clk_rate, ++ (u64)NSEC_PER_SEC * (pwm_div + 1)); ++ ++ if (!pre_div) ++ return -ERANGE; ++ ++ pre_div -= 1; ++ ++ if (pre_div > IPQ_PWM_MAX_DIV) ++ pre_div = IPQ_PWM_MAX_DIV; ++ ++ /* pwm duty = HI_DUR * (PRE_DIV + 1) / clk_rate */ ++ hi_dur = mul_u64_u64_div_u64(duty_ns, ipq_chip->clk_rate, ++ (u64)NSEC_PER_SEC * (pre_div + 1)); ++ ++ val = FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) | ++ FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div); ++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val); + -+ /* config divider values for the closest possible frequency */ -+ config_div_and_duty(pwm, best_pre_div, best_pwm_div, -+ rate, duty_ns, state->enabled); ++ val = FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div); ++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); ++ ++ /* PWM enable toggle needs a separate write to REG1 */ ++ val |= IPQ_PWM_REG1_UPDATE | IPQ_PWM_REG1_ENABLE; ++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); + + return 0; +} @@ -235,27 +223,41 @@ Signed-off-by: Devi Priya + struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(chip); -+ unsigned long rate = clk_get_rate(ipq_chip->clk); + unsigned int pre_div, pwm_div, hi_dur; + u64 effective_div, hi_div; + u32 reg0, reg1; + -+ reg0 = ipq_pwm_reg_read(pwm, IPQ_PWM_REG0); + reg1 = ipq_pwm_reg_read(pwm, IPQ_PWM_REG1); ++ state->enabled = reg1 & IPQ_PWM_REG1_ENABLE; ++ ++ if (!state->enabled) ++ return 0; ++ ++ reg0 = ipq_pwm_reg_read(pwm, IPQ_PWM_REG0); + + state->polarity = PWM_POLARITY_NORMAL; -+ state->enabled = reg1 & IPQ_PWM_REG1_ENABLE; + + pwm_div = FIELD_GET(IPQ_PWM_REG0_PWM_DIV, reg0); + hi_dur = FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0); + pre_div = FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1); + -+ /* No overflow here, both pre_div and pwm_div <= 0xffff */ -+ effective_div = (u64)(pre_div + 1) * (pwm_div + 1); -+ state->period = DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC, rate); ++ effective_div = (u64)(pwm_div + 1) * (pre_div + 1); ++ ++ /* ++ * effective_div <= 0x100000000, so the multiplication doesn't overflow. ++ */ ++ state->period = DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC, ++ ipq_chip->clk_rate); + + hi_div = hi_dur * (pre_div + 1); -+ state->duty_cycle = DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC, rate); ++ state->duty_cycle = DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC, ++ ipq_chip->clk_rate); ++ ++ /* ++ * ensure a valid config is passed back to PWM core in case duty_cycle ++ * is > period (>100%) ++ */ ++ state->duty_cycle = min(state->duty_cycle, state->period); + + return 0; +} @@ -267,9 +269,10 @@ Signed-off-by: Devi Priya + +static int ipq_pwm_probe(struct platform_device *pdev) +{ -+ struct pwm_chip *chip; -+ struct ipq_pwm_chip *pwm; + struct device *dev = &pdev->dev; ++ struct ipq_pwm_chip *pwm; ++ struct pwm_chip *chip; ++ struct clk *clk; + int ret; + + chip = devm_pwmchip_alloc(dev, 4, sizeof(*pwm)); @@ -280,20 +283,28 @@ Signed-off-by: Devi Priya + pwm->mem = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pwm->mem)) + return dev_err_probe(dev, PTR_ERR(pwm->mem), -+ "regs map failed"); ++ "Failed to acquire resource\n"); ++ ++ clk = devm_clk_get_enabled(dev, NULL); ++ if (IS_ERR(clk)) ++ return dev_err_probe(dev, PTR_ERR(clk), ++ "Failed to get clock\n"); + -+ pwm->clk = devm_clk_get_enabled(dev, NULL); -+ if (IS_ERR(pwm->clk)) -+ return dev_err_probe(dev, PTR_ERR(pwm->clk), -+ "failed to get clock"); ++ ret = devm_clk_rate_exclusive_get(dev, clk); ++ if (ret) ++ return dev_err_probe(dev, ret, "Failed to lock clock rate\n"); ++ ++ pwm->clk_rate = clk_get_rate(clk); ++ if (!pwm->clk_rate) ++ return dev_err_probe(dev, -EINVAL, "Failed due to clock rate being zero\n"); + + chip->ops = &ipq_pwm_ops; + + ret = devm_pwmchip_add(dev, chip); + if (ret < 0) -+ dev_err_probe(dev, ret, "devm_pwmchip_add() failed\n"); ++ return dev_err_probe(dev, ret, "Failed to add pwm chip\n"); + -+ return ret; ++ return 0; +} + +static const struct of_device_id pwm_ipq_dt_match[] = { @@ -312,4 +323,4 @@ Signed-off-by: Devi Priya + +module_platform_driver(ipq_pwm_driver); + -+MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/qualcommax/patches-6.12/0078-v7.3-arm64-dts-qcom-ipq6018-add-pwm-node.patch b/target/linux/qualcommax/patches-6.12/0078-v7.3-arm64-dts-qcom-ipq6018-add-pwm-node.patch new file mode 100644 index 00000000000..4ee9086b890 --- /dev/null +++ b/target/linux/qualcommax/patches-6.12/0078-v7.3-arm64-dts-qcom-ipq6018-add-pwm-node.patch @@ -0,0 +1,44 @@ +From 6cc812b7435a64cd9d66af107c6dfefb2e77a7cb Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Mon, 6 Apr 2026 22:24:40 +0200 +Subject: arm64: dts: qcom: ipq6018: add pwm node + +Describe the PWM block on IPQ6018. + +Although PWM is in the TCSR area, make pwm its own node as simple-mfd +has been removed from the bindings and as such hardware components +should have its own node. + +Reviewed-by: Krzysztof Kozlowski +Co-developed-by: Baruch Siach +Signed-off-by: Baruch Siach +Signed-off-by: Devi Priya +Reviewed-by: Konrad Dybcio +Signed-off-by: George Moussalem +Link: https://lore.kernel.org/r/20260406-ipq-pwm-v21-3-6ed1e868e4c2@outlook.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +(limited to 'arch/arm64/boot/dts/qcom/ipq6018.dtsi') + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -416,6 +416,16 @@ + reg = <0x0 0x01937000 0x0 0x21000>; + }; + ++ pwm: pwm@1941010 { ++ compatible = "qcom,ipq6018-pwm"; ++ reg = <0x0 0x01941010 0x0 0x20>; ++ clocks = <&gcc GCC_ADSS_PWM_CLK>; ++ assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; ++ assigned-clock-rates = <100000000>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ + usb2: usb@70f8800 { + compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; + reg = <0x0 0x070f8800 0x0 0x400>; diff --git a/target/linux/qualcommax/patches-6.12/0079-v7.3-arm64-dts-qcom-ipq5018-add-pwm-node.patch b/target/linux/qualcommax/patches-6.12/0079-v7.3-arm64-dts-qcom-ipq5018-add-pwm-node.patch new file mode 100644 index 00000000000..4be6601939c --- /dev/null +++ b/target/linux/qualcommax/patches-6.12/0079-v7.3-arm64-dts-qcom-ipq5018-add-pwm-node.patch @@ -0,0 +1,41 @@ +From 4b00afd17a28f44dc63a8602143f84e5f3fa592c Mon Sep 17 00:00:00 2001 +From: George Moussalem +Date: Mon, 6 Apr 2026 22:24:41 +0200 +Subject: arm64: dts: qcom: ipq5018: add pwm node + +Describe the PWM block on IPQ5018. + +Although PWM is in the TCSR area, make pwm its own node as simple-mfd +has been removed from the bindings and as such hardware components +should have its own node. + +Reviewed-by: Dmitry Baryshkov +Reviewed-by: Konrad Dybcio +Signed-off-by: George Moussalem +Link: https://lore.kernel.org/r/20260406-ipq-pwm-v21-4-6ed1e868e4c2@outlook.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi') + +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -453,6 +453,16 @@ + reg = <0x01937000 0x21000>; + }; + ++ pwm: pwm@1941010 { ++ compatible = "qcom,ipq5018-pwm", "qcom,ipq6018-pwm"; ++ reg = <0x01941010 0x20>; ++ clocks = <&gcc GCC_ADSS_PWM_CLK>; ++ assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; ++ assigned-clock-rates = <100000000>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ + sdhc_1: mmc@7804000 { + compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x7804000 0x1000>; diff --git a/target/linux/qualcommax/patches-6.12/0138-arm64-dts-qcom-ipq6018-add-pwm-node.patch b/target/linux/qualcommax/patches-6.12/0138-arm64-dts-qcom-ipq6018-add-pwm-node.patch deleted file mode 100644 index 006818abe0d..00000000000 --- a/target/linux/qualcommax/patches-6.12/0138-arm64-dts-qcom-ipq6018-add-pwm-node.patch +++ /dev/null @@ -1,45 +0,0 @@ -From b4a32d218d424b81a58fbd419e1114b1c1f76168 Mon Sep 17 00:00:00 2001 -From: Devi Priya -Date: Thu, 5 Oct 2023 21:35:50 +0530 -Subject: [PATCH] arm64: dts: qcom: ipq6018: add pwm node - -Describe the PWM block on IPQ6018. - -The PWM is in the TCSR area. Make &tcsr "simple-mfd" compatible, and add -&pwm as child of &tcsr. - -Add also ipq6018 specific compatible string. - -Reviewed-by: Krzysztof Kozlowski -Co-developed-by: Baruch Siach -Signed-off-by: Baruch Siach -Signed-off-by: Devi Priya ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 15 ++++++++++++++- - 1 file changed, 14 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -417,8 +417,21 @@ - }; - - tcsr: syscon@1937000 { -- compatible = "qcom,tcsr-ipq6018", "syscon"; -+ compatible = "qcom,tcsr-ipq6018", "syscon", "simple-mfd"; - reg = <0x0 0x01937000 0x0 0x21000>; -+ ranges = <0x0 0x0 0x01937000 0x21000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ pwm: pwm@a010 { -+ compatible = "qcom,ipq6018-pwm"; -+ reg = <0xa010 0x20>; -+ clocks = <&gcc GCC_ADSS_PWM_CLK>; -+ assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; -+ assigned-clock-rates = <100000000>; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; - }; - - usb2: usb@70f8800 { diff --git a/target/linux/qualcommax/patches-6.12/0189-arm64-dts-qcom-ipq5018-add-nodes-to-bringup-q6.patch b/target/linux/qualcommax/patches-6.12/0189-arm64-dts-qcom-ipq5018-add-nodes-to-bringup-q6.patch index 9ea80bf08a9..7620bb53e1b 100644 --- a/target/linux/qualcommax/patches-6.12/0189-arm64-dts-qcom-ipq5018-add-nodes-to-bringup-q6.patch +++ b/target/linux/qualcommax/patches-6.12/0189-arm64-dts-qcom-ipq5018-add-nodes-to-bringup-q6.patch @@ -28,7 +28,7 @@ Signed-off-by: George Moussalem }; soc: soc@0 { -@@ -721,6 +726,41 @@ +@@ -731,6 +736,41 @@ }; }; @@ -70,7 +70,7 @@ Signed-off-by: George Moussalem pcie1: pcie@80000000 { compatible = "qcom,pcie-ipq5018"; reg = <0x80000000 0xf1d>, -@@ -995,4 +1035,28 @@ +@@ -1005,4 +1045,28 @@ , ; }; diff --git a/target/linux/qualcommax/patches-6.12/0304-dt-bindings-pwm-add-IPQ5018-compatible.patch b/target/linux/qualcommax/patches-6.12/0304-dt-bindings-pwm-add-IPQ5018-compatible.patch deleted file mode 100644 index 5705028931b..00000000000 --- a/target/linux/qualcommax/patches-6.12/0304-dt-bindings-pwm-add-IPQ5018-compatible.patch +++ /dev/null @@ -1,22 +0,0 @@ -From: George Moussalem -Subject: [PATCH] dt-bindings: mfd: qcom,tcsr: Add IPQ5018 compatible -Date: Sun, 06 Oct 2024 16:34:11 +0400 - -Add compatible for IPQ5018. - -Signed-off-by: George Moussalem ---- ---- a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml -+++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml -@@ -11,7 +11,10 @@ maintainers: - - properties: - compatible: -- const: qcom,ipq6018-pwm -+ items: -+ - enum: -+ - qcom,ipq5018-pwm -+ - const: qcom,ipq6018-pwm - - reg: - description: Offset of PWM register in the TCSR block. diff --git a/target/linux/qualcommax/patches-6.12/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch b/target/linux/qualcommax/patches-6.12/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch deleted file mode 100644 index 5272a574657..00000000000 --- a/target/linux/qualcommax/patches-6.12/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch +++ /dev/null @@ -1,27 +0,0 @@ -From: George Moussalem -Subject: [PATCH] arm64: dts: qcom: ipq5018: Add PWM node -Date: Sun, 06 Oct 2024 16:34:11 +0400 - -Add PWM node. - -Signed-off-by: George Moussalem ---- ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -458,6 +458,16 @@ - reg = <0x01937000 0x21000>; - }; - -+ pwm: pwm@1941010 { -+ compatible = "qcom,ipq5018-pwm", "qcom,ipq6018-pwm"; -+ reg = <0x01941010 0x20>; -+ clocks = <&gcc GCC_ADSS_PWM_CLK>; -+ assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; -+ assigned-clock-rates = <100000000>; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ - sdhc_1: mmc@7804000 { - compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x7804000 0x1000>; diff --git a/target/linux/qualcommax/patches-6.12/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch b/target/linux/qualcommax/patches-6.12/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch index 3ff649f2a4a..aac8cd53dc2 100644 --- a/target/linux/qualcommax/patches-6.12/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch +++ b/target/linux/qualcommax/patches-6.12/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch @@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -834,6 +834,102 @@ +@@ -831,6 +831,102 @@ }; }; diff --git a/target/linux/qualcommax/patches-6.12/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch b/target/linux/qualcommax/patches-6.12/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch index 02d8da6305d..9dc8cd4d086 100644 --- a/target/linux/qualcommax/patches-6.12/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch +++ b/target/linux/qualcommax/patches-6.12/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch @@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -1186,6 +1186,7 @@ +@@ -1183,6 +1183,7 @@ wcss_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; diff --git a/target/linux/qualcommax/patches-6.12/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch b/target/linux/qualcommax/patches-6.12/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch index 4ef8f799ab6..2a2fa5ffc91 100644 --- a/target/linux/qualcommax/patches-6.12/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch +++ b/target/linux/qualcommax/patches-6.12/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch @@ -13,7 +13,7 @@ Signed-off-by: Mantas Pucka --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -955,8 +955,8 @@ +@@ -952,8 +952,8 @@ "wcss_reset", "wcss_q6_reset";