From: James Greenhalgh <james.greenhalgh@arm.com>
Date: Mon, 23 Jun 2014 16:00:02 +0000 (+0000)
Subject: Re: [AArch64] Implement ADD in vector registers for 32-bit scalar values.
X-Git-Tag: releases/gcc-5.1.0~6723
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=0379033b6388ad245e8926766929012c27b6f20a;p=thirdparty%2Fgcc.git

Re: [AArch64] Implement ADD in vector registers for 32-bit scalar values.

gcc/

	* config/aarch64/aarch64.md (addsi3_aarch64): Set "simd" attr to
	"yes" where needed.

From-SVN: r211899
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7979ff98feac..32917ef5e4a5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2014-06-23  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/aarch64/aarch64.md (addsi3_aarch64): Set "simd" attr to
+	"yes" where needed.
+
 2014-06-23  Alan Modra  <amodra@gmail.com>
 
 	PR bootstrap/61583
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 5f5b4ff89b64..8705ee9d1892 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1167,7 +1167,8 @@
   add\\t%w0, %w1, %w2
   add\\t%0.2s, %1.2s, %2.2s
   sub\\t%w0, %w1, #%n2"
-  [(set_attr "type" "alu_imm,alu_reg,neon_add,alu_imm")]
+  [(set_attr "type" "alu_imm,alu_reg,neon_add,alu_imm")
+   (set_attr "simd" "*,*,yes,*")]
 )
 
 ;; zero_extend version of above