From: Greg Kroah-Hartman Date: Thu, 12 Oct 2023 18:05:10 +0000 (+0200) Subject: 5.4-stable patches X-Git-Tag: v6.1.58~26 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=0599e1162c30902237eb2cdeabc40d676a61615d;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch --- diff --git a/queue-5.4/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch b/queue-5.4/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch new file mode 100644 index 00000000000..3466b4d9ab3 --- /dev/null +++ b/queue-5.4/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch @@ -0,0 +1,53 @@ +From 197c53c8ecb34f2cd5922f4bdcffa8f701a134eb Mon Sep 17 00:00:00 2001 +From: Shengjiu Wang +Date: Tue, 19 Sep 2023 17:42:13 +0800 +Subject: ASoC: fsl_sai: Don't disable bitclock for i.MX8MP + +From: Shengjiu Wang + +commit 197c53c8ecb34f2cd5922f4bdcffa8f701a134eb upstream. + +On i.MX8MP, the BCE and TERE bit are binding with mclk +enablement, if BCE and TERE are cleared the MCLK also be +disabled on output pin, that cause the external codec (wm8960) +in wrong state. + +Codec (wm8960) is using the mclk to generate PLL clock, +if mclk is disabled before disabling PLL, the codec (wm8960) +won't generate bclk and frameclk when sysclk switch to +MCLK source in next test case. + +The test case: +$aplay -r44100 test1.wav (PLL source) +$aplay -r48000 test2.wav (MCLK source) +aplay: pcm_write:2127: write error: Input/output error + +Fixes: 269f399dc19f ("ASoC: fsl_sai: Disable bit clock with transmitter") +Signed-off-by: Shengjiu Wang +Link: https://lore.kernel.org/r/1695116533-23287-1-git-send-email-shengjiu.wang@nxp.com +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman +--- + sound/soc/fsl/fsl_sai.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +--- a/sound/soc/fsl/fsl_sai.c ++++ b/sound/soc/fsl/fsl_sai.c +@@ -545,10 +545,15 @@ static void fsl_sai_config_disable(struc + { + unsigned int ofs = sai->soc_data->reg_offset; + bool tx = dir == TX; +- u32 xcsr, count = 100; ++ u32 xcsr, count = 100, mask; ++ ++ if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) ++ mask = FSL_SAI_CSR_TERE; ++ else ++ mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE; + + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), +- FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE, 0); ++ mask, 0); + + /* TERE will remain set till the end of current frame */ + do { diff --git a/queue-5.4/series b/queue-5.4/series index 19ebec718dd..f0f981fd3de 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -6,3 +6,4 @@ hid-logitech-hidpp-fix-kernel-crash-on-receiver-usb-disconnect.patch quota-fix-slow-quotaoff.patch net-prevent-address-rewrite-in-kernel_bind.patch drm-etvnaviv-fix-bad-backport-leading-to-warning.patch +asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch