From: Sasha Levin Date: Fri, 23 May 2025 12:21:59 +0000 (-0400) Subject: Drop drm-amdgpu-add-dce_v6_0_soft_reset-to-dce6.patch X-Git-Tag: v6.12.31~82 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=05bd9024a911b4f572cb5989a8561a10347dfc08;p=thirdparty%2Fkernel%2Fstable-queue.git Drop drm-amdgpu-add-dce_v6_0_soft_reset-to-dce6.patch Signed-off-by: Sasha Levin --- diff --git a/queue-6.14/drm-amdgpu-add-dce_v6_0_soft_reset-to-dce6.patch b/queue-6.14/drm-amdgpu-add-dce_v6_0_soft_reset-to-dce6.patch deleted file mode 100644 index bccf7bbdef..0000000000 --- a/queue-6.14/drm-amdgpu-add-dce_v6_0_soft_reset-to-dce6.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 1c2c44642f12b5c84c61e60074e9611c759dd16a Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Fri, 28 Feb 2025 23:11:20 -0500 -Subject: drm/amdgpu: add dce_v6_0_soft_reset() to DCE6 - -From: Alexandre Demers - -[ Upstream commit ab23db6d08efdda5d13d01a66c593d0e57f8917f ] - -DCE6 was missing soft reset, but it was easily identifiable under radeon. -This should be it, pretty much as it is done under DCE8 and DCE10. - -Signed-off-by: Alexandre Demers -Signed-off-by: Alex Deucher -Signed-off-by: Sasha Levin ---- - drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 53 ++++++++++++++++++++++++++- - 1 file changed, 51 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c -index 915804a6a1d7d..ed5e06b677df1 100644 ---- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c -@@ -370,13 +370,41 @@ static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) - return mmDC_GPIO_HPD_A; - } - -+static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev) -+{ -+ u32 crtc_hung = 0; -+ u32 crtc_status[6]; -+ u32 i, j, tmp; -+ -+ for (i = 0; i < adev->mode_info.num_crtc; i++) { -+ if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { -+ crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); -+ crtc_hung |= (1 << i); -+ } -+ } -+ -+ for (j = 0; j < 10; j++) { -+ for (i = 0; i < adev->mode_info.num_crtc; i++) { -+ if (crtc_hung & (1 << i)) { -+ tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); -+ if (tmp != crtc_status[i]) -+ crtc_hung &= ~(1 << i); -+ } -+ } -+ if (crtc_hung == 0) -+ return false; -+ udelay(100); -+ } -+ -+ return true; -+} -+ - static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, - bool render) - { - if (!render) - WREG32(mmVGA_RENDER_CONTROL, - RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL); -- - } - - static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) -@@ -2872,7 +2900,28 @@ static bool dce_v6_0_is_idle(void *handle) - - static int dce_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) - { -- DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n"); -+ u32 srbm_soft_reset = 0, tmp; -+ struct amdgpu_device *adev = ip_block->adev; -+ -+ if (dce_v6_0_is_display_hung(adev)) -+ srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; -+ -+ if (srbm_soft_reset) { -+ tmp = RREG32(mmSRBM_SOFT_RESET); -+ tmp |= srbm_soft_reset; -+ dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); -+ WREG32(mmSRBM_SOFT_RESET, tmp); -+ tmp = RREG32(mmSRBM_SOFT_RESET); -+ -+ udelay(50); -+ -+ tmp &= ~srbm_soft_reset; -+ WREG32(mmSRBM_SOFT_RESET, tmp); -+ tmp = RREG32(mmSRBM_SOFT_RESET); -+ -+ /* Wait a little for things to settle down */ -+ udelay(50); -+ } - return 0; - } - --- -2.39.5 - diff --git a/queue-6.14/series b/queue-6.14/series index 956b662ffc..cd0f61a487 100644 --- a/queue-6.14/series +++ b/queue-6.14/series @@ -284,7 +284,6 @@ remoteproc-qcom_wcnss-handle-platforms-with-only-sin.patch drm-xe-disambiguate-gmdid-based-ip-names.patch drm-amdgpu-do-not-program-agp-bar-regs-under-sriov-i.patch drm-amdgpu-reinit-fw-shared-flags-on-vcn-v5.0.1.patch -drm-amdgpu-add-dce_v6_0_soft_reset-to-dce6.patch drm-amd-display-ensure-dmcub-idle-before-reset-on-dc.patch drm-amd-display-skip-checking-frl_mode-bit-for-pcon-.patch drm-amd-display-fix-dmub-reset-sequence-for-dcn401.patch