From: Himal Prasad Ghimiray Date: Wed, 25 Feb 2026 16:47:48 +0000 (+0530) Subject: drm/xe/guc: Skip access counter queue init for unsupported platforms X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=07eb8b54166b208ca23382d650b5262a26a4492b;p=thirdparty%2Fkernel%2Flinux.git drm/xe/guc: Skip access counter queue init for unsupported platforms Add a has_access_counter feature flag to the graphics IP descriptor and skip writing parameters for the access counter queue in guc_um_init_params(), leaving queue_params[2] zero-initialized to signal unavailability to the GuC. The queue_params[] array layout is fixed by firmware ABI, so we maintain the structure with queues 0 and 1 (page fault request/response) always configured, and queue 2 conditionally skipped based on the has_access_counter flag. Bspec: 59323 Cc: Stuart Summers Cc: Matt Roper Suggested-by: Daniele Ceraolo Spurio Signed-off-by: Himal Prasad Ghimiray Signed-off-by: Varun Gupta Reviewed-by: Matt Roper Link: https://patch.msgid.link/20260225164748.2302380-1-varun.gupta@intel.com Signed-off-by: Tejas Upadhyay --- diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index caa8f34a6744a..e9032014923da 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -153,6 +153,8 @@ struct xe_device { /** @info.force_execlist: Forced execlist submission */ u8 force_execlist:1; + /** @info.has_access_counter: Device supports access counter */ + u8 has_access_counter:1; /** @info.has_asid: Has address space ID */ u8 has_asid:1; /** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */ diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c index f4cbc030f4c81..81b5f01b1f65c 100644 --- a/drivers/gpu/drm/xe/xe_guc_ads.c +++ b/drivers/gpu/drm/xe/xe_guc_ads.c @@ -819,6 +819,7 @@ static void guc_um_init_params(struct xe_guc_ads *ads) { u32 um_queue_offset = guc_ads_um_queues_offset(ads); struct xe_guc *guc = ads_to_guc(ads); + struct xe_device *xe = ads_to_xe(ads); u64 base_dpa; u32 base_ggtt; bool with_dpa; @@ -830,6 +831,16 @@ static void guc_um_init_params(struct xe_guc_ads *ads) base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset; for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) { + /* + * Some platforms support USM but not access counters. + * Skip ACCESS_COUNTER queue initialization for such + * platforms, leaving queue_params[2] zero-initialized + * to signal unavailability to the GuC. + */ + if (i == GUC_UM_HW_QUEUE_ACCESS_COUNTER && + !xe->info.has_access_counter) + continue; + ads_blob_write(ads, um_init_params.queue_params[i].base_dpa, with_dpa ? (base_dpa + (i * GUC_UM_QUEUE_SIZE)) : 0); ads_blob_write(ads, um_init_params.queue_params[i].base_ggtt_address, diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index b48e84549888a..8bd8d5c9171e7 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -81,6 +81,7 @@ static const struct xe_graphics_desc graphics_xehpc = { XE_HP_FEATURES, + .has_access_counter = 1, .has_asid = 1, .has_atomic_enable_pte_bit = 1, .has_usm = 1, @@ -98,6 +99,7 @@ static const struct xe_graphics_desc graphics_xelpg = { }; #define XE2_GFX_FEATURES \ + .has_access_counter = 1, \ .has_asid = 1, \ .has_atomic_enable_pte_bit = 1, \ .has_range_tlb_inval = 1, \ @@ -123,6 +125,7 @@ static const struct xe_graphics_desc graphics_xe3p_lpg = { static const struct xe_graphics_desc graphics_xe3p_xpc = { XE2_GFX_FEATURES, + .has_access_counter = 0, .has_indirect_ring_state = 1, .hw_engine_mask = GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) | @@ -944,6 +947,7 @@ static int xe_info_init(struct xe_device *xe, media_desc = NULL; } + xe->info.has_access_counter = graphics_desc->has_access_counter; xe->info.has_asid = graphics_desc->has_asid; xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit; if (xe->info.platform != XE_PVC) diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h index 47e8a1552c2bf..8eee4fb1c57cf 100644 --- a/drivers/gpu/drm/xe/xe_pci_types.h +++ b/drivers/gpu/drm/xe/xe_pci_types.h @@ -70,6 +70,7 @@ struct xe_graphics_desc { u8 num_geometry_xecore_fuse_regs; u8 num_compute_xecore_fuse_regs; + u8 has_access_counter:1; u8 has_asid:1; u8 has_atomic_enable_pte_bit:1; u8 has_indirect_ring_state:1;