From: Steve Ellcey <sje@cup.hp.com>
Date: Thu, 10 Apr 2003 19:53:54 +0000 (+0000)
Subject: ia64-protos.h (addp4_optimize_ok): New.
X-Git-Tag: releases/gcc-3.4.0~7384
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=08744705c05e5eac1407a340ea03d88f00d2cfbe;p=thirdparty%2Fgcc.git

ia64-protos.h (addp4_optimize_ok): New.

	* ia64-protos.h (addp4_optimize_ok): New.
	* ia64.c (addp4_optimize_ok): New.
	* ia64.md (*ptr_extend_plus_1): Use addp4_optimize_ok.
	(*ptr_extend_plus_2): Ditto.

From-SVN: r65435
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index dd2d12a43dad..d56304733d13 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2003-04-10  Steve Ellcey  <sje@cup.hp.com>
+
+	* ia64-protos.h (addp4_optimize_ok): New.
+	* ia64.c (addp4_optimize_ok): New.
+	* ia64.md (*ptr_extend_plus_1): Use addp4_optimize_ok.
+	(*ptr_extend_plus_2): Ditto.
+
 2003-04-10  Steve Ellcey  <sje@cup.hp.com>
 
 	* expr.c (expand_assignment): Extend offset_rtx with convert_to_mode
diff --git a/gcc/config/ia64/ia64-protos.h b/gcc/config/ia64/ia64-protos.h
index 53630e6a157d..baffb0169c3c 100644
--- a/gcc/config/ia64/ia64-protos.h
+++ b/gcc/config/ia64/ia64-protos.h
@@ -76,6 +76,7 @@ extern int basereg_operand PARAMS((rtx, enum machine_mode));
 
 extern rtx ia64_expand_move PARAMS ((rtx, rtx));
 extern int ia64_move_ok PARAMS((rtx, rtx));
+extern int addp4_optimize_ok PARAMS((rtx, rtx));
 extern void ia64_emit_cond_move PARAMS((rtx, rtx, rtx));
 extern int ia64_depz_field_mask PARAMS((rtx, rtx));
 extern rtx ia64_split_timode PARAMS((rtx[], rtx, rtx));
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index bbcd90dcae0d..3f867b5d73d2 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -48,6 +48,7 @@ Boston, MA 02111-1307, USA.  */
 #include "target-def.h"
 #include "tm_p.h"
 #include "hashtab.h"
+#include "langhooks.h"
 
 /* This is used for communication between ASM_OUTPUT_LABEL and
    ASM_OUTPUT_LABELREF.  */
@@ -1075,6 +1076,21 @@ ia64_move_ok (dst, src)
     return GET_CODE (src) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (src);
 }
 
+/* Return 0 if we are doing C++ code.  This optimization fails with
+   C++ because of GNAT c++/6685.  */
+
+int
+addp4_optimize_ok (op1, op2)
+     rtx op1, op2;
+{
+
+  if (!strcmp (lang_hooks.name, "GNU C++"))
+    return 0;
+
+  return (basereg_operand (op1, GET_MODE(op1)) !=
+	  basereg_operand (op2, GET_MODE(op2)));
+}
+
 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
    Return the length of the field, or <= 0 on failure.  */
 
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 074d8fdd3b5f..8a503cea539b 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -5469,7 +5469,7 @@
          [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
                    (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
          UNSPEC_ADDP4))]
-  ""
+  "addp4_optimize_ok (operands[1], operands[2])"
   "addp4 %0 = %2, %1"
   [(set_attr "itanium_class" "ialu")])
 
@@ -5479,6 +5479,6 @@
          [(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
                    (match_operand:SI 2 "basereg_operand" "r"))]
          UNSPEC_ADDP4))]
-  ""
+  "addp4_optimize_ok (operands[1], operands[2])"
   "addp4 %0 = %1, %2"
   [(set_attr "itanium_class" "ialu")])