From: Michal Simek Date: Thu, 3 Aug 2017 11:49:24 +0000 (+0200) Subject: arm64: zynqmp: Add support for Xilinx zc1275 board X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=08f7914d1dd1d65497c61a22bf0ddd3e92c31873;p=thirdparty%2Fu-boot.git arm64: zynqmp: Add support for Xilinx zc1275 board This patch adds support for Xilinx zc1275 board. The defconfig for compilation is xilinx_zynqmp_zc1275_revA_defconfig Only QSPI(single) and uarts are wired on this board. This configuration is taken based on schematics and not tested on real board yet. Signed-off-by: Michal Simek --- diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7f750815247..27330e6e2cd 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -128,6 +128,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu106-revA.dtb \ zynqmp-zc1232-revA.dtb \ zynqmp-zc1254-revA.dtb \ + zynqmp-zc1275-revA.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb \ zynqmp-zc1751-xm017-dc3.dtb \ diff --git a/arch/arm/dts/zynqmp-zc1275-revA.dts b/arch/arm/dts/zynqmp-zc1275-revA.dts new file mode 100644 index 00000000000..8cff7ad742f --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1275-revA.dts @@ -0,0 +1,73 @@ +/* + * dts file for Xilinx ZynqMP ZC1275 + * + * (C) Copyright 2017, Xilinx, Inc. + * + * Michal Simek + * Siva Durga Prasad Paladugu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" + +/ { + model = "ZynqMP ZC1275 RevA"; + compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; + + aliases { + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/board/xilinx/zynqmp/zynqmp-zc1275-revA b/board/xilinx/zynqmp/zynqmp-zc1275-revA new file mode 120000 index 00000000000..7abf1dc4627 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zc1275-revA @@ -0,0 +1 @@ +zynqmp-zc1254-revA \ No newline at end of file diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig new file mode 100644 index 00000000000..26671227b3a --- /dev/null +++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig @@ -0,0 +1,54 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +# CONFIG_SPL_FAT_SUPPORT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_ZYNQMP_QSPI=y +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1275 revA" +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_OS_BOOT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_SPL_DM=y +CONFIG_CLK_ZYNQMP=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_MISC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_REGEX=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y