From: Yao Zihong Date: Thu, 30 Oct 2025 22:49:21 +0000 (-0500) Subject: riscv: memcpy_noalignment: Reorder to store via a3, then bump a3 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=09a94c86ca30e2ec5c07a23eae0d9855b631de04;p=thirdparty%2Fglibc.git riscv: memcpy_noalignment: Reorder to store via a3, then bump a3 Rewrite the copy micro-step from: REG_L a4, 0(a5) addi a3, a3, SZREG addi a5, a5, SZREG REG_S a4, -SZREG(a3) to: REG_L a4, 0(a5) addi a5, a5, SZREG REG_S a4, 0(a3) addi a3, a3, SZREG Semantics are unchanged: both read *(a5_old), write *(a3_old), and then increment a3/a5 by SZREG. memcpy assumes non-overlapping regions, so the reordering preserves correctness. No functional change. Signed-off-by: Yao Zihong Reviewed-by: Peter Bergner --- diff --git a/sysdeps/riscv/multiarch/memcpy_noalignment.S b/sysdeps/riscv/multiarch/memcpy_noalignment.S index 6917fc435b..43ce890657 100644 --- a/sysdeps/riscv/multiarch/memcpy_noalignment.S +++ b/sysdeps/riscv/multiarch/memcpy_noalignment.S @@ -109,9 +109,9 @@ L(word_copy): mv a5, a1 L(word_copy_loop): REG_L a4, 0(a5) - addi a3, a3, SZREG addi a5, a5, SZREG - REG_S a4, -SZREG(a3) + REG_S a4, 0(a3) + addi a3, a3, SZREG bne a3, a6, L(word_copy_loop) add a1, a1, a7 andi a2, a2, SZREG-1