From: Greg Kroah-Hartman Date: Sun, 7 May 2023 08:52:48 +0000 (+0200) Subject: 6.3-stable patches X-Git-Tag: v5.15.111~84 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=0a97a2f9f923952ad29cc3e062f2b76775a4051a;p=thirdparty%2Fkernel%2Fstable-queue.git 6.3-stable patches added patches: alsa-hda-realtek-add-quirk-for-asus-um3402yar-using-cs35l41.patch alsa-hda-realtek-add-quirk-for-thinkpad-p1-gen-6.patch alsa-hda-realtek-fix-mute-and-micmute-leds-for-an-hp-laptop.patch alsa-hda-realtek-support-hp-pavilion-aero-13-be0xxx-mute-led.patch alsa-usb-audio-add-quirk-for-pioneer-ddj-800.patch asoc-codecs-wcd938x-fix-accessing-regmap-on-unattached-devices.patch drbd-correctly-submit-flush-bio-on-barrier.patch mm-do-not-reclaim-private-data-from-pinned-page.patch nilfs2-do-not-write-dirty-data-after-degenerating-to-read-only.patch nilfs2-fix-infinite-loop-in-nilfs_mdt_get_block.patch parisc-ensure-page-alignment-in-flush-functions.patch parisc-fix-argument-pointer-in-real64_call_asm.patch --- diff --git a/queue-6.3/alsa-hda-realtek-add-quirk-for-asus-um3402yar-using-cs35l41.patch b/queue-6.3/alsa-hda-realtek-add-quirk-for-asus-um3402yar-using-cs35l41.patch new file mode 100644 index 00000000000..2de0716db1b --- /dev/null +++ b/queue-6.3/alsa-hda-realtek-add-quirk-for-asus-um3402yar-using-cs35l41.patch @@ -0,0 +1,31 @@ +From 7e2d06628aab6324e1ac885910a52f4c038d4043 Mon Sep 17 00:00:00 2001 +From: Mark Asselstine +Date: Mon, 1 May 2023 19:13:46 -0400 +Subject: ALSA: hda/realtek: Add quirk for ASUS UM3402YAR using CS35L41 + +From: Mark Asselstine + +commit 7e2d06628aab6324e1ac885910a52f4c038d4043 upstream. + +This Asus Zenbook laptop uses Realtek HDA codec combined with +2xCS35L41 Amplifiers using I2C with External Boost. + +Signed-off-by: Mark Asselstine +Cc: +Link: https://lore.kernel.org/r/20230501231346.54979-1-asselsm@gmail.com +Signed-off-by: Takashi Iwai +Signed-off-by: Greg Kroah-Hartman +--- + sound/pci/hda/patch_realtek.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/sound/pci/hda/patch_realtek.c ++++ b/sound/pci/hda/patch_realtek.c +@@ -9500,6 +9500,7 @@ static const struct snd_pci_quirk alc269 + SND_PCI_QUIRK(0x1043, 0x1427, "Asus Zenbook UX31E", ALC269VB_FIXUP_ASUS_ZENBOOK), + SND_PCI_QUIRK(0x1043, 0x1517, "Asus Zenbook UX31A", ALC269VB_FIXUP_ASUS_ZENBOOK_UX31A), + SND_PCI_QUIRK(0x1043, 0x1662, "ASUS GV301QH", ALC294_FIXUP_ASUS_DUAL_SPK), ++ SND_PCI_QUIRK(0x1043, 0x1683, "ASUS UM3402YAR", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x1043, 0x16b2, "ASUS GU603", ALC289_FIXUP_ASUS_GA401), + SND_PCI_QUIRK(0x1043, 0x16e3, "ASUS UX50", ALC269_FIXUP_STEREO_DMIC), + SND_PCI_QUIRK(0x1043, 0x1740, "ASUS UX430UA", ALC295_FIXUP_ASUS_DACS), diff --git a/queue-6.3/alsa-hda-realtek-add-quirk-for-thinkpad-p1-gen-6.patch b/queue-6.3/alsa-hda-realtek-add-quirk-for-thinkpad-p1-gen-6.patch new file mode 100644 index 00000000000..a05667a4be4 --- /dev/null +++ b/queue-6.3/alsa-hda-realtek-add-quirk-for-thinkpad-p1-gen-6.patch @@ -0,0 +1,32 @@ +From 067eb084592819ad59d07afcb5de3e61cee2757c Mon Sep 17 00:00:00 2001 +From: Vitaly Rodionov +Date: Thu, 27 Apr 2023 12:04:52 +0100 +Subject: ALSA: hda/realtek: Add quirk for ThinkPad P1 Gen 6 + +From: Vitaly Rodionov + +commit 067eb084592819ad59d07afcb5de3e61cee2757c upstream. + +Lenovo ThinkPad P1 Gen 6 laptop has 2 CS35L41 amplifies +on I2C bus connected to Realtek codec. + +Signed-off-by: Vitaly Rodionov +Cc: +Link: https://lore.kernel.org/r/20230427110452.13787-1-vitalyr@opensource.cirrus.com +Signed-off-by: Takashi Iwai +Signed-off-by: Greg Kroah-Hartman +--- + sound/pci/hda/patch_realtek.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/sound/pci/hda/patch_realtek.c ++++ b/sound/pci/hda/patch_realtek.c +@@ -9689,6 +9689,8 @@ static const struct snd_pci_quirk alc269 + SND_PCI_QUIRK(0x17aa, 0x22f1, "Thinkpad", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x17aa, 0x22f2, "Thinkpad", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x17aa, 0x22f3, "Thinkpad", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x17aa, 0x2316, "Thinkpad P1 Gen 6", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x17aa, 0x2317, "Thinkpad P1 Gen 6", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x17aa, 0x2318, "Thinkpad Z13 Gen2", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x17aa, 0x2319, "Thinkpad Z16 Gen2", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x17aa, 0x231a, "Thinkpad Z16 Gen2", ALC287_FIXUP_CS35L41_I2C_2), diff --git a/queue-6.3/alsa-hda-realtek-fix-mute-and-micmute-leds-for-an-hp-laptop.patch b/queue-6.3/alsa-hda-realtek-fix-mute-and-micmute-leds-for-an-hp-laptop.patch new file mode 100644 index 00000000000..af47e819602 --- /dev/null +++ b/queue-6.3/alsa-hda-realtek-fix-mute-and-micmute-leds-for-an-hp-laptop.patch @@ -0,0 +1,31 @@ +From 56fc217f0db4fc78e02a1b8450df06389474a5e5 Mon Sep 17 00:00:00 2001 +From: Kai-Heng Feng +Date: Fri, 5 May 2023 14:59:23 +0200 +Subject: ALSA: hda/realtek: Fix mute and micmute LEDs for an HP laptop + +From: Kai-Heng Feng + +commit 56fc217f0db4fc78e02a1b8450df06389474a5e5 upstream. + +There's another laptop that needs the fixup to enable mute and micmute +LEDs. So do it accordingly. + +Signed-off-by: Kai-Heng Feng +Cc: +Link: https://lore.kernel.org/r/20230505125925.543601-1-kai.heng.feng@canonical.com +Signed-off-by: Takashi Iwai +Signed-off-by: Greg Kroah-Hartman +--- + sound/pci/hda/patch_realtek.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/sound/pci/hda/patch_realtek.c ++++ b/sound/pci/hda/patch_realtek.c +@@ -9479,6 +9479,7 @@ static const struct snd_pci_quirk alc269 + SND_PCI_QUIRK(0x103c, 0x8b8d, "HP", ALC236_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8b8f, "HP", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8b92, "HP", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8b96, "HP", ALC236_FIXUP_HP_MUTE_LED_MICMUTE_VREF), + SND_PCI_QUIRK(0x103c, 0x8bf0, "HP", ALC236_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x1043, 0x103e, "ASUS X540SA", ALC256_FIXUP_ASUS_MIC), + SND_PCI_QUIRK(0x1043, 0x103f, "ASUS TX300", ALC282_FIXUP_ASUS_TX300), diff --git a/queue-6.3/alsa-hda-realtek-support-hp-pavilion-aero-13-be0xxx-mute-led.patch b/queue-6.3/alsa-hda-realtek-support-hp-pavilion-aero-13-be0xxx-mute-led.patch new file mode 100644 index 00000000000..f5aefd6033a --- /dev/null +++ b/queue-6.3/alsa-hda-realtek-support-hp-pavilion-aero-13-be0xxx-mute-led.patch @@ -0,0 +1,38 @@ +From e7477cb97607b373d175a759c8c0270a640ab3f2 Mon Sep 17 00:00:00 2001 +From: Caleb Harper +Date: Wed, 3 May 2023 12:50:26 -0500 +Subject: ALSA: hda/realtek: support HP Pavilion Aero 13-be0xxx Mute LED + +From: Caleb Harper + +commit e7477cb97607b373d175a759c8c0270a640ab3f2 upstream. + +This patch adds support for the mute LED on the HP Pavilion Aero Laptop +13-be0xxx. The current behavior is that the LED does not turn on at any +time and does not indicate to the user whether the sound is muted. + +The solution is to add a PCI quirk to properly recognize and support the +LED on this device. + +This change has been tested on the device in question using modified +versions of kernels 6.0.7-6.2.12 on Arch Linux. + +Signed-off-by: Caleb Harper +Cc: +Link: https://lore.kernel.org/r/20230503175026.6796-1-calebharp2005@gmail.com +Signed-off-by: Takashi Iwai +Signed-off-by: Greg Kroah-Hartman +--- + sound/pci/hda/patch_realtek.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/sound/pci/hda/patch_realtek.c ++++ b/sound/pci/hda/patch_realtek.c +@@ -9428,6 +9428,7 @@ static const struct snd_pci_quirk alc269 + SND_PCI_QUIRK(0x103c, 0x8898, "HP EliteBook 845 G8 Notebook PC", ALC285_FIXUP_HP_LIMIT_INT_MIC_BOOST), + SND_PCI_QUIRK(0x103c, 0x88d0, "HP Pavilion 15-eh1xxx (mainboard 88D0)", ALC287_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8902, "HP OMEN 16", ALC285_FIXUP_HP_MUTE_LED), ++ SND_PCI_QUIRK(0x103c, 0x8919, "HP Pavilion Aero Laptop 13-be0xxx", ALC287_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x896d, "HP ZBook Firefly 16 G9", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x896e, "HP EliteBook x360 830 G9", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8971, "HP EliteBook 830 G9", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), diff --git a/queue-6.3/alsa-usb-audio-add-quirk-for-pioneer-ddj-800.patch b/queue-6.3/alsa-usb-audio-add-quirk-for-pioneer-ddj-800.patch new file mode 100644 index 00000000000..29120d3556a --- /dev/null +++ b/queue-6.3/alsa-usb-audio-add-quirk-for-pioneer-ddj-800.patch @@ -0,0 +1,92 @@ +From 7501f472977df233d039d86c6981e0641708e1ca Mon Sep 17 00:00:00 2001 +From: Geraldo Nascimento +Date: Wed, 3 May 2023 18:02:06 -0300 +Subject: ALSA: usb-audio: Add quirk for Pioneer DDJ-800 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Geraldo Nascimento + +commit 7501f472977df233d039d86c6981e0641708e1ca upstream. + +One more Pioneer quirk, this time for DDJ-800, which is quite similar like +other DJ DDJ models but with slightly different EPs or channels. + +Signed-off-by: Geraldo Nascimento +Tested-by: Grégory Desor +Cc: +Link: https://lore.kernel.org/r/ZFLLzgEcsSF5aIHG@geday +Signed-off-by: Takashi Iwai +Signed-off-by: Greg Kroah-Hartman +--- + sound/usb/quirks-table.h | 58 +++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 58 insertions(+) + +--- a/sound/usb/quirks-table.h ++++ b/sound/usb/quirks-table.h +@@ -3884,6 +3884,64 @@ YAMAHA_DEVICE(0x7010, "UB99"), + } + }, + ++{ ++ /* ++ * PIONEER DJ DDJ-800 ++ * PCM is 6 channels out, 6 channels in @ 44.1 fixed ++ * The Feedback for the output is the input ++ */ ++ USB_DEVICE_VENDOR_SPEC(0x2b73, 0x0029), ++ .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) { ++ .ifnum = QUIRK_ANY_INTERFACE, ++ .type = QUIRK_COMPOSITE, ++ .data = (const struct snd_usb_audio_quirk[]) { ++ { ++ .ifnum = 0, ++ .type = QUIRK_AUDIO_FIXED_ENDPOINT, ++ .data = &(const struct audioformat) { ++ .formats = SNDRV_PCM_FMTBIT_S24_3LE, ++ .channels = 6, ++ .iface = 0, ++ .altsetting = 1, ++ .altset_idx = 1, ++ .endpoint = 0x01, ++ .ep_attr = USB_ENDPOINT_XFER_ISOC| ++ USB_ENDPOINT_SYNC_ASYNC, ++ .rates = SNDRV_PCM_RATE_44100, ++ .rate_min = 44100, ++ .rate_max = 44100, ++ .nr_rates = 1, ++ .rate_table = (unsigned int[]) { 44100 } ++ } ++ }, ++ { ++ .ifnum = 0, ++ .type = QUIRK_AUDIO_FIXED_ENDPOINT, ++ .data = &(const struct audioformat) { ++ .formats = SNDRV_PCM_FMTBIT_S24_3LE, ++ .channels = 6, ++ .iface = 0, ++ .altsetting = 1, ++ .altset_idx = 1, ++ .endpoint = 0x82, ++ .ep_idx = 1, ++ .ep_attr = USB_ENDPOINT_XFER_ISOC| ++ USB_ENDPOINT_SYNC_ASYNC| ++ USB_ENDPOINT_USAGE_IMPLICIT_FB, ++ .rates = SNDRV_PCM_RATE_44100, ++ .rate_min = 44100, ++ .rate_max = 44100, ++ .nr_rates = 1, ++ .rate_table = (unsigned int[]) { 44100 } ++ } ++ }, ++ { ++ .ifnum = -1 ++ } ++ } ++ } ++}, ++ + /* + * MacroSilicon MS2100/MS2106 based AV capture cards + * diff --git a/queue-6.3/asoc-codecs-wcd938x-fix-accessing-regmap-on-unattached-devices.patch b/queue-6.3/asoc-codecs-wcd938x-fix-accessing-regmap-on-unattached-devices.patch new file mode 100644 index 00000000000..710aa0a4613 --- /dev/null +++ b/queue-6.3/asoc-codecs-wcd938x-fix-accessing-regmap-on-unattached-devices.patch @@ -0,0 +1,2159 @@ +From 84822215acd15bd86a7759a835271e63bba83a7b Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Wed, 3 May 2023 16:41:02 +0200 +Subject: ASoC: codecs: wcd938x: fix accessing regmap on unattached devices + +From: Krzysztof Kozlowski + +commit 84822215acd15bd86a7759a835271e63bba83a7b upstream. + +The WCD938x comes with three devices on two Linux drivers: +1. RX Soundwire device (wcd938x-sdw.c driver), +2. TX Soundwire device, which is used to access devices via regmap (also + wcd938x-sdw.c driver), +3. platform device (wcd938x.c driver) - glue and component master, + actually having most of the code using TX Soundwire device regmap. + +When RX and TX Soundwire devices probe, the component master (platform +device) bind tries to write micbias configuration via TX Soundwire +regmap. This might happen before TX Soundwire enumerates, so the regmap +access fails. On Qualcomm SM8550 board with WCD9385: + + qcom-soundwire 6d30000.soundwire-controller: Qualcomm Soundwire controller v2.0.0 Registered + wcd938x_codec audio-codec: bound sdw:0:0217:010d:00:4 (ops wcd938x_sdw_component_ops) + wcd938x_codec audio-codec: bound sdw:0:0217:010d:00:3 (ops wcd938x_sdw_component_ops) + qcom-soundwire 6ad0000.soundwire-controller: swrm_wait_for_wr_fifo_avail err write overflow + +Fix the issue by: +1. Moving the regmap creation from platform device to TX Soundwire + device. The regmap settings are moved as-is with one difference: + making the wcd938x_regmap_config const. +2. Using regmap in cache only mode till the actual TX Soundwire device + enumerates and then sync the regmap cache. + +Cc: # v3.14+ +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Pierre-Louis Bossart +Message-Id: <20230503144102.242240-1-krzysztof.kozlowski@linaro.org> +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman +--- + sound/soc/codecs/wcd938x-sdw.c | 1037 ++++++++++++++++++++++++++++++++++++++++- + sound/soc/codecs/wcd938x.c | 1003 --------------------------------------- + sound/soc/codecs/wcd938x.h | 1 + 3 files changed, 1030 insertions(+), 1011 deletions(-) + +--- a/sound/soc/codecs/wcd938x-sdw.c ++++ b/sound/soc/codecs/wcd938x-sdw.c +@@ -161,6 +161,14 @@ EXPORT_SYMBOL_GPL(wcd938x_sdw_set_sdw_st + static int wcd9380_update_status(struct sdw_slave *slave, + enum sdw_slave_status status) + { ++ struct wcd938x_sdw_priv *wcd = dev_get_drvdata(&slave->dev); ++ ++ if (wcd->regmap && (status == SDW_SLAVE_ATTACHED)) { ++ /* Write out any cached changes that happened between probe and attach */ ++ regcache_cache_only(wcd->regmap, false); ++ return regcache_sync(wcd->regmap); ++ } ++ + return 0; + } + +@@ -177,20 +185,1014 @@ static int wcd9380_interrupt_callback(st + { + struct wcd938x_sdw_priv *wcd = dev_get_drvdata(&slave->dev); + struct irq_domain *slave_irq = wcd->slave_irq; +- struct regmap *regmap = dev_get_regmap(&slave->dev, NULL); + u32 sts1, sts2, sts3; + + do { + handle_nested_irq(irq_find_mapping(slave_irq, 0)); +- regmap_read(regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1); +- regmap_read(regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2); +- regmap_read(regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3); ++ regmap_read(wcd->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1); ++ regmap_read(wcd->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2); ++ regmap_read(wcd->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3); + + } while (sts1 || sts2 || sts3); + + return IRQ_HANDLED; + } + ++static const struct reg_default wcd938x_defaults[] = { ++ {WCD938X_ANA_PAGE_REGISTER, 0x00}, ++ {WCD938X_ANA_BIAS, 0x00}, ++ {WCD938X_ANA_RX_SUPPLIES, 0x00}, ++ {WCD938X_ANA_HPH, 0x0C}, ++ {WCD938X_ANA_EAR, 0x00}, ++ {WCD938X_ANA_EAR_COMPANDER_CTL, 0x02}, ++ {WCD938X_ANA_TX_CH1, 0x20}, ++ {WCD938X_ANA_TX_CH2, 0x00}, ++ {WCD938X_ANA_TX_CH3, 0x20}, ++ {WCD938X_ANA_TX_CH4, 0x00}, ++ {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00}, ++ {WCD938X_ANA_MICB3_DSP_EN_LOGIC, 0x00}, ++ {WCD938X_ANA_MBHC_MECH, 0x39}, ++ {WCD938X_ANA_MBHC_ELECT, 0x08}, ++ {WCD938X_ANA_MBHC_ZDET, 0x00}, ++ {WCD938X_ANA_MBHC_RESULT_1, 0x00}, ++ {WCD938X_ANA_MBHC_RESULT_2, 0x00}, ++ {WCD938X_ANA_MBHC_RESULT_3, 0x00}, ++ {WCD938X_ANA_MBHC_BTN0, 0x00}, ++ {WCD938X_ANA_MBHC_BTN1, 0x10}, ++ {WCD938X_ANA_MBHC_BTN2, 0x20}, ++ {WCD938X_ANA_MBHC_BTN3, 0x30}, ++ {WCD938X_ANA_MBHC_BTN4, 0x40}, ++ {WCD938X_ANA_MBHC_BTN5, 0x50}, ++ {WCD938X_ANA_MBHC_BTN6, 0x60}, ++ {WCD938X_ANA_MBHC_BTN7, 0x70}, ++ {WCD938X_ANA_MICB1, 0x10}, ++ {WCD938X_ANA_MICB2, 0x10}, ++ {WCD938X_ANA_MICB2_RAMP, 0x00}, ++ {WCD938X_ANA_MICB3, 0x10}, ++ {WCD938X_ANA_MICB4, 0x10}, ++ {WCD938X_BIAS_CTL, 0x2A}, ++ {WCD938X_BIAS_VBG_FINE_ADJ, 0x55}, ++ {WCD938X_LDOL_VDDCX_ADJUST, 0x01}, ++ {WCD938X_LDOL_DISABLE_LDOL, 0x00}, ++ {WCD938X_MBHC_CTL_CLK, 0x00}, ++ {WCD938X_MBHC_CTL_ANA, 0x00}, ++ {WCD938X_MBHC_CTL_SPARE_1, 0x00}, ++ {WCD938X_MBHC_CTL_SPARE_2, 0x00}, ++ {WCD938X_MBHC_CTL_BCS, 0x00}, ++ {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS, 0x00}, ++ {WCD938X_MBHC_TEST_CTL, 0x00}, ++ {WCD938X_LDOH_MODE, 0x2B}, ++ {WCD938X_LDOH_BIAS, 0x68}, ++ {WCD938X_LDOH_STB_LOADS, 0x00}, ++ {WCD938X_LDOH_SLOWRAMP, 0x50}, ++ {WCD938X_MICB1_TEST_CTL_1, 0x1A}, ++ {WCD938X_MICB1_TEST_CTL_2, 0x00}, ++ {WCD938X_MICB1_TEST_CTL_3, 0xA4}, ++ {WCD938X_MICB2_TEST_CTL_1, 0x1A}, ++ {WCD938X_MICB2_TEST_CTL_2, 0x00}, ++ {WCD938X_MICB2_TEST_CTL_3, 0x24}, ++ {WCD938X_MICB3_TEST_CTL_1, 0x1A}, ++ {WCD938X_MICB3_TEST_CTL_2, 0x00}, ++ {WCD938X_MICB3_TEST_CTL_3, 0xA4}, ++ {WCD938X_MICB4_TEST_CTL_1, 0x1A}, ++ {WCD938X_MICB4_TEST_CTL_2, 0x00}, ++ {WCD938X_MICB4_TEST_CTL_3, 0xA4}, ++ {WCD938X_TX_COM_ADC_VCM, 0x39}, ++ {WCD938X_TX_COM_BIAS_ATEST, 0xE0}, ++ {WCD938X_TX_COM_SPARE1, 0x00}, ++ {WCD938X_TX_COM_SPARE2, 0x00}, ++ {WCD938X_TX_COM_TXFE_DIV_CTL, 0x22}, ++ {WCD938X_TX_COM_TXFE_DIV_START, 0x00}, ++ {WCD938X_TX_COM_SPARE3, 0x00}, ++ {WCD938X_TX_COM_SPARE4, 0x00}, ++ {WCD938X_TX_1_2_TEST_EN, 0xCC}, ++ {WCD938X_TX_1_2_ADC_IB, 0xE9}, ++ {WCD938X_TX_1_2_ATEST_REFCTL, 0x0A}, ++ {WCD938X_TX_1_2_TEST_CTL, 0x38}, ++ {WCD938X_TX_1_2_TEST_BLK_EN1, 0xFF}, ++ {WCD938X_TX_1_2_TXFE1_CLKDIV, 0x00}, ++ {WCD938X_TX_1_2_SAR2_ERR, 0x00}, ++ {WCD938X_TX_1_2_SAR1_ERR, 0x00}, ++ {WCD938X_TX_3_4_TEST_EN, 0xCC}, ++ {WCD938X_TX_3_4_ADC_IB, 0xE9}, ++ {WCD938X_TX_3_4_ATEST_REFCTL, 0x0A}, ++ {WCD938X_TX_3_4_TEST_CTL, 0x38}, ++ {WCD938X_TX_3_4_TEST_BLK_EN3, 0xFF}, ++ {WCD938X_TX_3_4_TXFE3_CLKDIV, 0x00}, ++ {WCD938X_TX_3_4_SAR4_ERR, 0x00}, ++ {WCD938X_TX_3_4_SAR3_ERR, 0x00}, ++ {WCD938X_TX_3_4_TEST_BLK_EN2, 0xFB}, ++ {WCD938X_TX_3_4_TXFE2_CLKDIV, 0x00}, ++ {WCD938X_TX_3_4_SPARE1, 0x00}, ++ {WCD938X_TX_3_4_TEST_BLK_EN4, 0xFB}, ++ {WCD938X_TX_3_4_TXFE4_CLKDIV, 0x00}, ++ {WCD938X_TX_3_4_SPARE2, 0x00}, ++ {WCD938X_CLASSH_MODE_1, 0x40}, ++ {WCD938X_CLASSH_MODE_2, 0x3A}, ++ {WCD938X_CLASSH_MODE_3, 0x00}, ++ {WCD938X_CLASSH_CTRL_VCL_1, 0x70}, ++ {WCD938X_CLASSH_CTRL_VCL_2, 0x82}, ++ {WCD938X_CLASSH_CTRL_CCL_1, 0x31}, ++ {WCD938X_CLASSH_CTRL_CCL_2, 0x80}, ++ {WCD938X_CLASSH_CTRL_CCL_3, 0x80}, ++ {WCD938X_CLASSH_CTRL_CCL_4, 0x51}, ++ {WCD938X_CLASSH_CTRL_CCL_5, 0x00}, ++ {WCD938X_CLASSH_BUCK_TMUX_A_D, 0x00}, ++ {WCD938X_CLASSH_BUCK_SW_DRV_CNTL, 0x77}, ++ {WCD938X_CLASSH_SPARE, 0x00}, ++ {WCD938X_FLYBACK_EN, 0x4E}, ++ {WCD938X_FLYBACK_VNEG_CTRL_1, 0x0B}, ++ {WCD938X_FLYBACK_VNEG_CTRL_2, 0x45}, ++ {WCD938X_FLYBACK_VNEG_CTRL_3, 0x74}, ++ {WCD938X_FLYBACK_VNEG_CTRL_4, 0x7F}, ++ {WCD938X_FLYBACK_VNEG_CTRL_5, 0x83}, ++ {WCD938X_FLYBACK_VNEG_CTRL_6, 0x98}, ++ {WCD938X_FLYBACK_VNEG_CTRL_7, 0xA9}, ++ {WCD938X_FLYBACK_VNEG_CTRL_8, 0x68}, ++ {WCD938X_FLYBACK_VNEG_CTRL_9, 0x64}, ++ {WCD938X_FLYBACK_VNEGDAC_CTRL_1, 0xED}, ++ {WCD938X_FLYBACK_VNEGDAC_CTRL_2, 0xF0}, ++ {WCD938X_FLYBACK_VNEGDAC_CTRL_3, 0xA6}, ++ {WCD938X_FLYBACK_CTRL_1, 0x65}, ++ {WCD938X_FLYBACK_TEST_CTL, 0x00}, ++ {WCD938X_RX_AUX_SW_CTL, 0x00}, ++ {WCD938X_RX_PA_AUX_IN_CONN, 0x01}, ++ {WCD938X_RX_TIMER_DIV, 0x32}, ++ {WCD938X_RX_OCP_CTL, 0x1F}, ++ {WCD938X_RX_OCP_COUNT, 0x77}, ++ {WCD938X_RX_BIAS_EAR_DAC, 0xA0}, ++ {WCD938X_RX_BIAS_EAR_AMP, 0xAA}, ++ {WCD938X_RX_BIAS_HPH_LDO, 0xA9}, ++ {WCD938X_RX_BIAS_HPH_PA, 0xAA}, ++ {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A}, ++ {WCD938X_RX_BIAS_HPH_RDAC_LDO, 0x88}, ++ {WCD938X_RX_BIAS_HPH_CNP1, 0x82}, ++ {WCD938X_RX_BIAS_HPH_LOWPOWER, 0x82}, ++ {WCD938X_RX_BIAS_AUX_DAC, 0xA0}, ++ {WCD938X_RX_BIAS_AUX_AMP, 0xAA}, ++ {WCD938X_RX_BIAS_VNEGDAC_BLEEDER, 0x50}, ++ {WCD938X_RX_BIAS_MISC, 0x00}, ++ {WCD938X_RX_BIAS_BUCK_RST, 0x08}, ++ {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44}, ++ {WCD938X_RX_BIAS_FLYB_ERRAMP, 0x40}, ++ {WCD938X_RX_BIAS_FLYB_BUFF, 0xAA}, ++ {WCD938X_RX_BIAS_FLYB_MID_RST, 0x14}, ++ {WCD938X_HPH_L_STATUS, 0x04}, ++ {WCD938X_HPH_R_STATUS, 0x04}, ++ {WCD938X_HPH_CNP_EN, 0x80}, ++ {WCD938X_HPH_CNP_WG_CTL, 0x9A}, ++ {WCD938X_HPH_CNP_WG_TIME, 0x14}, ++ {WCD938X_HPH_OCP_CTL, 0x28}, ++ {WCD938X_HPH_AUTO_CHOP, 0x16}, ++ {WCD938X_HPH_CHOP_CTL, 0x83}, ++ {WCD938X_HPH_PA_CTL1, 0x46}, ++ {WCD938X_HPH_PA_CTL2, 0x50}, ++ {WCD938X_HPH_L_EN, 0x80}, ++ {WCD938X_HPH_L_TEST, 0xE0}, ++ {WCD938X_HPH_L_ATEST, 0x50}, ++ {WCD938X_HPH_R_EN, 0x80}, ++ {WCD938X_HPH_R_TEST, 0xE0}, ++ {WCD938X_HPH_R_ATEST, 0x54}, ++ {WCD938X_HPH_RDAC_CLK_CTL1, 0x99}, ++ {WCD938X_HPH_RDAC_CLK_CTL2, 0x9B}, ++ {WCD938X_HPH_RDAC_LDO_CTL, 0x33}, ++ {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00}, ++ {WCD938X_HPH_REFBUFF_UHQA_CTL, 0x68}, ++ {WCD938X_HPH_REFBUFF_LP_CTL, 0x0E}, ++ {WCD938X_HPH_L_DAC_CTL, 0x20}, ++ {WCD938X_HPH_R_DAC_CTL, 0x20}, ++ {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55}, ++ {WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0x19}, ++ {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1, 0xA0}, ++ {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00}, ++ {WCD938X_EAR_EAR_EN_REG, 0x22}, ++ {WCD938X_EAR_EAR_PA_CON, 0x44}, ++ {WCD938X_EAR_EAR_SP_CON, 0xDB}, ++ {WCD938X_EAR_EAR_DAC_CON, 0x80}, ++ {WCD938X_EAR_EAR_CNP_FSM_CON, 0xB2}, ++ {WCD938X_EAR_TEST_CTL, 0x00}, ++ {WCD938X_EAR_STATUS_REG_1, 0x00}, ++ {WCD938X_EAR_STATUS_REG_2, 0x08}, ++ {WCD938X_ANA_NEW_PAGE_REGISTER, 0x00}, ++ {WCD938X_HPH_NEW_ANA_HPH2, 0x00}, ++ {WCD938X_HPH_NEW_ANA_HPH3, 0x00}, ++ {WCD938X_SLEEP_CTL, 0x16}, ++ {WCD938X_SLEEP_WATCHDOG_CTL, 0x00}, ++ {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00}, ++ {WCD938X_MBHC_NEW_CTL_1, 0x02}, ++ {WCD938X_MBHC_NEW_CTL_2, 0x05}, ++ {WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0xE9}, ++ {WCD938X_MBHC_NEW_ZDET_ANA_CTL, 0x0F}, ++ {WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 0x00}, ++ {WCD938X_MBHC_NEW_FSM_STATUS, 0x00}, ++ {WCD938X_MBHC_NEW_ADC_RESULT, 0x00}, ++ {WCD938X_TX_NEW_AMIC_MUX_CFG, 0x00}, ++ {WCD938X_AUX_AUXPA, 0x00}, ++ {WCD938X_LDORXTX_MODE, 0x0C}, ++ {WCD938X_LDORXTX_CONFIG, 0x10}, ++ {WCD938X_DIE_CRACK_DIE_CRK_DET_EN, 0x00}, ++ {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT, 0x00}, ++ {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40}, ++ {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81}, ++ {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10}, ++ {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00}, ++ {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81}, ++ {WCD938X_HPH_NEW_INT_PA_MISC1, 0x22}, ++ {WCD938X_HPH_NEW_INT_PA_MISC2, 0x00}, ++ {WCD938X_HPH_NEW_INT_PA_RDAC_MISC, 0x00}, ++ {WCD938X_HPH_NEW_INT_HPH_TIMER1, 0xFE}, ++ {WCD938X_HPH_NEW_INT_HPH_TIMER2, 0x02}, ++ {WCD938X_HPH_NEW_INT_HPH_TIMER3, 0x4E}, ++ {WCD938X_HPH_NEW_INT_HPH_TIMER4, 0x54}, ++ {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00}, ++ {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00}, ++ {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 0x90}, ++ {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 0x90}, ++ {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62}, ++ {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01}, ++ {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11}, ++ {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57}, ++ {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01}, ++ {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00}, ++ {WCD938X_MBHC_NEW_INT_SPARE_2, 0x00}, ++ {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON, 0xA8}, ++ {WCD938X_EAR_INT_NEW_CNP_VCM_CON1, 0x42}, ++ {WCD938X_EAR_INT_NEW_CNP_VCM_CON2, 0x22}, ++ {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00}, ++ {WCD938X_AUX_INT_EN_REG, 0x00}, ++ {WCD938X_AUX_INT_PA_CTRL, 0x06}, ++ {WCD938X_AUX_INT_SP_CTRL, 0xD2}, ++ {WCD938X_AUX_INT_DAC_CTRL, 0x80}, ++ {WCD938X_AUX_INT_CLK_CTRL, 0x50}, ++ {WCD938X_AUX_INT_TEST_CTRL, 0x00}, ++ {WCD938X_AUX_INT_STATUS_REG, 0x00}, ++ {WCD938X_AUX_INT_MISC, 0x00}, ++ {WCD938X_LDORXTX_INT_BIAS, 0x6E}, ++ {WCD938X_LDORXTX_INT_STB_LOADS_DTEST, 0x50}, ++ {WCD938X_LDORXTX_INT_TEST0, 0x1C}, ++ {WCD938X_LDORXTX_INT_STARTUP_TIMER, 0xFF}, ++ {WCD938X_LDORXTX_INT_TEST1, 0x1F}, ++ {WCD938X_LDORXTX_INT_STATUS, 0x00}, ++ {WCD938X_SLEEP_INT_WATCHDOG_CTL_1, 0x0A}, ++ {WCD938X_SLEEP_INT_WATCHDOG_CTL_2, 0x0A}, ++ {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02}, ++ {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60}, ++ {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xFF}, ++ {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7F}, ++ {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3F}, ++ {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M, 0x1F}, ++ {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M, 0x0F}, ++ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1, 0xD7}, ++ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0, 0xC8}, ++ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP, 0xC6}, ++ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1, 0xD5}, ++ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0, 0xCA}, ++ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 0x05}, ++ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0, 0xA5}, ++ {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 0x13}, ++ {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88}, ++ {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP, 0x42}, ++ {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2, 0xFF}, ++ {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1, 0x64}, ++ {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0, 0x64}, ++ {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP, 0x77}, ++ {WCD938X_DIGITAL_PAGE_REGISTER, 0x00}, ++ {WCD938X_DIGITAL_CHIP_ID0, 0x00}, ++ {WCD938X_DIGITAL_CHIP_ID1, 0x00}, ++ {WCD938X_DIGITAL_CHIP_ID2, 0x0D}, ++ {WCD938X_DIGITAL_CHIP_ID3, 0x01}, ++ {WCD938X_DIGITAL_SWR_TX_CLK_RATE, 0x00}, ++ {WCD938X_DIGITAL_CDC_RST_CTL, 0x03}, ++ {WCD938X_DIGITAL_TOP_CLK_CFG, 0x00}, ++ {WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x00}, ++ {WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0}, ++ {WCD938X_DIGITAL_SWR_RST_EN, 0x00}, ++ {WCD938X_DIGITAL_CDC_PATH_MODE, 0x55}, ++ {WCD938X_DIGITAL_CDC_RX_RST, 0x00}, ++ {WCD938X_DIGITAL_CDC_RX0_CTL, 0xFC}, ++ {WCD938X_DIGITAL_CDC_RX1_CTL, 0xFC}, ++ {WCD938X_DIGITAL_CDC_RX2_CTL, 0xFC}, ++ {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x00}, ++ {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x00}, ++ {WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x00}, ++ {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x1E}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0, 0x00}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1, 0x01}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0, 0x63}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1, 0x04}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0, 0xAC}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1, 0x04}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0, 0x1A}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1, 0x03}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0, 0xBC}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1, 0x02}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0, 0xC7}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0, 0xF8}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_C_0, 0x47}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_C_1, 0x43}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_C_2, 0xB1}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_C_3, 0x17}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_R1, 0x4D}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_R2, 0x29}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_R3, 0x34}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_R4, 0x59}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_R5, 0x66}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_R6, 0x87}, ++ {WCD938X_DIGITAL_CDC_HPH_DSM_R7, 0x64}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0, 0x00}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1, 0x01}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0, 0x96}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1, 0x09}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0, 0xAB}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1, 0x05}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0, 0x1C}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1, 0x02}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0, 0x17}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1, 0x02}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0, 0xAA}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0, 0xE3}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_C_0, 0x69}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_C_1, 0x54}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_C_2, 0x02}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_C_3, 0x15}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_R1, 0xA4}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_R2, 0xB5}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_R3, 0x86}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_R4, 0x85}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_R5, 0xAA}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_R6, 0xE2}, ++ {WCD938X_DIGITAL_CDC_AUX_DSM_R7, 0x62}, ++ {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0, 0x55}, ++ {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1, 0xA9}, ++ {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0, 0x3D}, ++ {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1, 0x2E}, ++ {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2, 0x01}, ++ {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0, 0x00}, ++ {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1, 0xFC}, ++ {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2, 0x01}, ++ {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x00}, ++ {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x00}, ++ {WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0x00}, ++ {WCD938X_DIGITAL_CDC_SWR_CLH, 0x00}, ++ {WCD938X_DIGITAL_SWR_CLH_BYP, 0x00}, ++ {WCD938X_DIGITAL_CDC_TX0_CTL, 0x68}, ++ {WCD938X_DIGITAL_CDC_TX1_CTL, 0x68}, ++ {WCD938X_DIGITAL_CDC_TX2_CTL, 0x68}, ++ {WCD938X_DIGITAL_CDC_TX_RST, 0x00}, ++ {WCD938X_DIGITAL_CDC_REQ_CTL, 0x01}, ++ {WCD938X_DIGITAL_CDC_RST, 0x00}, ++ {WCD938X_DIGITAL_CDC_AMIC_CTL, 0x0F}, ++ {WCD938X_DIGITAL_CDC_DMIC_CTL, 0x04}, ++ {WCD938X_DIGITAL_CDC_DMIC1_CTL, 0x01}, ++ {WCD938X_DIGITAL_CDC_DMIC2_CTL, 0x01}, ++ {WCD938X_DIGITAL_CDC_DMIC3_CTL, 0x01}, ++ {WCD938X_DIGITAL_CDC_DMIC4_CTL, 0x01}, ++ {WCD938X_DIGITAL_EFUSE_PRG_CTL, 0x00}, ++ {WCD938X_DIGITAL_EFUSE_CTL, 0x2B}, ++ {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2, 0x11}, ++ {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4, 0x11}, ++ {WCD938X_DIGITAL_PDM_WD_CTL0, 0x00}, ++ {WCD938X_DIGITAL_PDM_WD_CTL1, 0x00}, ++ {WCD938X_DIGITAL_PDM_WD_CTL2, 0x00}, ++ {WCD938X_DIGITAL_INTR_MODE, 0x00}, ++ {WCD938X_DIGITAL_INTR_MASK_0, 0xFF}, ++ {WCD938X_DIGITAL_INTR_MASK_1, 0xFF}, ++ {WCD938X_DIGITAL_INTR_MASK_2, 0x3F}, ++ {WCD938X_DIGITAL_INTR_STATUS_0, 0x00}, ++ {WCD938X_DIGITAL_INTR_STATUS_1, 0x00}, ++ {WCD938X_DIGITAL_INTR_STATUS_2, 0x00}, ++ {WCD938X_DIGITAL_INTR_CLEAR_0, 0x00}, ++ {WCD938X_DIGITAL_INTR_CLEAR_1, 0x00}, ++ {WCD938X_DIGITAL_INTR_CLEAR_2, 0x00}, ++ {WCD938X_DIGITAL_INTR_LEVEL_0, 0x00}, ++ {WCD938X_DIGITAL_INTR_LEVEL_1, 0x00}, ++ {WCD938X_DIGITAL_INTR_LEVEL_2, 0x00}, ++ {WCD938X_DIGITAL_INTR_SET_0, 0x00}, ++ {WCD938X_DIGITAL_INTR_SET_1, 0x00}, ++ {WCD938X_DIGITAL_INTR_SET_2, 0x00}, ++ {WCD938X_DIGITAL_INTR_TEST_0, 0x00}, ++ {WCD938X_DIGITAL_INTR_TEST_1, 0x00}, ++ {WCD938X_DIGITAL_INTR_TEST_2, 0x00}, ++ {WCD938X_DIGITAL_TX_MODE_DBG_EN, 0x00}, ++ {WCD938X_DIGITAL_TX_MODE_DBG_0_1, 0x00}, ++ {WCD938X_DIGITAL_TX_MODE_DBG_2_3, 0x00}, ++ {WCD938X_DIGITAL_LB_IN_SEL_CTL, 0x00}, ++ {WCD938X_DIGITAL_LOOP_BACK_MODE, 0x00}, ++ {WCD938X_DIGITAL_SWR_DAC_TEST, 0x00}, ++ {WCD938X_DIGITAL_SWR_HM_TEST_RX_0, 0x40}, ++ {WCD938X_DIGITAL_SWR_HM_TEST_TX_0, 0x40}, ++ {WCD938X_DIGITAL_SWR_HM_TEST_RX_1, 0x00}, ++ {WCD938X_DIGITAL_SWR_HM_TEST_TX_1, 0x00}, ++ {WCD938X_DIGITAL_SWR_HM_TEST_TX_2, 0x00}, ++ {WCD938X_DIGITAL_SWR_HM_TEST_0, 0x00}, ++ {WCD938X_DIGITAL_SWR_HM_TEST_1, 0x00}, ++ {WCD938X_DIGITAL_PAD_CTL_SWR_0, 0x8F}, ++ {WCD938X_DIGITAL_PAD_CTL_SWR_1, 0x06}, ++ {WCD938X_DIGITAL_I2C_CTL, 0x00}, ++ {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE, 0x00}, ++ {WCD938X_DIGITAL_EFUSE_TEST_CTL_0, 0x00}, ++ {WCD938X_DIGITAL_EFUSE_TEST_CTL_1, 0x00}, ++ {WCD938X_DIGITAL_EFUSE_T_DATA_0, 0x00}, ++ {WCD938X_DIGITAL_EFUSE_T_DATA_1, 0x00}, ++ {WCD938X_DIGITAL_PAD_CTL_PDM_RX0, 0xF1}, ++ {WCD938X_DIGITAL_PAD_CTL_PDM_RX1, 0xF1}, ++ {WCD938X_DIGITAL_PAD_CTL_PDM_TX0, 0xF1}, ++ {WCD938X_DIGITAL_PAD_CTL_PDM_TX1, 0xF1}, ++ {WCD938X_DIGITAL_PAD_CTL_PDM_TX2, 0xF1}, ++ {WCD938X_DIGITAL_PAD_INP_DIS_0, 0x00}, ++ {WCD938X_DIGITAL_PAD_INP_DIS_1, 0x00}, ++ {WCD938X_DIGITAL_DRIVE_STRENGTH_0, 0x00}, ++ {WCD938X_DIGITAL_DRIVE_STRENGTH_1, 0x00}, ++ {WCD938X_DIGITAL_DRIVE_STRENGTH_2, 0x00}, ++ {WCD938X_DIGITAL_RX_DATA_EDGE_CTL, 0x1F}, ++ {WCD938X_DIGITAL_TX_DATA_EDGE_CTL, 0x80}, ++ {WCD938X_DIGITAL_GPIO_MODE, 0x00}, ++ {WCD938X_DIGITAL_PIN_CTL_OE, 0x00}, ++ {WCD938X_DIGITAL_PIN_CTL_DATA_0, 0x00}, ++ {WCD938X_DIGITAL_PIN_CTL_DATA_1, 0x00}, ++ {WCD938X_DIGITAL_PIN_STATUS_0, 0x00}, ++ {WCD938X_DIGITAL_PIN_STATUS_1, 0x00}, ++ {WCD938X_DIGITAL_DIG_DEBUG_CTL, 0x00}, ++ {WCD938X_DIGITAL_DIG_DEBUG_EN, 0x00}, ++ {WCD938X_DIGITAL_ANA_CSR_DBG_ADD, 0x00}, ++ {WCD938X_DIGITAL_ANA_CSR_DBG_CTL, 0x48}, ++ {WCD938X_DIGITAL_SSP_DBG, 0x00}, ++ {WCD938X_DIGITAL_MODE_STATUS_0, 0x00}, ++ {WCD938X_DIGITAL_MODE_STATUS_1, 0x00}, ++ {WCD938X_DIGITAL_SPARE_0, 0x00}, ++ {WCD938X_DIGITAL_SPARE_1, 0x00}, ++ {WCD938X_DIGITAL_SPARE_2, 0x00}, ++ {WCD938X_DIGITAL_EFUSE_REG_0, 0x00}, ++ {WCD938X_DIGITAL_EFUSE_REG_1, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_2, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_3, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_4, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_5, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_6, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_7, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_8, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_9, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_10, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_11, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_12, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_13, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_14, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_15, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_16, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_17, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_18, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_19, 0xFF}, ++ {WCD938X_DIGITAL_EFUSE_REG_20, 0x0E}, ++ {WCD938X_DIGITAL_EFUSE_REG_21, 0x00}, ++ {WCD938X_DIGITAL_EFUSE_REG_22, 0x00}, ++ {WCD938X_DIGITAL_EFUSE_REG_23, 0xF8}, ++ {WCD938X_DIGITAL_EFUSE_REG_24, 0x16}, ++ {WCD938X_DIGITAL_EFUSE_REG_25, 0x00}, ++ {WCD938X_DIGITAL_EFUSE_REG_26, 0x00}, ++ {WCD938X_DIGITAL_EFUSE_REG_27, 0x00}, ++ {WCD938X_DIGITAL_EFUSE_REG_28, 0x00}, ++ {WCD938X_DIGITAL_EFUSE_REG_29, 0x00}, ++ {WCD938X_DIGITAL_EFUSE_REG_30, 0x00}, ++ {WCD938X_DIGITAL_EFUSE_REG_31, 0x00}, ++ {WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0x88}, ++ {WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0x88}, ++ {WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0x88}, ++ {WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0x88}, ++ {WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0x88}, ++ {WCD938X_DIGITAL_DEM_BYPASS_DATA0, 0x55}, ++ {WCD938X_DIGITAL_DEM_BYPASS_DATA1, 0x55}, ++ {WCD938X_DIGITAL_DEM_BYPASS_DATA2, 0x55}, ++ {WCD938X_DIGITAL_DEM_BYPASS_DATA3, 0x01}, ++}; ++ ++static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case WCD938X_ANA_PAGE_REGISTER: ++ case WCD938X_ANA_BIAS: ++ case WCD938X_ANA_RX_SUPPLIES: ++ case WCD938X_ANA_HPH: ++ case WCD938X_ANA_EAR: ++ case WCD938X_ANA_EAR_COMPANDER_CTL: ++ case WCD938X_ANA_TX_CH1: ++ case WCD938X_ANA_TX_CH2: ++ case WCD938X_ANA_TX_CH3: ++ case WCD938X_ANA_TX_CH4: ++ case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC: ++ case WCD938X_ANA_MICB3_DSP_EN_LOGIC: ++ case WCD938X_ANA_MBHC_MECH: ++ case WCD938X_ANA_MBHC_ELECT: ++ case WCD938X_ANA_MBHC_ZDET: ++ case WCD938X_ANA_MBHC_BTN0: ++ case WCD938X_ANA_MBHC_BTN1: ++ case WCD938X_ANA_MBHC_BTN2: ++ case WCD938X_ANA_MBHC_BTN3: ++ case WCD938X_ANA_MBHC_BTN4: ++ case WCD938X_ANA_MBHC_BTN5: ++ case WCD938X_ANA_MBHC_BTN6: ++ case WCD938X_ANA_MBHC_BTN7: ++ case WCD938X_ANA_MICB1: ++ case WCD938X_ANA_MICB2: ++ case WCD938X_ANA_MICB2_RAMP: ++ case WCD938X_ANA_MICB3: ++ case WCD938X_ANA_MICB4: ++ case WCD938X_BIAS_CTL: ++ case WCD938X_BIAS_VBG_FINE_ADJ: ++ case WCD938X_LDOL_VDDCX_ADJUST: ++ case WCD938X_LDOL_DISABLE_LDOL: ++ case WCD938X_MBHC_CTL_CLK: ++ case WCD938X_MBHC_CTL_ANA: ++ case WCD938X_MBHC_CTL_SPARE_1: ++ case WCD938X_MBHC_CTL_SPARE_2: ++ case WCD938X_MBHC_CTL_BCS: ++ case WCD938X_MBHC_TEST_CTL: ++ case WCD938X_LDOH_MODE: ++ case WCD938X_LDOH_BIAS: ++ case WCD938X_LDOH_STB_LOADS: ++ case WCD938X_LDOH_SLOWRAMP: ++ case WCD938X_MICB1_TEST_CTL_1: ++ case WCD938X_MICB1_TEST_CTL_2: ++ case WCD938X_MICB1_TEST_CTL_3: ++ case WCD938X_MICB2_TEST_CTL_1: ++ case WCD938X_MICB2_TEST_CTL_2: ++ case WCD938X_MICB2_TEST_CTL_3: ++ case WCD938X_MICB3_TEST_CTL_1: ++ case WCD938X_MICB3_TEST_CTL_2: ++ case WCD938X_MICB3_TEST_CTL_3: ++ case WCD938X_MICB4_TEST_CTL_1: ++ case WCD938X_MICB4_TEST_CTL_2: ++ case WCD938X_MICB4_TEST_CTL_3: ++ case WCD938X_TX_COM_ADC_VCM: ++ case WCD938X_TX_COM_BIAS_ATEST: ++ case WCD938X_TX_COM_SPARE1: ++ case WCD938X_TX_COM_SPARE2: ++ case WCD938X_TX_COM_TXFE_DIV_CTL: ++ case WCD938X_TX_COM_TXFE_DIV_START: ++ case WCD938X_TX_COM_SPARE3: ++ case WCD938X_TX_COM_SPARE4: ++ case WCD938X_TX_1_2_TEST_EN: ++ case WCD938X_TX_1_2_ADC_IB: ++ case WCD938X_TX_1_2_ATEST_REFCTL: ++ case WCD938X_TX_1_2_TEST_CTL: ++ case WCD938X_TX_1_2_TEST_BLK_EN1: ++ case WCD938X_TX_1_2_TXFE1_CLKDIV: ++ case WCD938X_TX_3_4_TEST_EN: ++ case WCD938X_TX_3_4_ADC_IB: ++ case WCD938X_TX_3_4_ATEST_REFCTL: ++ case WCD938X_TX_3_4_TEST_CTL: ++ case WCD938X_TX_3_4_TEST_BLK_EN3: ++ case WCD938X_TX_3_4_TXFE3_CLKDIV: ++ case WCD938X_TX_3_4_TEST_BLK_EN2: ++ case WCD938X_TX_3_4_TXFE2_CLKDIV: ++ case WCD938X_TX_3_4_SPARE1: ++ case WCD938X_TX_3_4_TEST_BLK_EN4: ++ case WCD938X_TX_3_4_TXFE4_CLKDIV: ++ case WCD938X_TX_3_4_SPARE2: ++ case WCD938X_CLASSH_MODE_1: ++ case WCD938X_CLASSH_MODE_2: ++ case WCD938X_CLASSH_MODE_3: ++ case WCD938X_CLASSH_CTRL_VCL_1: ++ case WCD938X_CLASSH_CTRL_VCL_2: ++ case WCD938X_CLASSH_CTRL_CCL_1: ++ case WCD938X_CLASSH_CTRL_CCL_2: ++ case WCD938X_CLASSH_CTRL_CCL_3: ++ case WCD938X_CLASSH_CTRL_CCL_4: ++ case WCD938X_CLASSH_CTRL_CCL_5: ++ case WCD938X_CLASSH_BUCK_TMUX_A_D: ++ case WCD938X_CLASSH_BUCK_SW_DRV_CNTL: ++ case WCD938X_CLASSH_SPARE: ++ case WCD938X_FLYBACK_EN: ++ case WCD938X_FLYBACK_VNEG_CTRL_1: ++ case WCD938X_FLYBACK_VNEG_CTRL_2: ++ case WCD938X_FLYBACK_VNEG_CTRL_3: ++ case WCD938X_FLYBACK_VNEG_CTRL_4: ++ case WCD938X_FLYBACK_VNEG_CTRL_5: ++ case WCD938X_FLYBACK_VNEG_CTRL_6: ++ case WCD938X_FLYBACK_VNEG_CTRL_7: ++ case WCD938X_FLYBACK_VNEG_CTRL_8: ++ case WCD938X_FLYBACK_VNEG_CTRL_9: ++ case WCD938X_FLYBACK_VNEGDAC_CTRL_1: ++ case WCD938X_FLYBACK_VNEGDAC_CTRL_2: ++ case WCD938X_FLYBACK_VNEGDAC_CTRL_3: ++ case WCD938X_FLYBACK_CTRL_1: ++ case WCD938X_FLYBACK_TEST_CTL: ++ case WCD938X_RX_AUX_SW_CTL: ++ case WCD938X_RX_PA_AUX_IN_CONN: ++ case WCD938X_RX_TIMER_DIV: ++ case WCD938X_RX_OCP_CTL: ++ case WCD938X_RX_OCP_COUNT: ++ case WCD938X_RX_BIAS_EAR_DAC: ++ case WCD938X_RX_BIAS_EAR_AMP: ++ case WCD938X_RX_BIAS_HPH_LDO: ++ case WCD938X_RX_BIAS_HPH_PA: ++ case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2: ++ case WCD938X_RX_BIAS_HPH_RDAC_LDO: ++ case WCD938X_RX_BIAS_HPH_CNP1: ++ case WCD938X_RX_BIAS_HPH_LOWPOWER: ++ case WCD938X_RX_BIAS_AUX_DAC: ++ case WCD938X_RX_BIAS_AUX_AMP: ++ case WCD938X_RX_BIAS_VNEGDAC_BLEEDER: ++ case WCD938X_RX_BIAS_MISC: ++ case WCD938X_RX_BIAS_BUCK_RST: ++ case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP: ++ case WCD938X_RX_BIAS_FLYB_ERRAMP: ++ case WCD938X_RX_BIAS_FLYB_BUFF: ++ case WCD938X_RX_BIAS_FLYB_MID_RST: ++ case WCD938X_HPH_CNP_EN: ++ case WCD938X_HPH_CNP_WG_CTL: ++ case WCD938X_HPH_CNP_WG_TIME: ++ case WCD938X_HPH_OCP_CTL: ++ case WCD938X_HPH_AUTO_CHOP: ++ case WCD938X_HPH_CHOP_CTL: ++ case WCD938X_HPH_PA_CTL1: ++ case WCD938X_HPH_PA_CTL2: ++ case WCD938X_HPH_L_EN: ++ case WCD938X_HPH_L_TEST: ++ case WCD938X_HPH_L_ATEST: ++ case WCD938X_HPH_R_EN: ++ case WCD938X_HPH_R_TEST: ++ case WCD938X_HPH_R_ATEST: ++ case WCD938X_HPH_RDAC_CLK_CTL1: ++ case WCD938X_HPH_RDAC_CLK_CTL2: ++ case WCD938X_HPH_RDAC_LDO_CTL: ++ case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL: ++ case WCD938X_HPH_REFBUFF_UHQA_CTL: ++ case WCD938X_HPH_REFBUFF_LP_CTL: ++ case WCD938X_HPH_L_DAC_CTL: ++ case WCD938X_HPH_R_DAC_CTL: ++ case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL: ++ case WCD938X_HPH_SURGE_HPHLR_SURGE_EN: ++ case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1: ++ case WCD938X_EAR_EAR_EN_REG: ++ case WCD938X_EAR_EAR_PA_CON: ++ case WCD938X_EAR_EAR_SP_CON: ++ case WCD938X_EAR_EAR_DAC_CON: ++ case WCD938X_EAR_EAR_CNP_FSM_CON: ++ case WCD938X_EAR_TEST_CTL: ++ case WCD938X_ANA_NEW_PAGE_REGISTER: ++ case WCD938X_HPH_NEW_ANA_HPH2: ++ case WCD938X_HPH_NEW_ANA_HPH3: ++ case WCD938X_SLEEP_CTL: ++ case WCD938X_SLEEP_WATCHDOG_CTL: ++ case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL: ++ case WCD938X_MBHC_NEW_CTL_1: ++ case WCD938X_MBHC_NEW_CTL_2: ++ case WCD938X_MBHC_NEW_PLUG_DETECT_CTL: ++ case WCD938X_MBHC_NEW_ZDET_ANA_CTL: ++ case WCD938X_MBHC_NEW_ZDET_RAMP_CTL: ++ case WCD938X_TX_NEW_AMIC_MUX_CFG: ++ case WCD938X_AUX_AUXPA: ++ case WCD938X_LDORXTX_MODE: ++ case WCD938X_LDORXTX_CONFIG: ++ case WCD938X_DIE_CRACK_DIE_CRK_DET_EN: ++ case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL: ++ case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L: ++ case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL: ++ case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL: ++ case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R: ++ case WCD938X_HPH_NEW_INT_PA_MISC1: ++ case WCD938X_HPH_NEW_INT_PA_MISC2: ++ case WCD938X_HPH_NEW_INT_PA_RDAC_MISC: ++ case WCD938X_HPH_NEW_INT_HPH_TIMER1: ++ case WCD938X_HPH_NEW_INT_HPH_TIMER2: ++ case WCD938X_HPH_NEW_INT_HPH_TIMER3: ++ case WCD938X_HPH_NEW_INT_HPH_TIMER4: ++ case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2: ++ case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3: ++ case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW: ++ case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW: ++ case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI: ++ case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP: ++ case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP: ++ case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL: ++ case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL: ++ case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT: ++ case WCD938X_MBHC_NEW_INT_SPARE_2: ++ case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON: ++ case WCD938X_EAR_INT_NEW_CNP_VCM_CON1: ++ case WCD938X_EAR_INT_NEW_CNP_VCM_CON2: ++ case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS: ++ case WCD938X_AUX_INT_EN_REG: ++ case WCD938X_AUX_INT_PA_CTRL: ++ case WCD938X_AUX_INT_SP_CTRL: ++ case WCD938X_AUX_INT_DAC_CTRL: ++ case WCD938X_AUX_INT_CLK_CTRL: ++ case WCD938X_AUX_INT_TEST_CTRL: ++ case WCD938X_AUX_INT_MISC: ++ case WCD938X_LDORXTX_INT_BIAS: ++ case WCD938X_LDORXTX_INT_STB_LOADS_DTEST: ++ case WCD938X_LDORXTX_INT_TEST0: ++ case WCD938X_LDORXTX_INT_STARTUP_TIMER: ++ case WCD938X_LDORXTX_INT_TEST1: ++ case WCD938X_SLEEP_INT_WATCHDOG_CTL_1: ++ case WCD938X_SLEEP_INT_WATCHDOG_CTL_2: ++ case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1: ++ case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2: ++ case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2: ++ case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1: ++ case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0: ++ case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M: ++ case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M: ++ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1: ++ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0: ++ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP: ++ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1: ++ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0: ++ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP: ++ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0: ++ case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP: ++ case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1: ++ case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP: ++ case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2: ++ case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1: ++ case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0: ++ case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP: ++ case WCD938X_DIGITAL_PAGE_REGISTER: ++ case WCD938X_DIGITAL_SWR_TX_CLK_RATE: ++ case WCD938X_DIGITAL_CDC_RST_CTL: ++ case WCD938X_DIGITAL_TOP_CLK_CFG: ++ case WCD938X_DIGITAL_CDC_ANA_CLK_CTL: ++ case WCD938X_DIGITAL_CDC_DIG_CLK_CTL: ++ case WCD938X_DIGITAL_SWR_RST_EN: ++ case WCD938X_DIGITAL_CDC_PATH_MODE: ++ case WCD938X_DIGITAL_CDC_RX_RST: ++ case WCD938X_DIGITAL_CDC_RX0_CTL: ++ case WCD938X_DIGITAL_CDC_RX1_CTL: ++ case WCD938X_DIGITAL_CDC_RX2_CTL: ++ case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1: ++ case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3: ++ case WCD938X_DIGITAL_CDC_COMP_CTL_0: ++ case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_C_0: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_C_1: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_C_2: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_C_3: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_R1: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_R2: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_R3: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_R4: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_R5: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_R6: ++ case WCD938X_DIGITAL_CDC_HPH_DSM_R7: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_C_0: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_C_1: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_C_2: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_C_3: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_R1: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_R2: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_R3: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_R4: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_R5: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_R6: ++ case WCD938X_DIGITAL_CDC_AUX_DSM_R7: ++ case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0: ++ case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1: ++ case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0: ++ case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1: ++ case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2: ++ case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0: ++ case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1: ++ case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2: ++ case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL: ++ case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL: ++ case WCD938X_DIGITAL_CDC_EAR_PATH_CTL: ++ case WCD938X_DIGITAL_CDC_SWR_CLH: ++ case WCD938X_DIGITAL_SWR_CLH_BYP: ++ case WCD938X_DIGITAL_CDC_TX0_CTL: ++ case WCD938X_DIGITAL_CDC_TX1_CTL: ++ case WCD938X_DIGITAL_CDC_TX2_CTL: ++ case WCD938X_DIGITAL_CDC_TX_RST: ++ case WCD938X_DIGITAL_CDC_REQ_CTL: ++ case WCD938X_DIGITAL_CDC_RST: ++ case WCD938X_DIGITAL_CDC_AMIC_CTL: ++ case WCD938X_DIGITAL_CDC_DMIC_CTL: ++ case WCD938X_DIGITAL_CDC_DMIC1_CTL: ++ case WCD938X_DIGITAL_CDC_DMIC2_CTL: ++ case WCD938X_DIGITAL_CDC_DMIC3_CTL: ++ case WCD938X_DIGITAL_CDC_DMIC4_CTL: ++ case WCD938X_DIGITAL_EFUSE_PRG_CTL: ++ case WCD938X_DIGITAL_EFUSE_CTL: ++ case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2: ++ case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4: ++ case WCD938X_DIGITAL_PDM_WD_CTL0: ++ case WCD938X_DIGITAL_PDM_WD_CTL1: ++ case WCD938X_DIGITAL_PDM_WD_CTL2: ++ case WCD938X_DIGITAL_INTR_MODE: ++ case WCD938X_DIGITAL_INTR_MASK_0: ++ case WCD938X_DIGITAL_INTR_MASK_1: ++ case WCD938X_DIGITAL_INTR_MASK_2: ++ case WCD938X_DIGITAL_INTR_CLEAR_0: ++ case WCD938X_DIGITAL_INTR_CLEAR_1: ++ case WCD938X_DIGITAL_INTR_CLEAR_2: ++ case WCD938X_DIGITAL_INTR_LEVEL_0: ++ case WCD938X_DIGITAL_INTR_LEVEL_1: ++ case WCD938X_DIGITAL_INTR_LEVEL_2: ++ case WCD938X_DIGITAL_INTR_SET_0: ++ case WCD938X_DIGITAL_INTR_SET_1: ++ case WCD938X_DIGITAL_INTR_SET_2: ++ case WCD938X_DIGITAL_INTR_TEST_0: ++ case WCD938X_DIGITAL_INTR_TEST_1: ++ case WCD938X_DIGITAL_INTR_TEST_2: ++ case WCD938X_DIGITAL_TX_MODE_DBG_EN: ++ case WCD938X_DIGITAL_TX_MODE_DBG_0_1: ++ case WCD938X_DIGITAL_TX_MODE_DBG_2_3: ++ case WCD938X_DIGITAL_LB_IN_SEL_CTL: ++ case WCD938X_DIGITAL_LOOP_BACK_MODE: ++ case WCD938X_DIGITAL_SWR_DAC_TEST: ++ case WCD938X_DIGITAL_SWR_HM_TEST_RX_0: ++ case WCD938X_DIGITAL_SWR_HM_TEST_TX_0: ++ case WCD938X_DIGITAL_SWR_HM_TEST_RX_1: ++ case WCD938X_DIGITAL_SWR_HM_TEST_TX_1: ++ case WCD938X_DIGITAL_SWR_HM_TEST_TX_2: ++ case WCD938X_DIGITAL_PAD_CTL_SWR_0: ++ case WCD938X_DIGITAL_PAD_CTL_SWR_1: ++ case WCD938X_DIGITAL_I2C_CTL: ++ case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE: ++ case WCD938X_DIGITAL_EFUSE_TEST_CTL_0: ++ case WCD938X_DIGITAL_EFUSE_TEST_CTL_1: ++ case WCD938X_DIGITAL_PAD_CTL_PDM_RX0: ++ case WCD938X_DIGITAL_PAD_CTL_PDM_RX1: ++ case WCD938X_DIGITAL_PAD_CTL_PDM_TX0: ++ case WCD938X_DIGITAL_PAD_CTL_PDM_TX1: ++ case WCD938X_DIGITAL_PAD_CTL_PDM_TX2: ++ case WCD938X_DIGITAL_PAD_INP_DIS_0: ++ case WCD938X_DIGITAL_PAD_INP_DIS_1: ++ case WCD938X_DIGITAL_DRIVE_STRENGTH_0: ++ case WCD938X_DIGITAL_DRIVE_STRENGTH_1: ++ case WCD938X_DIGITAL_DRIVE_STRENGTH_2: ++ case WCD938X_DIGITAL_RX_DATA_EDGE_CTL: ++ case WCD938X_DIGITAL_TX_DATA_EDGE_CTL: ++ case WCD938X_DIGITAL_GPIO_MODE: ++ case WCD938X_DIGITAL_PIN_CTL_OE: ++ case WCD938X_DIGITAL_PIN_CTL_DATA_0: ++ case WCD938X_DIGITAL_PIN_CTL_DATA_1: ++ case WCD938X_DIGITAL_DIG_DEBUG_CTL: ++ case WCD938X_DIGITAL_DIG_DEBUG_EN: ++ case WCD938X_DIGITAL_ANA_CSR_DBG_ADD: ++ case WCD938X_DIGITAL_ANA_CSR_DBG_CTL: ++ case WCD938X_DIGITAL_SSP_DBG: ++ case WCD938X_DIGITAL_SPARE_0: ++ case WCD938X_DIGITAL_SPARE_1: ++ case WCD938X_DIGITAL_SPARE_2: ++ case WCD938X_DIGITAL_TX_REQ_FB_CTL_0: ++ case WCD938X_DIGITAL_TX_REQ_FB_CTL_1: ++ case WCD938X_DIGITAL_TX_REQ_FB_CTL_2: ++ case WCD938X_DIGITAL_TX_REQ_FB_CTL_3: ++ case WCD938X_DIGITAL_TX_REQ_FB_CTL_4: ++ case WCD938X_DIGITAL_DEM_BYPASS_DATA0: ++ case WCD938X_DIGITAL_DEM_BYPASS_DATA1: ++ case WCD938X_DIGITAL_DEM_BYPASS_DATA2: ++ case WCD938X_DIGITAL_DEM_BYPASS_DATA3: ++ return true; ++ } ++ ++ return false; ++} ++ ++static bool wcd938x_readonly_register(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case WCD938X_ANA_MBHC_RESULT_1: ++ case WCD938X_ANA_MBHC_RESULT_2: ++ case WCD938X_ANA_MBHC_RESULT_3: ++ case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS: ++ case WCD938X_TX_1_2_SAR2_ERR: ++ case WCD938X_TX_1_2_SAR1_ERR: ++ case WCD938X_TX_3_4_SAR4_ERR: ++ case WCD938X_TX_3_4_SAR3_ERR: ++ case WCD938X_HPH_L_STATUS: ++ case WCD938X_HPH_R_STATUS: ++ case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS: ++ case WCD938X_EAR_STATUS_REG_1: ++ case WCD938X_EAR_STATUS_REG_2: ++ case WCD938X_MBHC_NEW_FSM_STATUS: ++ case WCD938X_MBHC_NEW_ADC_RESULT: ++ case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT: ++ case WCD938X_AUX_INT_STATUS_REG: ++ case WCD938X_LDORXTX_INT_STATUS: ++ case WCD938X_DIGITAL_CHIP_ID0: ++ case WCD938X_DIGITAL_CHIP_ID1: ++ case WCD938X_DIGITAL_CHIP_ID2: ++ case WCD938X_DIGITAL_CHIP_ID3: ++ case WCD938X_DIGITAL_INTR_STATUS_0: ++ case WCD938X_DIGITAL_INTR_STATUS_1: ++ case WCD938X_DIGITAL_INTR_STATUS_2: ++ case WCD938X_DIGITAL_INTR_CLEAR_0: ++ case WCD938X_DIGITAL_INTR_CLEAR_1: ++ case WCD938X_DIGITAL_INTR_CLEAR_2: ++ case WCD938X_DIGITAL_SWR_HM_TEST_0: ++ case WCD938X_DIGITAL_SWR_HM_TEST_1: ++ case WCD938X_DIGITAL_EFUSE_T_DATA_0: ++ case WCD938X_DIGITAL_EFUSE_T_DATA_1: ++ case WCD938X_DIGITAL_PIN_STATUS_0: ++ case WCD938X_DIGITAL_PIN_STATUS_1: ++ case WCD938X_DIGITAL_MODE_STATUS_0: ++ case WCD938X_DIGITAL_MODE_STATUS_1: ++ case WCD938X_DIGITAL_EFUSE_REG_0: ++ case WCD938X_DIGITAL_EFUSE_REG_1: ++ case WCD938X_DIGITAL_EFUSE_REG_2: ++ case WCD938X_DIGITAL_EFUSE_REG_3: ++ case WCD938X_DIGITAL_EFUSE_REG_4: ++ case WCD938X_DIGITAL_EFUSE_REG_5: ++ case WCD938X_DIGITAL_EFUSE_REG_6: ++ case WCD938X_DIGITAL_EFUSE_REG_7: ++ case WCD938X_DIGITAL_EFUSE_REG_8: ++ case WCD938X_DIGITAL_EFUSE_REG_9: ++ case WCD938X_DIGITAL_EFUSE_REG_10: ++ case WCD938X_DIGITAL_EFUSE_REG_11: ++ case WCD938X_DIGITAL_EFUSE_REG_12: ++ case WCD938X_DIGITAL_EFUSE_REG_13: ++ case WCD938X_DIGITAL_EFUSE_REG_14: ++ case WCD938X_DIGITAL_EFUSE_REG_15: ++ case WCD938X_DIGITAL_EFUSE_REG_16: ++ case WCD938X_DIGITAL_EFUSE_REG_17: ++ case WCD938X_DIGITAL_EFUSE_REG_18: ++ case WCD938X_DIGITAL_EFUSE_REG_19: ++ case WCD938X_DIGITAL_EFUSE_REG_20: ++ case WCD938X_DIGITAL_EFUSE_REG_21: ++ case WCD938X_DIGITAL_EFUSE_REG_22: ++ case WCD938X_DIGITAL_EFUSE_REG_23: ++ case WCD938X_DIGITAL_EFUSE_REG_24: ++ case WCD938X_DIGITAL_EFUSE_REG_25: ++ case WCD938X_DIGITAL_EFUSE_REG_26: ++ case WCD938X_DIGITAL_EFUSE_REG_27: ++ case WCD938X_DIGITAL_EFUSE_REG_28: ++ case WCD938X_DIGITAL_EFUSE_REG_29: ++ case WCD938X_DIGITAL_EFUSE_REG_30: ++ case WCD938X_DIGITAL_EFUSE_REG_31: ++ return true; ++ } ++ return false; ++} ++ ++static bool wcd938x_readable_register(struct device *dev, unsigned int reg) ++{ ++ bool ret; ++ ++ ret = wcd938x_readonly_register(dev, reg); ++ if (!ret) ++ return wcd938x_rdwr_register(dev, reg); ++ ++ return ret; ++} ++ ++static bool wcd938x_writeable_register(struct device *dev, unsigned int reg) ++{ ++ return wcd938x_rdwr_register(dev, reg); ++} ++ ++static bool wcd938x_volatile_register(struct device *dev, unsigned int reg) ++{ ++ if (reg <= WCD938X_BASE_ADDRESS) ++ return false; ++ ++ if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE) ++ return true; ++ ++ if (wcd938x_readonly_register(dev, reg)) ++ return true; ++ ++ return false; ++} ++ ++static const struct regmap_config wcd938x_regmap_config = { ++ .name = "wcd938x_csr", ++ .reg_bits = 32, ++ .val_bits = 8, ++ .cache_type = REGCACHE_RBTREE, ++ .reg_defaults = wcd938x_defaults, ++ .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults), ++ .max_register = WCD938X_MAX_REGISTER, ++ .readable_reg = wcd938x_readable_register, ++ .writeable_reg = wcd938x_writeable_register, ++ .volatile_reg = wcd938x_volatile_register, ++ .can_multi_write = true, ++}; ++ + static const struct sdw_slave_ops wcd9380_slave_ops = { + .update_status = wcd9380_update_status, + .interrupt_callback = wcd9380_interrupt_callback, +@@ -261,6 +1263,16 @@ static int wcd9380_probe(struct sdw_slav + wcd->ch_info = &wcd938x_sdw_rx_ch_info[0]; + } + ++ if (wcd->is_tx) { ++ wcd->regmap = devm_regmap_init_sdw(pdev, &wcd938x_regmap_config); ++ if (IS_ERR(wcd->regmap)) ++ return dev_err_probe(dev, PTR_ERR(wcd->regmap), ++ "Regmap init failed\n"); ++ ++ /* Start in cache-only until device is enumerated */ ++ regcache_cache_only(wcd->regmap, true); ++ }; ++ + pm_runtime_set_autosuspend_delay(dev, 3000); + pm_runtime_use_autosuspend(dev); + pm_runtime_mark_last_busy(dev); +@@ -278,22 +1290,23 @@ MODULE_DEVICE_TABLE(sdw, wcd9380_slave_i + + static int __maybe_unused wcd938x_sdw_runtime_suspend(struct device *dev) + { +- struct regmap *regmap = dev_get_regmap(dev, NULL); ++ struct wcd938x_sdw_priv *wcd = dev_get_drvdata(dev); + +- if (regmap) { +- regcache_cache_only(regmap, true); +- regcache_mark_dirty(regmap); ++ if (wcd->regmap) { ++ regcache_cache_only(wcd->regmap, true); ++ regcache_mark_dirty(wcd->regmap); + } ++ + return 0; + } + + static int __maybe_unused wcd938x_sdw_runtime_resume(struct device *dev) + { +- struct regmap *regmap = dev_get_regmap(dev, NULL); ++ struct wcd938x_sdw_priv *wcd = dev_get_drvdata(dev); + +- if (regmap) { +- regcache_cache_only(regmap, false); +- regcache_sync(regmap); ++ if (wcd->regmap) { ++ regcache_cache_only(wcd->regmap, false); ++ regcache_sync(wcd->regmap); + } + + pm_runtime_mark_last_busy(dev); +--- a/sound/soc/codecs/wcd938x.c ++++ b/sound/soc/codecs/wcd938x.c +@@ -273,1001 +273,6 @@ static struct wcd_mbhc_field wcd_mbhc_fi + WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02), + }; + +-static const struct reg_default wcd938x_defaults[] = { +- {WCD938X_ANA_PAGE_REGISTER, 0x00}, +- {WCD938X_ANA_BIAS, 0x00}, +- {WCD938X_ANA_RX_SUPPLIES, 0x00}, +- {WCD938X_ANA_HPH, 0x0C}, +- {WCD938X_ANA_EAR, 0x00}, +- {WCD938X_ANA_EAR_COMPANDER_CTL, 0x02}, +- {WCD938X_ANA_TX_CH1, 0x20}, +- {WCD938X_ANA_TX_CH2, 0x00}, +- {WCD938X_ANA_TX_CH3, 0x20}, +- {WCD938X_ANA_TX_CH4, 0x00}, +- {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00}, +- {WCD938X_ANA_MICB3_DSP_EN_LOGIC, 0x00}, +- {WCD938X_ANA_MBHC_MECH, 0x39}, +- {WCD938X_ANA_MBHC_ELECT, 0x08}, +- {WCD938X_ANA_MBHC_ZDET, 0x00}, +- {WCD938X_ANA_MBHC_RESULT_1, 0x00}, +- {WCD938X_ANA_MBHC_RESULT_2, 0x00}, +- {WCD938X_ANA_MBHC_RESULT_3, 0x00}, +- {WCD938X_ANA_MBHC_BTN0, 0x00}, +- {WCD938X_ANA_MBHC_BTN1, 0x10}, +- {WCD938X_ANA_MBHC_BTN2, 0x20}, +- {WCD938X_ANA_MBHC_BTN3, 0x30}, +- {WCD938X_ANA_MBHC_BTN4, 0x40}, +- {WCD938X_ANA_MBHC_BTN5, 0x50}, +- {WCD938X_ANA_MBHC_BTN6, 0x60}, +- {WCD938X_ANA_MBHC_BTN7, 0x70}, +- {WCD938X_ANA_MICB1, 0x10}, +- {WCD938X_ANA_MICB2, 0x10}, +- {WCD938X_ANA_MICB2_RAMP, 0x00}, +- {WCD938X_ANA_MICB3, 0x10}, +- {WCD938X_ANA_MICB4, 0x10}, +- {WCD938X_BIAS_CTL, 0x2A}, +- {WCD938X_BIAS_VBG_FINE_ADJ, 0x55}, +- {WCD938X_LDOL_VDDCX_ADJUST, 0x01}, +- {WCD938X_LDOL_DISABLE_LDOL, 0x00}, +- {WCD938X_MBHC_CTL_CLK, 0x00}, +- {WCD938X_MBHC_CTL_ANA, 0x00}, +- {WCD938X_MBHC_CTL_SPARE_1, 0x00}, +- {WCD938X_MBHC_CTL_SPARE_2, 0x00}, +- {WCD938X_MBHC_CTL_BCS, 0x00}, +- {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS, 0x00}, +- {WCD938X_MBHC_TEST_CTL, 0x00}, +- {WCD938X_LDOH_MODE, 0x2B}, +- {WCD938X_LDOH_BIAS, 0x68}, +- {WCD938X_LDOH_STB_LOADS, 0x00}, +- {WCD938X_LDOH_SLOWRAMP, 0x50}, +- {WCD938X_MICB1_TEST_CTL_1, 0x1A}, +- {WCD938X_MICB1_TEST_CTL_2, 0x00}, +- {WCD938X_MICB1_TEST_CTL_3, 0xA4}, +- {WCD938X_MICB2_TEST_CTL_1, 0x1A}, +- {WCD938X_MICB2_TEST_CTL_2, 0x00}, +- {WCD938X_MICB2_TEST_CTL_3, 0x24}, +- {WCD938X_MICB3_TEST_CTL_1, 0x1A}, +- {WCD938X_MICB3_TEST_CTL_2, 0x00}, +- {WCD938X_MICB3_TEST_CTL_3, 0xA4}, +- {WCD938X_MICB4_TEST_CTL_1, 0x1A}, +- {WCD938X_MICB4_TEST_CTL_2, 0x00}, +- {WCD938X_MICB4_TEST_CTL_3, 0xA4}, +- {WCD938X_TX_COM_ADC_VCM, 0x39}, +- {WCD938X_TX_COM_BIAS_ATEST, 0xE0}, +- {WCD938X_TX_COM_SPARE1, 0x00}, +- {WCD938X_TX_COM_SPARE2, 0x00}, +- {WCD938X_TX_COM_TXFE_DIV_CTL, 0x22}, +- {WCD938X_TX_COM_TXFE_DIV_START, 0x00}, +- {WCD938X_TX_COM_SPARE3, 0x00}, +- {WCD938X_TX_COM_SPARE4, 0x00}, +- {WCD938X_TX_1_2_TEST_EN, 0xCC}, +- {WCD938X_TX_1_2_ADC_IB, 0xE9}, +- {WCD938X_TX_1_2_ATEST_REFCTL, 0x0A}, +- {WCD938X_TX_1_2_TEST_CTL, 0x38}, +- {WCD938X_TX_1_2_TEST_BLK_EN1, 0xFF}, +- {WCD938X_TX_1_2_TXFE1_CLKDIV, 0x00}, +- {WCD938X_TX_1_2_SAR2_ERR, 0x00}, +- {WCD938X_TX_1_2_SAR1_ERR, 0x00}, +- {WCD938X_TX_3_4_TEST_EN, 0xCC}, +- {WCD938X_TX_3_4_ADC_IB, 0xE9}, +- {WCD938X_TX_3_4_ATEST_REFCTL, 0x0A}, +- {WCD938X_TX_3_4_TEST_CTL, 0x38}, +- {WCD938X_TX_3_4_TEST_BLK_EN3, 0xFF}, +- {WCD938X_TX_3_4_TXFE3_CLKDIV, 0x00}, +- {WCD938X_TX_3_4_SAR4_ERR, 0x00}, +- {WCD938X_TX_3_4_SAR3_ERR, 0x00}, +- {WCD938X_TX_3_4_TEST_BLK_EN2, 0xFB}, +- {WCD938X_TX_3_4_TXFE2_CLKDIV, 0x00}, +- {WCD938X_TX_3_4_SPARE1, 0x00}, +- {WCD938X_TX_3_4_TEST_BLK_EN4, 0xFB}, +- {WCD938X_TX_3_4_TXFE4_CLKDIV, 0x00}, +- {WCD938X_TX_3_4_SPARE2, 0x00}, +- {WCD938X_CLASSH_MODE_1, 0x40}, +- {WCD938X_CLASSH_MODE_2, 0x3A}, +- {WCD938X_CLASSH_MODE_3, 0x00}, +- {WCD938X_CLASSH_CTRL_VCL_1, 0x70}, +- {WCD938X_CLASSH_CTRL_VCL_2, 0x82}, +- {WCD938X_CLASSH_CTRL_CCL_1, 0x31}, +- {WCD938X_CLASSH_CTRL_CCL_2, 0x80}, +- {WCD938X_CLASSH_CTRL_CCL_3, 0x80}, +- {WCD938X_CLASSH_CTRL_CCL_4, 0x51}, +- {WCD938X_CLASSH_CTRL_CCL_5, 0x00}, +- {WCD938X_CLASSH_BUCK_TMUX_A_D, 0x00}, +- {WCD938X_CLASSH_BUCK_SW_DRV_CNTL, 0x77}, +- {WCD938X_CLASSH_SPARE, 0x00}, +- {WCD938X_FLYBACK_EN, 0x4E}, +- {WCD938X_FLYBACK_VNEG_CTRL_1, 0x0B}, +- {WCD938X_FLYBACK_VNEG_CTRL_2, 0x45}, +- {WCD938X_FLYBACK_VNEG_CTRL_3, 0x74}, +- {WCD938X_FLYBACK_VNEG_CTRL_4, 0x7F}, +- {WCD938X_FLYBACK_VNEG_CTRL_5, 0x83}, +- {WCD938X_FLYBACK_VNEG_CTRL_6, 0x98}, +- {WCD938X_FLYBACK_VNEG_CTRL_7, 0xA9}, +- {WCD938X_FLYBACK_VNEG_CTRL_8, 0x68}, +- {WCD938X_FLYBACK_VNEG_CTRL_9, 0x64}, +- {WCD938X_FLYBACK_VNEGDAC_CTRL_1, 0xED}, +- {WCD938X_FLYBACK_VNEGDAC_CTRL_2, 0xF0}, +- {WCD938X_FLYBACK_VNEGDAC_CTRL_3, 0xA6}, +- {WCD938X_FLYBACK_CTRL_1, 0x65}, +- {WCD938X_FLYBACK_TEST_CTL, 0x00}, +- {WCD938X_RX_AUX_SW_CTL, 0x00}, +- {WCD938X_RX_PA_AUX_IN_CONN, 0x01}, +- {WCD938X_RX_TIMER_DIV, 0x32}, +- {WCD938X_RX_OCP_CTL, 0x1F}, +- {WCD938X_RX_OCP_COUNT, 0x77}, +- {WCD938X_RX_BIAS_EAR_DAC, 0xA0}, +- {WCD938X_RX_BIAS_EAR_AMP, 0xAA}, +- {WCD938X_RX_BIAS_HPH_LDO, 0xA9}, +- {WCD938X_RX_BIAS_HPH_PA, 0xAA}, +- {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A}, +- {WCD938X_RX_BIAS_HPH_RDAC_LDO, 0x88}, +- {WCD938X_RX_BIAS_HPH_CNP1, 0x82}, +- {WCD938X_RX_BIAS_HPH_LOWPOWER, 0x82}, +- {WCD938X_RX_BIAS_AUX_DAC, 0xA0}, +- {WCD938X_RX_BIAS_AUX_AMP, 0xAA}, +- {WCD938X_RX_BIAS_VNEGDAC_BLEEDER, 0x50}, +- {WCD938X_RX_BIAS_MISC, 0x00}, +- {WCD938X_RX_BIAS_BUCK_RST, 0x08}, +- {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44}, +- {WCD938X_RX_BIAS_FLYB_ERRAMP, 0x40}, +- {WCD938X_RX_BIAS_FLYB_BUFF, 0xAA}, +- {WCD938X_RX_BIAS_FLYB_MID_RST, 0x14}, +- {WCD938X_HPH_L_STATUS, 0x04}, +- {WCD938X_HPH_R_STATUS, 0x04}, +- {WCD938X_HPH_CNP_EN, 0x80}, +- {WCD938X_HPH_CNP_WG_CTL, 0x9A}, +- {WCD938X_HPH_CNP_WG_TIME, 0x14}, +- {WCD938X_HPH_OCP_CTL, 0x28}, +- {WCD938X_HPH_AUTO_CHOP, 0x16}, +- {WCD938X_HPH_CHOP_CTL, 0x83}, +- {WCD938X_HPH_PA_CTL1, 0x46}, +- {WCD938X_HPH_PA_CTL2, 0x50}, +- {WCD938X_HPH_L_EN, 0x80}, +- {WCD938X_HPH_L_TEST, 0xE0}, +- {WCD938X_HPH_L_ATEST, 0x50}, +- {WCD938X_HPH_R_EN, 0x80}, +- {WCD938X_HPH_R_TEST, 0xE0}, +- {WCD938X_HPH_R_ATEST, 0x54}, +- {WCD938X_HPH_RDAC_CLK_CTL1, 0x99}, +- {WCD938X_HPH_RDAC_CLK_CTL2, 0x9B}, +- {WCD938X_HPH_RDAC_LDO_CTL, 0x33}, +- {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00}, +- {WCD938X_HPH_REFBUFF_UHQA_CTL, 0x68}, +- {WCD938X_HPH_REFBUFF_LP_CTL, 0x0E}, +- {WCD938X_HPH_L_DAC_CTL, 0x20}, +- {WCD938X_HPH_R_DAC_CTL, 0x20}, +- {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55}, +- {WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0x19}, +- {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1, 0xA0}, +- {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00}, +- {WCD938X_EAR_EAR_EN_REG, 0x22}, +- {WCD938X_EAR_EAR_PA_CON, 0x44}, +- {WCD938X_EAR_EAR_SP_CON, 0xDB}, +- {WCD938X_EAR_EAR_DAC_CON, 0x80}, +- {WCD938X_EAR_EAR_CNP_FSM_CON, 0xB2}, +- {WCD938X_EAR_TEST_CTL, 0x00}, +- {WCD938X_EAR_STATUS_REG_1, 0x00}, +- {WCD938X_EAR_STATUS_REG_2, 0x08}, +- {WCD938X_ANA_NEW_PAGE_REGISTER, 0x00}, +- {WCD938X_HPH_NEW_ANA_HPH2, 0x00}, +- {WCD938X_HPH_NEW_ANA_HPH3, 0x00}, +- {WCD938X_SLEEP_CTL, 0x16}, +- {WCD938X_SLEEP_WATCHDOG_CTL, 0x00}, +- {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00}, +- {WCD938X_MBHC_NEW_CTL_1, 0x02}, +- {WCD938X_MBHC_NEW_CTL_2, 0x05}, +- {WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0xE9}, +- {WCD938X_MBHC_NEW_ZDET_ANA_CTL, 0x0F}, +- {WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 0x00}, +- {WCD938X_MBHC_NEW_FSM_STATUS, 0x00}, +- {WCD938X_MBHC_NEW_ADC_RESULT, 0x00}, +- {WCD938X_TX_NEW_AMIC_MUX_CFG, 0x00}, +- {WCD938X_AUX_AUXPA, 0x00}, +- {WCD938X_LDORXTX_MODE, 0x0C}, +- {WCD938X_LDORXTX_CONFIG, 0x10}, +- {WCD938X_DIE_CRACK_DIE_CRK_DET_EN, 0x00}, +- {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT, 0x00}, +- {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40}, +- {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81}, +- {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10}, +- {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00}, +- {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81}, +- {WCD938X_HPH_NEW_INT_PA_MISC1, 0x22}, +- {WCD938X_HPH_NEW_INT_PA_MISC2, 0x00}, +- {WCD938X_HPH_NEW_INT_PA_RDAC_MISC, 0x00}, +- {WCD938X_HPH_NEW_INT_HPH_TIMER1, 0xFE}, +- {WCD938X_HPH_NEW_INT_HPH_TIMER2, 0x02}, +- {WCD938X_HPH_NEW_INT_HPH_TIMER3, 0x4E}, +- {WCD938X_HPH_NEW_INT_HPH_TIMER4, 0x54}, +- {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00}, +- {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00}, +- {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 0x90}, +- {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 0x90}, +- {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62}, +- {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01}, +- {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11}, +- {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57}, +- {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01}, +- {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00}, +- {WCD938X_MBHC_NEW_INT_SPARE_2, 0x00}, +- {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON, 0xA8}, +- {WCD938X_EAR_INT_NEW_CNP_VCM_CON1, 0x42}, +- {WCD938X_EAR_INT_NEW_CNP_VCM_CON2, 0x22}, +- {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00}, +- {WCD938X_AUX_INT_EN_REG, 0x00}, +- {WCD938X_AUX_INT_PA_CTRL, 0x06}, +- {WCD938X_AUX_INT_SP_CTRL, 0xD2}, +- {WCD938X_AUX_INT_DAC_CTRL, 0x80}, +- {WCD938X_AUX_INT_CLK_CTRL, 0x50}, +- {WCD938X_AUX_INT_TEST_CTRL, 0x00}, +- {WCD938X_AUX_INT_STATUS_REG, 0x00}, +- {WCD938X_AUX_INT_MISC, 0x00}, +- {WCD938X_LDORXTX_INT_BIAS, 0x6E}, +- {WCD938X_LDORXTX_INT_STB_LOADS_DTEST, 0x50}, +- {WCD938X_LDORXTX_INT_TEST0, 0x1C}, +- {WCD938X_LDORXTX_INT_STARTUP_TIMER, 0xFF}, +- {WCD938X_LDORXTX_INT_TEST1, 0x1F}, +- {WCD938X_LDORXTX_INT_STATUS, 0x00}, +- {WCD938X_SLEEP_INT_WATCHDOG_CTL_1, 0x0A}, +- {WCD938X_SLEEP_INT_WATCHDOG_CTL_2, 0x0A}, +- {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02}, +- {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60}, +- {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xFF}, +- {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7F}, +- {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3F}, +- {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M, 0x1F}, +- {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M, 0x0F}, +- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1, 0xD7}, +- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0, 0xC8}, +- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP, 0xC6}, +- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1, 0xD5}, +- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0, 0xCA}, +- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 0x05}, +- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0, 0xA5}, +- {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 0x13}, +- {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88}, +- {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP, 0x42}, +- {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2, 0xFF}, +- {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1, 0x64}, +- {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0, 0x64}, +- {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP, 0x77}, +- {WCD938X_DIGITAL_PAGE_REGISTER, 0x00}, +- {WCD938X_DIGITAL_CHIP_ID0, 0x00}, +- {WCD938X_DIGITAL_CHIP_ID1, 0x00}, +- {WCD938X_DIGITAL_CHIP_ID2, 0x0D}, +- {WCD938X_DIGITAL_CHIP_ID3, 0x01}, +- {WCD938X_DIGITAL_SWR_TX_CLK_RATE, 0x00}, +- {WCD938X_DIGITAL_CDC_RST_CTL, 0x03}, +- {WCD938X_DIGITAL_TOP_CLK_CFG, 0x00}, +- {WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x00}, +- {WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0}, +- {WCD938X_DIGITAL_SWR_RST_EN, 0x00}, +- {WCD938X_DIGITAL_CDC_PATH_MODE, 0x55}, +- {WCD938X_DIGITAL_CDC_RX_RST, 0x00}, +- {WCD938X_DIGITAL_CDC_RX0_CTL, 0xFC}, +- {WCD938X_DIGITAL_CDC_RX1_CTL, 0xFC}, +- {WCD938X_DIGITAL_CDC_RX2_CTL, 0xFC}, +- {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x00}, +- {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x00}, +- {WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x00}, +- {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x1E}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0, 0x00}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1, 0x01}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0, 0x63}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1, 0x04}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0, 0xAC}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1, 0x04}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0, 0x1A}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1, 0x03}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0, 0xBC}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1, 0x02}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0, 0xC7}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0, 0xF8}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_C_0, 0x47}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_C_1, 0x43}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_C_2, 0xB1}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_C_3, 0x17}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_R1, 0x4D}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_R2, 0x29}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_R3, 0x34}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_R4, 0x59}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_R5, 0x66}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_R6, 0x87}, +- {WCD938X_DIGITAL_CDC_HPH_DSM_R7, 0x64}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0, 0x00}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1, 0x01}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0, 0x96}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1, 0x09}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0, 0xAB}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1, 0x05}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0, 0x1C}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1, 0x02}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0, 0x17}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1, 0x02}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0, 0xAA}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0, 0xE3}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_C_0, 0x69}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_C_1, 0x54}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_C_2, 0x02}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_C_3, 0x15}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_R1, 0xA4}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_R2, 0xB5}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_R3, 0x86}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_R4, 0x85}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_R5, 0xAA}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_R6, 0xE2}, +- {WCD938X_DIGITAL_CDC_AUX_DSM_R7, 0x62}, +- {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0, 0x55}, +- {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1, 0xA9}, +- {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0, 0x3D}, +- {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1, 0x2E}, +- {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2, 0x01}, +- {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0, 0x00}, +- {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1, 0xFC}, +- {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2, 0x01}, +- {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x00}, +- {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x00}, +- {WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0x00}, +- {WCD938X_DIGITAL_CDC_SWR_CLH, 0x00}, +- {WCD938X_DIGITAL_SWR_CLH_BYP, 0x00}, +- {WCD938X_DIGITAL_CDC_TX0_CTL, 0x68}, +- {WCD938X_DIGITAL_CDC_TX1_CTL, 0x68}, +- {WCD938X_DIGITAL_CDC_TX2_CTL, 0x68}, +- {WCD938X_DIGITAL_CDC_TX_RST, 0x00}, +- {WCD938X_DIGITAL_CDC_REQ_CTL, 0x01}, +- {WCD938X_DIGITAL_CDC_RST, 0x00}, +- {WCD938X_DIGITAL_CDC_AMIC_CTL, 0x0F}, +- {WCD938X_DIGITAL_CDC_DMIC_CTL, 0x04}, +- {WCD938X_DIGITAL_CDC_DMIC1_CTL, 0x01}, +- {WCD938X_DIGITAL_CDC_DMIC2_CTL, 0x01}, +- {WCD938X_DIGITAL_CDC_DMIC3_CTL, 0x01}, +- {WCD938X_DIGITAL_CDC_DMIC4_CTL, 0x01}, +- {WCD938X_DIGITAL_EFUSE_PRG_CTL, 0x00}, +- {WCD938X_DIGITAL_EFUSE_CTL, 0x2B}, +- {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2, 0x11}, +- {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4, 0x11}, +- {WCD938X_DIGITAL_PDM_WD_CTL0, 0x00}, +- {WCD938X_DIGITAL_PDM_WD_CTL1, 0x00}, +- {WCD938X_DIGITAL_PDM_WD_CTL2, 0x00}, +- {WCD938X_DIGITAL_INTR_MODE, 0x00}, +- {WCD938X_DIGITAL_INTR_MASK_0, 0xFF}, +- {WCD938X_DIGITAL_INTR_MASK_1, 0xFF}, +- {WCD938X_DIGITAL_INTR_MASK_2, 0x3F}, +- {WCD938X_DIGITAL_INTR_STATUS_0, 0x00}, +- {WCD938X_DIGITAL_INTR_STATUS_1, 0x00}, +- {WCD938X_DIGITAL_INTR_STATUS_2, 0x00}, +- {WCD938X_DIGITAL_INTR_CLEAR_0, 0x00}, +- {WCD938X_DIGITAL_INTR_CLEAR_1, 0x00}, +- {WCD938X_DIGITAL_INTR_CLEAR_2, 0x00}, +- {WCD938X_DIGITAL_INTR_LEVEL_0, 0x00}, +- {WCD938X_DIGITAL_INTR_LEVEL_1, 0x00}, +- {WCD938X_DIGITAL_INTR_LEVEL_2, 0x00}, +- {WCD938X_DIGITAL_INTR_SET_0, 0x00}, +- {WCD938X_DIGITAL_INTR_SET_1, 0x00}, +- {WCD938X_DIGITAL_INTR_SET_2, 0x00}, +- {WCD938X_DIGITAL_INTR_TEST_0, 0x00}, +- {WCD938X_DIGITAL_INTR_TEST_1, 0x00}, +- {WCD938X_DIGITAL_INTR_TEST_2, 0x00}, +- {WCD938X_DIGITAL_TX_MODE_DBG_EN, 0x00}, +- {WCD938X_DIGITAL_TX_MODE_DBG_0_1, 0x00}, +- {WCD938X_DIGITAL_TX_MODE_DBG_2_3, 0x00}, +- {WCD938X_DIGITAL_LB_IN_SEL_CTL, 0x00}, +- {WCD938X_DIGITAL_LOOP_BACK_MODE, 0x00}, +- {WCD938X_DIGITAL_SWR_DAC_TEST, 0x00}, +- {WCD938X_DIGITAL_SWR_HM_TEST_RX_0, 0x40}, +- {WCD938X_DIGITAL_SWR_HM_TEST_TX_0, 0x40}, +- {WCD938X_DIGITAL_SWR_HM_TEST_RX_1, 0x00}, +- {WCD938X_DIGITAL_SWR_HM_TEST_TX_1, 0x00}, +- {WCD938X_DIGITAL_SWR_HM_TEST_TX_2, 0x00}, +- {WCD938X_DIGITAL_SWR_HM_TEST_0, 0x00}, +- {WCD938X_DIGITAL_SWR_HM_TEST_1, 0x00}, +- {WCD938X_DIGITAL_PAD_CTL_SWR_0, 0x8F}, +- {WCD938X_DIGITAL_PAD_CTL_SWR_1, 0x06}, +- {WCD938X_DIGITAL_I2C_CTL, 0x00}, +- {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE, 0x00}, +- {WCD938X_DIGITAL_EFUSE_TEST_CTL_0, 0x00}, +- {WCD938X_DIGITAL_EFUSE_TEST_CTL_1, 0x00}, +- {WCD938X_DIGITAL_EFUSE_T_DATA_0, 0x00}, +- {WCD938X_DIGITAL_EFUSE_T_DATA_1, 0x00}, +- {WCD938X_DIGITAL_PAD_CTL_PDM_RX0, 0xF1}, +- {WCD938X_DIGITAL_PAD_CTL_PDM_RX1, 0xF1}, +- {WCD938X_DIGITAL_PAD_CTL_PDM_TX0, 0xF1}, +- {WCD938X_DIGITAL_PAD_CTL_PDM_TX1, 0xF1}, +- {WCD938X_DIGITAL_PAD_CTL_PDM_TX2, 0xF1}, +- {WCD938X_DIGITAL_PAD_INP_DIS_0, 0x00}, +- {WCD938X_DIGITAL_PAD_INP_DIS_1, 0x00}, +- {WCD938X_DIGITAL_DRIVE_STRENGTH_0, 0x00}, +- {WCD938X_DIGITAL_DRIVE_STRENGTH_1, 0x00}, +- {WCD938X_DIGITAL_DRIVE_STRENGTH_2, 0x00}, +- {WCD938X_DIGITAL_RX_DATA_EDGE_CTL, 0x1F}, +- {WCD938X_DIGITAL_TX_DATA_EDGE_CTL, 0x80}, +- {WCD938X_DIGITAL_GPIO_MODE, 0x00}, +- {WCD938X_DIGITAL_PIN_CTL_OE, 0x00}, +- {WCD938X_DIGITAL_PIN_CTL_DATA_0, 0x00}, +- {WCD938X_DIGITAL_PIN_CTL_DATA_1, 0x00}, +- {WCD938X_DIGITAL_PIN_STATUS_0, 0x00}, +- {WCD938X_DIGITAL_PIN_STATUS_1, 0x00}, +- {WCD938X_DIGITAL_DIG_DEBUG_CTL, 0x00}, +- {WCD938X_DIGITAL_DIG_DEBUG_EN, 0x00}, +- {WCD938X_DIGITAL_ANA_CSR_DBG_ADD, 0x00}, +- {WCD938X_DIGITAL_ANA_CSR_DBG_CTL, 0x48}, +- {WCD938X_DIGITAL_SSP_DBG, 0x00}, +- {WCD938X_DIGITAL_MODE_STATUS_0, 0x00}, +- {WCD938X_DIGITAL_MODE_STATUS_1, 0x00}, +- {WCD938X_DIGITAL_SPARE_0, 0x00}, +- {WCD938X_DIGITAL_SPARE_1, 0x00}, +- {WCD938X_DIGITAL_SPARE_2, 0x00}, +- {WCD938X_DIGITAL_EFUSE_REG_0, 0x00}, +- {WCD938X_DIGITAL_EFUSE_REG_1, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_2, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_3, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_4, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_5, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_6, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_7, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_8, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_9, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_10, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_11, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_12, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_13, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_14, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_15, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_16, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_17, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_18, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_19, 0xFF}, +- {WCD938X_DIGITAL_EFUSE_REG_20, 0x0E}, +- {WCD938X_DIGITAL_EFUSE_REG_21, 0x00}, +- {WCD938X_DIGITAL_EFUSE_REG_22, 0x00}, +- {WCD938X_DIGITAL_EFUSE_REG_23, 0xF8}, +- {WCD938X_DIGITAL_EFUSE_REG_24, 0x16}, +- {WCD938X_DIGITAL_EFUSE_REG_25, 0x00}, +- {WCD938X_DIGITAL_EFUSE_REG_26, 0x00}, +- {WCD938X_DIGITAL_EFUSE_REG_27, 0x00}, +- {WCD938X_DIGITAL_EFUSE_REG_28, 0x00}, +- {WCD938X_DIGITAL_EFUSE_REG_29, 0x00}, +- {WCD938X_DIGITAL_EFUSE_REG_30, 0x00}, +- {WCD938X_DIGITAL_EFUSE_REG_31, 0x00}, +- {WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0x88}, +- {WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0x88}, +- {WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0x88}, +- {WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0x88}, +- {WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0x88}, +- {WCD938X_DIGITAL_DEM_BYPASS_DATA0, 0x55}, +- {WCD938X_DIGITAL_DEM_BYPASS_DATA1, 0x55}, +- {WCD938X_DIGITAL_DEM_BYPASS_DATA2, 0x55}, +- {WCD938X_DIGITAL_DEM_BYPASS_DATA3, 0x01}, +-}; +- +-static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg) +-{ +- switch (reg) { +- case WCD938X_ANA_PAGE_REGISTER: +- case WCD938X_ANA_BIAS: +- case WCD938X_ANA_RX_SUPPLIES: +- case WCD938X_ANA_HPH: +- case WCD938X_ANA_EAR: +- case WCD938X_ANA_EAR_COMPANDER_CTL: +- case WCD938X_ANA_TX_CH1: +- case WCD938X_ANA_TX_CH2: +- case WCD938X_ANA_TX_CH3: +- case WCD938X_ANA_TX_CH4: +- case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC: +- case WCD938X_ANA_MICB3_DSP_EN_LOGIC: +- case WCD938X_ANA_MBHC_MECH: +- case WCD938X_ANA_MBHC_ELECT: +- case WCD938X_ANA_MBHC_ZDET: +- case WCD938X_ANA_MBHC_BTN0: +- case WCD938X_ANA_MBHC_BTN1: +- case WCD938X_ANA_MBHC_BTN2: +- case WCD938X_ANA_MBHC_BTN3: +- case WCD938X_ANA_MBHC_BTN4: +- case WCD938X_ANA_MBHC_BTN5: +- case WCD938X_ANA_MBHC_BTN6: +- case WCD938X_ANA_MBHC_BTN7: +- case WCD938X_ANA_MICB1: +- case WCD938X_ANA_MICB2: +- case WCD938X_ANA_MICB2_RAMP: +- case WCD938X_ANA_MICB3: +- case WCD938X_ANA_MICB4: +- case WCD938X_BIAS_CTL: +- case WCD938X_BIAS_VBG_FINE_ADJ: +- case WCD938X_LDOL_VDDCX_ADJUST: +- case WCD938X_LDOL_DISABLE_LDOL: +- case WCD938X_MBHC_CTL_CLK: +- case WCD938X_MBHC_CTL_ANA: +- case WCD938X_MBHC_CTL_SPARE_1: +- case WCD938X_MBHC_CTL_SPARE_2: +- case WCD938X_MBHC_CTL_BCS: +- case WCD938X_MBHC_TEST_CTL: +- case WCD938X_LDOH_MODE: +- case WCD938X_LDOH_BIAS: +- case WCD938X_LDOH_STB_LOADS: +- case WCD938X_LDOH_SLOWRAMP: +- case WCD938X_MICB1_TEST_CTL_1: +- case WCD938X_MICB1_TEST_CTL_2: +- case WCD938X_MICB1_TEST_CTL_3: +- case WCD938X_MICB2_TEST_CTL_1: +- case WCD938X_MICB2_TEST_CTL_2: +- case WCD938X_MICB2_TEST_CTL_3: +- case WCD938X_MICB3_TEST_CTL_1: +- case WCD938X_MICB3_TEST_CTL_2: +- case WCD938X_MICB3_TEST_CTL_3: +- case WCD938X_MICB4_TEST_CTL_1: +- case WCD938X_MICB4_TEST_CTL_2: +- case WCD938X_MICB4_TEST_CTL_3: +- case WCD938X_TX_COM_ADC_VCM: +- case WCD938X_TX_COM_BIAS_ATEST: +- case WCD938X_TX_COM_SPARE1: +- case WCD938X_TX_COM_SPARE2: +- case WCD938X_TX_COM_TXFE_DIV_CTL: +- case WCD938X_TX_COM_TXFE_DIV_START: +- case WCD938X_TX_COM_SPARE3: +- case WCD938X_TX_COM_SPARE4: +- case WCD938X_TX_1_2_TEST_EN: +- case WCD938X_TX_1_2_ADC_IB: +- case WCD938X_TX_1_2_ATEST_REFCTL: +- case WCD938X_TX_1_2_TEST_CTL: +- case WCD938X_TX_1_2_TEST_BLK_EN1: +- case WCD938X_TX_1_2_TXFE1_CLKDIV: +- case WCD938X_TX_3_4_TEST_EN: +- case WCD938X_TX_3_4_ADC_IB: +- case WCD938X_TX_3_4_ATEST_REFCTL: +- case WCD938X_TX_3_4_TEST_CTL: +- case WCD938X_TX_3_4_TEST_BLK_EN3: +- case WCD938X_TX_3_4_TXFE3_CLKDIV: +- case WCD938X_TX_3_4_TEST_BLK_EN2: +- case WCD938X_TX_3_4_TXFE2_CLKDIV: +- case WCD938X_TX_3_4_SPARE1: +- case WCD938X_TX_3_4_TEST_BLK_EN4: +- case WCD938X_TX_3_4_TXFE4_CLKDIV: +- case WCD938X_TX_3_4_SPARE2: +- case WCD938X_CLASSH_MODE_1: +- case WCD938X_CLASSH_MODE_2: +- case WCD938X_CLASSH_MODE_3: +- case WCD938X_CLASSH_CTRL_VCL_1: +- case WCD938X_CLASSH_CTRL_VCL_2: +- case WCD938X_CLASSH_CTRL_CCL_1: +- case WCD938X_CLASSH_CTRL_CCL_2: +- case WCD938X_CLASSH_CTRL_CCL_3: +- case WCD938X_CLASSH_CTRL_CCL_4: +- case WCD938X_CLASSH_CTRL_CCL_5: +- case WCD938X_CLASSH_BUCK_TMUX_A_D: +- case WCD938X_CLASSH_BUCK_SW_DRV_CNTL: +- case WCD938X_CLASSH_SPARE: +- case WCD938X_FLYBACK_EN: +- case WCD938X_FLYBACK_VNEG_CTRL_1: +- case WCD938X_FLYBACK_VNEG_CTRL_2: +- case WCD938X_FLYBACK_VNEG_CTRL_3: +- case WCD938X_FLYBACK_VNEG_CTRL_4: +- case WCD938X_FLYBACK_VNEG_CTRL_5: +- case WCD938X_FLYBACK_VNEG_CTRL_6: +- case WCD938X_FLYBACK_VNEG_CTRL_7: +- case WCD938X_FLYBACK_VNEG_CTRL_8: +- case WCD938X_FLYBACK_VNEG_CTRL_9: +- case WCD938X_FLYBACK_VNEGDAC_CTRL_1: +- case WCD938X_FLYBACK_VNEGDAC_CTRL_2: +- case WCD938X_FLYBACK_VNEGDAC_CTRL_3: +- case WCD938X_FLYBACK_CTRL_1: +- case WCD938X_FLYBACK_TEST_CTL: +- case WCD938X_RX_AUX_SW_CTL: +- case WCD938X_RX_PA_AUX_IN_CONN: +- case WCD938X_RX_TIMER_DIV: +- case WCD938X_RX_OCP_CTL: +- case WCD938X_RX_OCP_COUNT: +- case WCD938X_RX_BIAS_EAR_DAC: +- case WCD938X_RX_BIAS_EAR_AMP: +- case WCD938X_RX_BIAS_HPH_LDO: +- case WCD938X_RX_BIAS_HPH_PA: +- case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2: +- case WCD938X_RX_BIAS_HPH_RDAC_LDO: +- case WCD938X_RX_BIAS_HPH_CNP1: +- case WCD938X_RX_BIAS_HPH_LOWPOWER: +- case WCD938X_RX_BIAS_AUX_DAC: +- case WCD938X_RX_BIAS_AUX_AMP: +- case WCD938X_RX_BIAS_VNEGDAC_BLEEDER: +- case WCD938X_RX_BIAS_MISC: +- case WCD938X_RX_BIAS_BUCK_RST: +- case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP: +- case WCD938X_RX_BIAS_FLYB_ERRAMP: +- case WCD938X_RX_BIAS_FLYB_BUFF: +- case WCD938X_RX_BIAS_FLYB_MID_RST: +- case WCD938X_HPH_CNP_EN: +- case WCD938X_HPH_CNP_WG_CTL: +- case WCD938X_HPH_CNP_WG_TIME: +- case WCD938X_HPH_OCP_CTL: +- case WCD938X_HPH_AUTO_CHOP: +- case WCD938X_HPH_CHOP_CTL: +- case WCD938X_HPH_PA_CTL1: +- case WCD938X_HPH_PA_CTL2: +- case WCD938X_HPH_L_EN: +- case WCD938X_HPH_L_TEST: +- case WCD938X_HPH_L_ATEST: +- case WCD938X_HPH_R_EN: +- case WCD938X_HPH_R_TEST: +- case WCD938X_HPH_R_ATEST: +- case WCD938X_HPH_RDAC_CLK_CTL1: +- case WCD938X_HPH_RDAC_CLK_CTL2: +- case WCD938X_HPH_RDAC_LDO_CTL: +- case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL: +- case WCD938X_HPH_REFBUFF_UHQA_CTL: +- case WCD938X_HPH_REFBUFF_LP_CTL: +- case WCD938X_HPH_L_DAC_CTL: +- case WCD938X_HPH_R_DAC_CTL: +- case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL: +- case WCD938X_HPH_SURGE_HPHLR_SURGE_EN: +- case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1: +- case WCD938X_EAR_EAR_EN_REG: +- case WCD938X_EAR_EAR_PA_CON: +- case WCD938X_EAR_EAR_SP_CON: +- case WCD938X_EAR_EAR_DAC_CON: +- case WCD938X_EAR_EAR_CNP_FSM_CON: +- case WCD938X_EAR_TEST_CTL: +- case WCD938X_ANA_NEW_PAGE_REGISTER: +- case WCD938X_HPH_NEW_ANA_HPH2: +- case WCD938X_HPH_NEW_ANA_HPH3: +- case WCD938X_SLEEP_CTL: +- case WCD938X_SLEEP_WATCHDOG_CTL: +- case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL: +- case WCD938X_MBHC_NEW_CTL_1: +- case WCD938X_MBHC_NEW_CTL_2: +- case WCD938X_MBHC_NEW_PLUG_DETECT_CTL: +- case WCD938X_MBHC_NEW_ZDET_ANA_CTL: +- case WCD938X_MBHC_NEW_ZDET_RAMP_CTL: +- case WCD938X_TX_NEW_AMIC_MUX_CFG: +- case WCD938X_AUX_AUXPA: +- case WCD938X_LDORXTX_MODE: +- case WCD938X_LDORXTX_CONFIG: +- case WCD938X_DIE_CRACK_DIE_CRK_DET_EN: +- case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL: +- case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L: +- case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL: +- case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL: +- case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R: +- case WCD938X_HPH_NEW_INT_PA_MISC1: +- case WCD938X_HPH_NEW_INT_PA_MISC2: +- case WCD938X_HPH_NEW_INT_PA_RDAC_MISC: +- case WCD938X_HPH_NEW_INT_HPH_TIMER1: +- case WCD938X_HPH_NEW_INT_HPH_TIMER2: +- case WCD938X_HPH_NEW_INT_HPH_TIMER3: +- case WCD938X_HPH_NEW_INT_HPH_TIMER4: +- case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2: +- case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3: +- case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW: +- case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW: +- case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI: +- case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP: +- case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP: +- case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL: +- case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL: +- case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT: +- case WCD938X_MBHC_NEW_INT_SPARE_2: +- case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON: +- case WCD938X_EAR_INT_NEW_CNP_VCM_CON1: +- case WCD938X_EAR_INT_NEW_CNP_VCM_CON2: +- case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS: +- case WCD938X_AUX_INT_EN_REG: +- case WCD938X_AUX_INT_PA_CTRL: +- case WCD938X_AUX_INT_SP_CTRL: +- case WCD938X_AUX_INT_DAC_CTRL: +- case WCD938X_AUX_INT_CLK_CTRL: +- case WCD938X_AUX_INT_TEST_CTRL: +- case WCD938X_AUX_INT_MISC: +- case WCD938X_LDORXTX_INT_BIAS: +- case WCD938X_LDORXTX_INT_STB_LOADS_DTEST: +- case WCD938X_LDORXTX_INT_TEST0: +- case WCD938X_LDORXTX_INT_STARTUP_TIMER: +- case WCD938X_LDORXTX_INT_TEST1: +- case WCD938X_SLEEP_INT_WATCHDOG_CTL_1: +- case WCD938X_SLEEP_INT_WATCHDOG_CTL_2: +- case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1: +- case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2: +- case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2: +- case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1: +- case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0: +- case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M: +- case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M: +- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1: +- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0: +- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP: +- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1: +- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0: +- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP: +- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0: +- case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP: +- case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1: +- case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP: +- case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2: +- case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1: +- case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0: +- case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP: +- case WCD938X_DIGITAL_PAGE_REGISTER: +- case WCD938X_DIGITAL_SWR_TX_CLK_RATE: +- case WCD938X_DIGITAL_CDC_RST_CTL: +- case WCD938X_DIGITAL_TOP_CLK_CFG: +- case WCD938X_DIGITAL_CDC_ANA_CLK_CTL: +- case WCD938X_DIGITAL_CDC_DIG_CLK_CTL: +- case WCD938X_DIGITAL_SWR_RST_EN: +- case WCD938X_DIGITAL_CDC_PATH_MODE: +- case WCD938X_DIGITAL_CDC_RX_RST: +- case WCD938X_DIGITAL_CDC_RX0_CTL: +- case WCD938X_DIGITAL_CDC_RX1_CTL: +- case WCD938X_DIGITAL_CDC_RX2_CTL: +- case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1: +- case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3: +- case WCD938X_DIGITAL_CDC_COMP_CTL_0: +- case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL: +- case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0: +- case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1: +- case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0: +- case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1: +- case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0: +- case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1: +- case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0: +- case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1: +- case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0: +- case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1: +- case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0: +- case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0: +- case WCD938X_DIGITAL_CDC_HPH_DSM_C_0: +- case WCD938X_DIGITAL_CDC_HPH_DSM_C_1: +- case WCD938X_DIGITAL_CDC_HPH_DSM_C_2: +- case WCD938X_DIGITAL_CDC_HPH_DSM_C_3: +- case WCD938X_DIGITAL_CDC_HPH_DSM_R1: +- case WCD938X_DIGITAL_CDC_HPH_DSM_R2: +- case WCD938X_DIGITAL_CDC_HPH_DSM_R3: +- case WCD938X_DIGITAL_CDC_HPH_DSM_R4: +- case WCD938X_DIGITAL_CDC_HPH_DSM_R5: +- case WCD938X_DIGITAL_CDC_HPH_DSM_R6: +- case WCD938X_DIGITAL_CDC_HPH_DSM_R7: +- case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0: +- case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1: +- case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0: +- case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1: +- case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0: +- case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1: +- case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0: +- case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1: +- case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0: +- case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1: +- case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0: +- case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0: +- case WCD938X_DIGITAL_CDC_AUX_DSM_C_0: +- case WCD938X_DIGITAL_CDC_AUX_DSM_C_1: +- case WCD938X_DIGITAL_CDC_AUX_DSM_C_2: +- case WCD938X_DIGITAL_CDC_AUX_DSM_C_3: +- case WCD938X_DIGITAL_CDC_AUX_DSM_R1: +- case WCD938X_DIGITAL_CDC_AUX_DSM_R2: +- case WCD938X_DIGITAL_CDC_AUX_DSM_R3: +- case WCD938X_DIGITAL_CDC_AUX_DSM_R4: +- case WCD938X_DIGITAL_CDC_AUX_DSM_R5: +- case WCD938X_DIGITAL_CDC_AUX_DSM_R6: +- case WCD938X_DIGITAL_CDC_AUX_DSM_R7: +- case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0: +- case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1: +- case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0: +- case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1: +- case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2: +- case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0: +- case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1: +- case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2: +- case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL: +- case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL: +- case WCD938X_DIGITAL_CDC_EAR_PATH_CTL: +- case WCD938X_DIGITAL_CDC_SWR_CLH: +- case WCD938X_DIGITAL_SWR_CLH_BYP: +- case WCD938X_DIGITAL_CDC_TX0_CTL: +- case WCD938X_DIGITAL_CDC_TX1_CTL: +- case WCD938X_DIGITAL_CDC_TX2_CTL: +- case WCD938X_DIGITAL_CDC_TX_RST: +- case WCD938X_DIGITAL_CDC_REQ_CTL: +- case WCD938X_DIGITAL_CDC_RST: +- case WCD938X_DIGITAL_CDC_AMIC_CTL: +- case WCD938X_DIGITAL_CDC_DMIC_CTL: +- case WCD938X_DIGITAL_CDC_DMIC1_CTL: +- case WCD938X_DIGITAL_CDC_DMIC2_CTL: +- case WCD938X_DIGITAL_CDC_DMIC3_CTL: +- case WCD938X_DIGITAL_CDC_DMIC4_CTL: +- case WCD938X_DIGITAL_EFUSE_PRG_CTL: +- case WCD938X_DIGITAL_EFUSE_CTL: +- case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2: +- case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4: +- case WCD938X_DIGITAL_PDM_WD_CTL0: +- case WCD938X_DIGITAL_PDM_WD_CTL1: +- case WCD938X_DIGITAL_PDM_WD_CTL2: +- case WCD938X_DIGITAL_INTR_MODE: +- case WCD938X_DIGITAL_INTR_MASK_0: +- case WCD938X_DIGITAL_INTR_MASK_1: +- case WCD938X_DIGITAL_INTR_MASK_2: +- case WCD938X_DIGITAL_INTR_CLEAR_0: +- case WCD938X_DIGITAL_INTR_CLEAR_1: +- case WCD938X_DIGITAL_INTR_CLEAR_2: +- case WCD938X_DIGITAL_INTR_LEVEL_0: +- case WCD938X_DIGITAL_INTR_LEVEL_1: +- case WCD938X_DIGITAL_INTR_LEVEL_2: +- case WCD938X_DIGITAL_INTR_SET_0: +- case WCD938X_DIGITAL_INTR_SET_1: +- case WCD938X_DIGITAL_INTR_SET_2: +- case WCD938X_DIGITAL_INTR_TEST_0: +- case WCD938X_DIGITAL_INTR_TEST_1: +- case WCD938X_DIGITAL_INTR_TEST_2: +- case WCD938X_DIGITAL_TX_MODE_DBG_EN: +- case WCD938X_DIGITAL_TX_MODE_DBG_0_1: +- case WCD938X_DIGITAL_TX_MODE_DBG_2_3: +- case WCD938X_DIGITAL_LB_IN_SEL_CTL: +- case WCD938X_DIGITAL_LOOP_BACK_MODE: +- case WCD938X_DIGITAL_SWR_DAC_TEST: +- case WCD938X_DIGITAL_SWR_HM_TEST_RX_0: +- case WCD938X_DIGITAL_SWR_HM_TEST_TX_0: +- case WCD938X_DIGITAL_SWR_HM_TEST_RX_1: +- case WCD938X_DIGITAL_SWR_HM_TEST_TX_1: +- case WCD938X_DIGITAL_SWR_HM_TEST_TX_2: +- case WCD938X_DIGITAL_PAD_CTL_SWR_0: +- case WCD938X_DIGITAL_PAD_CTL_SWR_1: +- case WCD938X_DIGITAL_I2C_CTL: +- case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE: +- case WCD938X_DIGITAL_EFUSE_TEST_CTL_0: +- case WCD938X_DIGITAL_EFUSE_TEST_CTL_1: +- case WCD938X_DIGITAL_PAD_CTL_PDM_RX0: +- case WCD938X_DIGITAL_PAD_CTL_PDM_RX1: +- case WCD938X_DIGITAL_PAD_CTL_PDM_TX0: +- case WCD938X_DIGITAL_PAD_CTL_PDM_TX1: +- case WCD938X_DIGITAL_PAD_CTL_PDM_TX2: +- case WCD938X_DIGITAL_PAD_INP_DIS_0: +- case WCD938X_DIGITAL_PAD_INP_DIS_1: +- case WCD938X_DIGITAL_DRIVE_STRENGTH_0: +- case WCD938X_DIGITAL_DRIVE_STRENGTH_1: +- case WCD938X_DIGITAL_DRIVE_STRENGTH_2: +- case WCD938X_DIGITAL_RX_DATA_EDGE_CTL: +- case WCD938X_DIGITAL_TX_DATA_EDGE_CTL: +- case WCD938X_DIGITAL_GPIO_MODE: +- case WCD938X_DIGITAL_PIN_CTL_OE: +- case WCD938X_DIGITAL_PIN_CTL_DATA_0: +- case WCD938X_DIGITAL_PIN_CTL_DATA_1: +- case WCD938X_DIGITAL_DIG_DEBUG_CTL: +- case WCD938X_DIGITAL_DIG_DEBUG_EN: +- case WCD938X_DIGITAL_ANA_CSR_DBG_ADD: +- case WCD938X_DIGITAL_ANA_CSR_DBG_CTL: +- case WCD938X_DIGITAL_SSP_DBG: +- case WCD938X_DIGITAL_SPARE_0: +- case WCD938X_DIGITAL_SPARE_1: +- case WCD938X_DIGITAL_SPARE_2: +- case WCD938X_DIGITAL_TX_REQ_FB_CTL_0: +- case WCD938X_DIGITAL_TX_REQ_FB_CTL_1: +- case WCD938X_DIGITAL_TX_REQ_FB_CTL_2: +- case WCD938X_DIGITAL_TX_REQ_FB_CTL_3: +- case WCD938X_DIGITAL_TX_REQ_FB_CTL_4: +- case WCD938X_DIGITAL_DEM_BYPASS_DATA0: +- case WCD938X_DIGITAL_DEM_BYPASS_DATA1: +- case WCD938X_DIGITAL_DEM_BYPASS_DATA2: +- case WCD938X_DIGITAL_DEM_BYPASS_DATA3: +- return true; +- } +- +- return false; +-} +- +-static bool wcd938x_readonly_register(struct device *dev, unsigned int reg) +-{ +- switch (reg) { +- case WCD938X_ANA_MBHC_RESULT_1: +- case WCD938X_ANA_MBHC_RESULT_2: +- case WCD938X_ANA_MBHC_RESULT_3: +- case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS: +- case WCD938X_TX_1_2_SAR2_ERR: +- case WCD938X_TX_1_2_SAR1_ERR: +- case WCD938X_TX_3_4_SAR4_ERR: +- case WCD938X_TX_3_4_SAR3_ERR: +- case WCD938X_HPH_L_STATUS: +- case WCD938X_HPH_R_STATUS: +- case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS: +- case WCD938X_EAR_STATUS_REG_1: +- case WCD938X_EAR_STATUS_REG_2: +- case WCD938X_MBHC_NEW_FSM_STATUS: +- case WCD938X_MBHC_NEW_ADC_RESULT: +- case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT: +- case WCD938X_AUX_INT_STATUS_REG: +- case WCD938X_LDORXTX_INT_STATUS: +- case WCD938X_DIGITAL_CHIP_ID0: +- case WCD938X_DIGITAL_CHIP_ID1: +- case WCD938X_DIGITAL_CHIP_ID2: +- case WCD938X_DIGITAL_CHIP_ID3: +- case WCD938X_DIGITAL_INTR_STATUS_0: +- case WCD938X_DIGITAL_INTR_STATUS_1: +- case WCD938X_DIGITAL_INTR_STATUS_2: +- case WCD938X_DIGITAL_INTR_CLEAR_0: +- case WCD938X_DIGITAL_INTR_CLEAR_1: +- case WCD938X_DIGITAL_INTR_CLEAR_2: +- case WCD938X_DIGITAL_SWR_HM_TEST_0: +- case WCD938X_DIGITAL_SWR_HM_TEST_1: +- case WCD938X_DIGITAL_EFUSE_T_DATA_0: +- case WCD938X_DIGITAL_EFUSE_T_DATA_1: +- case WCD938X_DIGITAL_PIN_STATUS_0: +- case WCD938X_DIGITAL_PIN_STATUS_1: +- case WCD938X_DIGITAL_MODE_STATUS_0: +- case WCD938X_DIGITAL_MODE_STATUS_1: +- case WCD938X_DIGITAL_EFUSE_REG_0: +- case WCD938X_DIGITAL_EFUSE_REG_1: +- case WCD938X_DIGITAL_EFUSE_REG_2: +- case WCD938X_DIGITAL_EFUSE_REG_3: +- case WCD938X_DIGITAL_EFUSE_REG_4: +- case WCD938X_DIGITAL_EFUSE_REG_5: +- case WCD938X_DIGITAL_EFUSE_REG_6: +- case WCD938X_DIGITAL_EFUSE_REG_7: +- case WCD938X_DIGITAL_EFUSE_REG_8: +- case WCD938X_DIGITAL_EFUSE_REG_9: +- case WCD938X_DIGITAL_EFUSE_REG_10: +- case WCD938X_DIGITAL_EFUSE_REG_11: +- case WCD938X_DIGITAL_EFUSE_REG_12: +- case WCD938X_DIGITAL_EFUSE_REG_13: +- case WCD938X_DIGITAL_EFUSE_REG_14: +- case WCD938X_DIGITAL_EFUSE_REG_15: +- case WCD938X_DIGITAL_EFUSE_REG_16: +- case WCD938X_DIGITAL_EFUSE_REG_17: +- case WCD938X_DIGITAL_EFUSE_REG_18: +- case WCD938X_DIGITAL_EFUSE_REG_19: +- case WCD938X_DIGITAL_EFUSE_REG_20: +- case WCD938X_DIGITAL_EFUSE_REG_21: +- case WCD938X_DIGITAL_EFUSE_REG_22: +- case WCD938X_DIGITAL_EFUSE_REG_23: +- case WCD938X_DIGITAL_EFUSE_REG_24: +- case WCD938X_DIGITAL_EFUSE_REG_25: +- case WCD938X_DIGITAL_EFUSE_REG_26: +- case WCD938X_DIGITAL_EFUSE_REG_27: +- case WCD938X_DIGITAL_EFUSE_REG_28: +- case WCD938X_DIGITAL_EFUSE_REG_29: +- case WCD938X_DIGITAL_EFUSE_REG_30: +- case WCD938X_DIGITAL_EFUSE_REG_31: +- return true; +- } +- return false; +-} +- +-static bool wcd938x_readable_register(struct device *dev, unsigned int reg) +-{ +- bool ret; +- +- ret = wcd938x_readonly_register(dev, reg); +- if (!ret) +- return wcd938x_rdwr_register(dev, reg); +- +- return ret; +-} +- +-static bool wcd938x_writeable_register(struct device *dev, unsigned int reg) +-{ +- return wcd938x_rdwr_register(dev, reg); +-} +- +-static bool wcd938x_volatile_register(struct device *dev, unsigned int reg) +-{ +- if (reg <= WCD938X_BASE_ADDRESS) +- return false; +- +- if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE) +- return true; +- +- if (wcd938x_readonly_register(dev, reg)) +- return true; +- +- return false; +-} +- +-static struct regmap_config wcd938x_regmap_config = { +- .name = "wcd938x_csr", +- .reg_bits = 32, +- .val_bits = 8, +- .cache_type = REGCACHE_RBTREE, +- .reg_defaults = wcd938x_defaults, +- .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults), +- .max_register = WCD938X_MAX_REGISTER, +- .readable_reg = wcd938x_readable_register, +- .writeable_reg = wcd938x_writeable_register, +- .volatile_reg = wcd938x_volatile_register, +- .can_multi_write = true, +-}; +- + static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = { + REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01), + REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02), +@@ -4412,10 +3417,10 @@ static int wcd938x_bind(struct device *d + return -EINVAL; + } + +- wcd938x->regmap = devm_regmap_init_sdw(wcd938x->tx_sdw_dev, &wcd938x_regmap_config); +- if (IS_ERR(wcd938x->regmap)) { +- dev_err(dev, "%s: tx csr regmap not found\n", __func__); +- return PTR_ERR(wcd938x->regmap); ++ wcd938x->regmap = dev_get_regmap(&wcd938x->tx_sdw_dev->dev, NULL); ++ if (!wcd938x->regmap) { ++ dev_err(dev, "could not get TX device regmap\n"); ++ return -EINVAL; + } + + ret = wcd938x_irq_init(wcd938x, dev); +--- a/sound/soc/codecs/wcd938x.h ++++ b/sound/soc/codecs/wcd938x.h +@@ -663,6 +663,7 @@ struct wcd938x_sdw_priv { + bool is_tx; + struct wcd938x_priv *wcd938x; + struct irq_domain *slave_irq; ++ struct regmap *regmap; + }; + + #if IS_ENABLED(CONFIG_SND_SOC_WCD938X_SDW) diff --git a/queue-6.3/drbd-correctly-submit-flush-bio-on-barrier.patch b/queue-6.3/drbd-correctly-submit-flush-bio-on-barrier.patch new file mode 100644 index 00000000000..26cd40bdb0a --- /dev/null +++ b/queue-6.3/drbd-correctly-submit-flush-bio-on-barrier.patch @@ -0,0 +1,49 @@ +From 3899d94e3831ee07ea6821c032dc297aec80586a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christoph=20B=C3=B6hmwalder?= + +Date: Wed, 3 May 2023 14:19:37 +0200 +Subject: drbd: correctly submit flush bio on barrier +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christoph Böhmwalder + +commit 3899d94e3831ee07ea6821c032dc297aec80586a upstream. + +When we receive a flush command (or "barrier" in DRBD), we currently use +a REQ_OP_FLUSH with the REQ_PREFLUSH flag set. + +The correct way to submit a flush bio is by using a REQ_OP_WRITE without +any data, and set the REQ_PREFLUSH flag. + +Since commit b4a6bb3a67aa ("block: add a sanity check for non-write +flush/fua bios"), this triggers a warning in the block layer, but this +has been broken for quite some time before that. + +So use the correct set of flags to actually make the flush happen. + +Cc: Christoph Hellwig +Cc: stable@vger.kernel.org +Fixes: f9ff0da56437 ("drbd: allow parallel flushes for multi-volume resources") +Reported-by: Thomas Voegtle +Signed-off-by: Christoph Böhmwalder +Reviewed-by: Christoph Hellwig +Link: https://lore.kernel.org/r/20230503121937.17232-1-christoph.boehmwalder@linbit.com +Signed-off-by: Jens Axboe +Signed-off-by: Greg Kroah-Hartman +--- + drivers/block/drbd/drbd_receiver.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/block/drbd/drbd_receiver.c ++++ b/drivers/block/drbd/drbd_receiver.c +@@ -1283,7 +1283,7 @@ static void one_flush_endio(struct bio * + static void submit_one_flush(struct drbd_device *device, struct issue_flush_context *ctx) + { + struct bio *bio = bio_alloc(device->ldev->backing_bdev, 0, +- REQ_OP_FLUSH | REQ_PREFLUSH, GFP_NOIO); ++ REQ_OP_WRITE | REQ_PREFLUSH, GFP_NOIO); + struct one_flush_context *octx = kmalloc(sizeof(*octx), GFP_NOIO); + + if (!octx) { diff --git a/queue-6.3/mm-do-not-reclaim-private-data-from-pinned-page.patch b/queue-6.3/mm-do-not-reclaim-private-data-from-pinned-page.patch new file mode 100644 index 00000000000..006d687b8a5 --- /dev/null +++ b/queue-6.3/mm-do-not-reclaim-private-data-from-pinned-page.patch @@ -0,0 +1,50 @@ +From d824ec2a154677f63c56cc71ffe4578274f6e32e Mon Sep 17 00:00:00 2001 +From: Jan Kara +Date: Fri, 28 Apr 2023 14:41:40 +0200 +Subject: mm: do not reclaim private data from pinned page + +From: Jan Kara + +commit d824ec2a154677f63c56cc71ffe4578274f6e32e upstream. + +If the page is pinned, there's no point in trying to reclaim it. +Furthermore if the page is from the page cache we don't want to reclaim +fs-private data from the page because the pinning process may be writing +to the page at any time and reclaiming fs private info on a dirty page can +upset the filesystem (see link below). + +Link: https://lore.kernel.org/linux-mm/20180103100430.GE4911@quack2.suse.cz +Link: https://lkml.kernel.org/r/20230428124140.30166-1-jack@suse.cz +Signed-off-by: Jan Kara +Reviewed-by: Matthew Wilcox (Oracle) +Reviewed-by: Lorenzo Stoakes +Reviewed-by: Christoph Hellwig +Reviewed-by: John Hubbard +Acked-by: David Hildenbrand +Acked-by: Peter Xu +Cc: +Signed-off-by: Andrew Morton +Signed-off-by: Greg Kroah-Hartman +--- + mm/vmscan.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/mm/vmscan.c ++++ b/mm/vmscan.c +@@ -1911,6 +1911,16 @@ retry: + } + } + ++ /* ++ * Folio is unmapped now so it cannot be newly pinned anymore. ++ * No point in trying to reclaim folio if it is pinned. ++ * Furthermore we don't want to reclaim underlying fs metadata ++ * if the folio is pinned and thus potentially modified by the ++ * pinning process as that may upset the filesystem. ++ */ ++ if (folio_maybe_dma_pinned(folio)) ++ goto activate_locked; ++ + mapping = folio_mapping(folio); + if (folio_test_dirty(folio)) { + /* diff --git a/queue-6.3/nilfs2-do-not-write-dirty-data-after-degenerating-to-read-only.patch b/queue-6.3/nilfs2-do-not-write-dirty-data-after-degenerating-to-read-only.patch new file mode 100644 index 00000000000..1fa903bb11e --- /dev/null +++ b/queue-6.3/nilfs2-do-not-write-dirty-data-after-degenerating-to-read-only.patch @@ -0,0 +1,61 @@ +From 28a65b49eb53e172d23567005465019658bfdb4d Mon Sep 17 00:00:00 2001 +From: Ryusuke Konishi +Date: Thu, 27 Apr 2023 10:15:26 +0900 +Subject: nilfs2: do not write dirty data after degenerating to read-only + +From: Ryusuke Konishi + +commit 28a65b49eb53e172d23567005465019658bfdb4d upstream. + +According to syzbot's report, mark_buffer_dirty() called from +nilfs_segctor_do_construct() outputs a warning with some patterns after +nilfs2 detects metadata corruption and degrades to read-only mode. + +After such read-only degeneration, page cache data may be cleared through +nilfs_clear_dirty_page() which may also clear the uptodate flag for their +buffer heads. However, even after the degeneration, log writes are still +performed by unmount processing etc., which causes mark_buffer_dirty() to +be called for buffer heads without the "uptodate" flag and causes the +warning. + +Since any writes should not be done to a read-only file system in the +first place, this fixes the warning in mark_buffer_dirty() by letting +nilfs_segctor_do_construct() abort early if in read-only mode. + +This also changes the retry check of nilfs_segctor_write_out() to avoid +unnecessary log write retries if it detects -EROFS that +nilfs_segctor_do_construct() returned. + +Link: https://lkml.kernel.org/r/20230427011526.13457-1-konishi.ryusuke@gmail.com +Signed-off-by: Ryusuke Konishi +Tested-by: Ryusuke Konishi +Reported-by: syzbot+2af3bc9585be7f23f290@syzkaller.appspotmail.com + Link: https://syzkaller.appspot.com/bug?extid=2af3bc9585be7f23f290 +Cc: +Signed-off-by: Andrew Morton +Signed-off-by: Greg Kroah-Hartman +--- + fs/nilfs2/segment.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/fs/nilfs2/segment.c ++++ b/fs/nilfs2/segment.c +@@ -2041,6 +2041,9 @@ static int nilfs_segctor_do_construct(st + struct the_nilfs *nilfs = sci->sc_super->s_fs_info; + int err; + ++ if (sb_rdonly(sci->sc_super)) ++ return -EROFS; ++ + nilfs_sc_cstage_set(sci, NILFS_ST_INIT); + sci->sc_cno = nilfs->ns_cno; + +@@ -2724,7 +2727,7 @@ static void nilfs_segctor_write_out(stru + + flush_work(&sci->sc_iput_work); + +- } while (ret && retrycount-- > 0); ++ } while (ret && ret != -EROFS && retrycount-- > 0); + } + + /** diff --git a/queue-6.3/nilfs2-fix-infinite-loop-in-nilfs_mdt_get_block.patch b/queue-6.3/nilfs2-fix-infinite-loop-in-nilfs_mdt_get_block.patch new file mode 100644 index 00000000000..48efad238d7 --- /dev/null +++ b/queue-6.3/nilfs2-fix-infinite-loop-in-nilfs_mdt_get_block.patch @@ -0,0 +1,71 @@ +From a6a491c048882e7e424d407d32cba0b52d9ef2bf Mon Sep 17 00:00:00 2001 +From: Ryusuke Konishi +Date: Mon, 1 May 2023 04:30:46 +0900 +Subject: nilfs2: fix infinite loop in nilfs_mdt_get_block() + +From: Ryusuke Konishi + +commit a6a491c048882e7e424d407d32cba0b52d9ef2bf upstream. + +If the disk image that nilfs2 mounts is corrupted and a virtual block +address obtained by block lookup for a metadata file is invalid, +nilfs_bmap_lookup_at_level() may return the same internal return code as +-ENOENT, meaning the block does not exist in the metadata file. + +This duplication of return codes confuses nilfs_mdt_get_block(), causing +it to read and create a metadata block indefinitely. + +In particular, if this happens to the inode metadata file, ifile, +semaphore i_rwsem can be left held, causing task hangs in lock_mount. + +Fix this issue by making nilfs_bmap_lookup_at_level() treat virtual block +address translation failures with -ENOENT as metadata corruption instead +of returning the error code. + +Link: https://lkml.kernel.org/r/20230430193046.6769-1-konishi.ryusuke@gmail.com +Signed-off-by: Ryusuke Konishi +Tested-by: Ryusuke Konishi +Reported-by: syzbot+221d75710bde87fa0e97@syzkaller.appspotmail.com + Link: https://syzkaller.appspot.com/bug?extid=221d75710bde87fa0e97 +Cc: +Signed-off-by: Andrew Morton +Signed-off-by: Greg Kroah-Hartman +--- + fs/nilfs2/bmap.c | 16 ++++++++++++---- + 1 file changed, 12 insertions(+), 4 deletions(-) + +--- a/fs/nilfs2/bmap.c ++++ b/fs/nilfs2/bmap.c +@@ -67,20 +67,28 @@ int nilfs_bmap_lookup_at_level(struct ni + + down_read(&bmap->b_sem); + ret = bmap->b_ops->bop_lookup(bmap, key, level, ptrp); +- if (ret < 0) { +- ret = nilfs_bmap_convert_error(bmap, __func__, ret); ++ if (ret < 0) + goto out; +- } ++ + if (NILFS_BMAP_USE_VBN(bmap)) { + ret = nilfs_dat_translate(nilfs_bmap_get_dat(bmap), *ptrp, + &blocknr); + if (!ret) + *ptrp = blocknr; ++ else if (ret == -ENOENT) { ++ /* ++ * If there was no valid entry in DAT for the block ++ * address obtained by b_ops->bop_lookup, then pass ++ * internal code -EINVAL to nilfs_bmap_convert_error ++ * to treat it as metadata corruption. ++ */ ++ ret = -EINVAL; ++ } + } + + out: + up_read(&bmap->b_sem); +- return ret; ++ return nilfs_bmap_convert_error(bmap, __func__, ret); + } + + int nilfs_bmap_lookup_contig(struct nilfs_bmap *bmap, __u64 key, __u64 *ptrp, diff --git a/queue-6.3/parisc-ensure-page-alignment-in-flush-functions.patch b/queue-6.3/parisc-ensure-page-alignment-in-flush-functions.patch new file mode 100644 index 00000000000..2c7b1883da2 --- /dev/null +++ b/queue-6.3/parisc-ensure-page-alignment-in-flush-functions.patch @@ -0,0 +1,43 @@ +From d755bd2caeb47fd806e12399fe8b56798fa5d2cc Mon Sep 17 00:00:00 2001 +From: Helge Deller +Date: Wed, 15 Mar 2023 19:25:15 +0100 +Subject: parisc: Ensure page alignment in flush functions + +From: Helge Deller + +commit d755bd2caeb47fd806e12399fe8b56798fa5d2cc upstream. + +Matthew Wilcox noticed, that if ARCH_HAS_FLUSH_ON_KUNMAP is defined +(which is the case for PA-RISC), __kunmap_local() calls +kunmap_flush_on_unmap(), which may call the parisc flush functions with +a non-page-aligned address and thus the page might not be fully flushed. + +This patch ensures that flush_kernel_dcache_page_asm() and +flush_kernel_dcache_page_asm() will always operate on page-aligned +addresses. + +Signed-off-by: Helge Deller +Cc: # v6.0+ +Signed-off-by: Greg Kroah-Hartman +--- + arch/parisc/kernel/pacache.S | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/parisc/kernel/pacache.S ++++ b/arch/parisc/kernel/pacache.S +@@ -889,6 +889,7 @@ ENDPROC_CFI(flush_icache_page_asm) + ENTRY_CFI(flush_kernel_dcache_page_asm) + 88: ldil L%dcache_stride, %r1 + ldw R%dcache_stride(%r1), %r23 ++ depi_safe 0, 31,PAGE_SHIFT, %r26 /* Clear any offset bits */ + + #ifdef CONFIG_64BIT + depdi,z 1, 63-PAGE_SHIFT,1, %r25 +@@ -925,6 +926,7 @@ ENDPROC_CFI(flush_kernel_dcache_page_asm + ENTRY_CFI(purge_kernel_dcache_page_asm) + 88: ldil L%dcache_stride, %r1 + ldw R%dcache_stride(%r1), %r23 ++ depi_safe 0, 31,PAGE_SHIFT, %r26 /* Clear any offset bits */ + + #ifdef CONFIG_64BIT + depdi,z 1, 63-PAGE_SHIFT,1, %r25 diff --git a/queue-6.3/parisc-fix-argument-pointer-in-real64_call_asm.patch b/queue-6.3/parisc-fix-argument-pointer-in-real64_call_asm.patch new file mode 100644 index 00000000000..4212e91806f --- /dev/null +++ b/queue-6.3/parisc-fix-argument-pointer-in-real64_call_asm.patch @@ -0,0 +1,48 @@ +From 6e3220ba3323a2c24be834aebf5d6e9f89d0993f Mon Sep 17 00:00:00 2001 +From: Helge Deller +Date: Wed, 3 May 2023 16:39:56 +0200 +Subject: parisc: Fix argument pointer in real64_call_asm() + +From: Helge Deller + +commit 6e3220ba3323a2c24be834aebf5d6e9f89d0993f upstream. + +Fix the argument pointer (ap) to point to real-mode memory +instead of virtual memory. + +It's interesting that this issue hasn't shown up earlier, as this could +have happened with any 64-bit PDC ROM code. + +I just noticed it because I suddenly faced a HPMC while trying to execute +the 64-bit STI ROM code of an Visualize-FXe graphics card for the STI +text console. + +Signed-off-by: Helge Deller +Cc: +Signed-off-by: Greg Kroah-Hartman +--- + arch/parisc/kernel/real2.S | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +--- a/arch/parisc/kernel/real2.S ++++ b/arch/parisc/kernel/real2.S +@@ -235,9 +235,6 @@ ENTRY_CFI(real64_call_asm) + /* save fn */ + copy %arg2, %r31 + +- /* set up the new ap */ +- ldo 64(%arg1), %r29 +- + /* load up the arg registers from the saved arg area */ + /* 32-bit calling convention passes first 4 args in registers */ + ldd 0*REG_SZ(%arg1), %arg0 /* note overwriting arg0 */ +@@ -249,7 +246,9 @@ ENTRY_CFI(real64_call_asm) + ldd 7*REG_SZ(%arg1), %r19 + ldd 1*REG_SZ(%arg1), %arg1 /* do this one last! */ + ++ /* set up real-mode stack and real-mode ap */ + tophys_r1 %sp ++ ldo -16(%sp), %r29 /* Reference param save area */ + + b,l rfi_virt2real,%r2 + nop diff --git a/queue-6.3/series b/queue-6.3/series index 95d207b75ef..aef5a1d2709 100644 --- a/queue-6.3/series +++ b/queue-6.3/series @@ -97,6 +97,18 @@ bus-mhi-host-remove-duplicate-ee-check-for-syserr.patch bus-mhi-host-use-mhi_tryset_pm_state-for-setting-fw-error-state.patch bus-mhi-host-range-check-chdboff-and-erdboff.patch asoc-dt-bindings-qcom-lpass-rx-macro-correct-minitems-for-clocks.patch +parisc-fix-argument-pointer-in-real64_call_asm.patch +parisc-ensure-page-alignment-in-flush-functions.patch +alsa-usb-audio-add-quirk-for-pioneer-ddj-800.patch +alsa-hda-realtek-add-quirk-for-thinkpad-p1-gen-6.patch +alsa-hda-realtek-add-quirk-for-asus-um3402yar-using-cs35l41.patch +alsa-hda-realtek-support-hp-pavilion-aero-13-be0xxx-mute-led.patch +alsa-hda-realtek-fix-mute-and-micmute-leds-for-an-hp-laptop.patch +asoc-codecs-wcd938x-fix-accessing-regmap-on-unattached-devices.patch +nilfs2-do-not-write-dirty-data-after-degenerating-to-read-only.patch +nilfs2-fix-infinite-loop-in-nilfs_mdt_get_block.patch +mm-do-not-reclaim-private-data-from-pinned-page.patch +drbd-correctly-submit-flush-bio-on-barrier.patch kunit-fix-bug-in-the-order-of-lines-in-debugfs-logs.patch rcu-fix-missing-tick_dep_mask_rcu_exp-dependency-che.patch selftests-resctrl-return-null-if-malloc_and_init_mem.patch