From: Ivan Vecera Date: Sun, 3 May 2026 16:42:00 +0000 (+0200) Subject: dpll: fix man page correctness issues X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=0bbe88abb731618db7bddd9db462d09b21de4c3b;p=thirdparty%2Fiproute2.git dpll: fix man page correctness issues Fix several inaccuracies in dpll.8 man page: - Remove bogus "holdover" and "freerun" from operating modes list, only "manual" and "automatic" modes exist in the DPLL API - Fix typo "locked-ho-ack" -> "locked-ho-acq" in lock status list - Add missing device show output fields: lock-status-error, clock-quality-level, mode-supported, phase-offset-monitor and phase-offset-avg-factor - Add missing pin show output fields: panel-label, package-label, fractional-frequency-offset and esync-pulse - Remove non-existent exit codes 2 and 255, the tool only returns 0 (success) or 1 (failure) - Use canonical enable/disable for phase-offset-monitor to match the tool's help text Fixes: 656cfc3ce05b ("dpll: Add dpll command") Signed-off-by: Ivan Vecera Reviewed-by: Vadim Fedorenko Signed-off-by: Stephen Hemminger --- diff --git a/man/man8/dpll.8 b/man/man8/dpll.8 index 89f17af7..3abed86f 100644 --- a/man/man8/dpll.8 +++ b/man/man8/dpll.8 @@ -102,13 +102,23 @@ Module name providing the device .IP \[bu] Clock ID (unique identifier) .IP \[bu] -Operating mode (manual, automatic, holdover, freerun) +Operating mode (manual, automatic) .IP \[bu] -Lock status (locked-ho-ack, locked, unlocked, holdover) +Lock status (unlocked, locked, locked-ho-acq, holdover) +.IP \[bu] +Lock status error (if present) +.IP \[bu] +Clock quality level (if supported) .IP \[bu] Temperature (if supported) .IP \[bu] Type (PPS or EEC) +.IP \[bu] +Supported modes +.IP \[bu] +Phase offset monitor status (enable/disable) +.IP \[bu] +Phase offset averaging factor .RE .SS dpll device set id ID [ mode { automatic | manual } ] [ phase-offset-monitor { enable | disable } ] [ phase-offset-avg-factor FACTOR ] @@ -131,7 +141,7 @@ mode, the input source must be explicitly configured and the DPLL will not automatically switch sources. .TP -.BI phase-offset-monitor " { enable | disable | true | false | 0 | 1 }" +.BI phase-offset-monitor " { enable | disable }" Enable or disable phase offset monitoring between the device and its pins. When enabled, the kernel continuously measures and reports phase differences. @@ -231,6 +241,10 @@ Clock ID .IP \[bu] Board label (hardware label from device tree or ACPI) .IP \[bu] +Panel label +.IP \[bu] +Package label +.IP \[bu] Pin type (mux, ext, synce-eth-port, int-oscillator, gnss) .IP \[bu] Frequency and supported frequency ranges @@ -239,13 +253,15 @@ Capabilities (state-can-change, priority-can-change, direction-can-change) .IP \[bu] Phase adjustment range, granularity, and current value .IP \[bu] +Fractional frequency offset +.IP \[bu] Parent device relationships (direction, priority, state, phase offset) .IP \[bu] Parent pin relationships .IP \[bu] Reference sync information .IP \[bu] -Esync frequency support (if applicable) +Esync frequency and pulse support (if applicable) .RE .SS dpll pin set id ID [ PARAMETER VALUE ] ... @@ -495,13 +511,7 @@ changes. Success .TP .B 1 -General failure -.TP -.B 2 -Invalid arguments or usage -.TP -.B 255 -Netlink communication error +Failure .SH NOTES .IP \[bu] 2