From: Greg Kroah-Hartman Date: Mon, 27 Sep 2021 11:07:58 +0000 (+0200) Subject: 4.14-stable patches X-Git-Tag: v5.4.150~18 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=0d2bdeb1ea7ea339e518a8c89b249588e13eb574;p=thirdparty%2Fkernel%2Fstable-queue.git 4.14-stable patches added patches: arm64-dts-marvell-armada-37xx-extend-pcie-mem-space.patch pci-aardvark-fix-checking-for-pio-non-posted-request.patch pci-aardvark-fix-checking-for-pio-status.patch --- diff --git a/queue-4.14/arm64-dts-marvell-armada-37xx-extend-pcie-mem-space.patch b/queue-4.14/arm64-dts-marvell-armada-37xx-extend-pcie-mem-space.patch new file mode 100644 index 00000000000..4ca848b189e --- /dev/null +++ b/queue-4.14/arm64-dts-marvell-armada-37xx-extend-pcie-mem-space.patch @@ -0,0 +1,72 @@ +From 514ef1e62d6521c2199d192b1c71b79d2aa21d5a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Thu, 24 Jun 2021 23:55:46 +0200 +Subject: arm64: dts: marvell: armada-37xx: Extend PCIe MEM space +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Pali Rohár + +commit 514ef1e62d6521c2199d192b1c71b79d2aa21d5a upstream. + +Current PCIe MEM space of size 16 MB is not enough for some combination +of PCIe cards (e.g. NVMe disk together with ath11k wifi card). ARM Trusted +Firmware for Armada 3700 platform already assigns 128 MB for PCIe window, +so extend PCIe MEM space to the end of 128 MB PCIe window which allows to +allocate more PCIe BARs for more PCIe cards. + +Without this change some combination of PCIe cards cannot be used and +kernel show error messages in dmesg during initialization: + + pci 0000:00:00.0: BAR 8: no space for [mem size 0x01800000] + pci 0000:00:00.0: BAR 8: failed to assign [mem size 0x01800000] + pci 0000:00:00.0: BAR 6: assigned [mem 0xe8000000-0xe80007ff pref] + pci 0000:01:00.0: BAR 8: no space for [mem size 0x01800000] + pci 0000:01:00.0: BAR 8: failed to assign [mem size 0x01800000] + pci 0000:02:03.0: BAR 8: no space for [mem size 0x01000000] + pci 0000:02:03.0: BAR 8: failed to assign [mem size 0x01000000] + pci 0000:02:07.0: BAR 8: no space for [mem size 0x00100000] + pci 0000:02:07.0: BAR 8: failed to assign [mem size 0x00100000] + pci 0000:03:00.0: BAR 0: no space for [mem size 0x01000000 64bit] + pci 0000:03:00.0: BAR 0: failed to assign [mem size 0x01000000 64bit] + +Due to bugs in U-Boot port for Turris Mox, the second range in Turris Mox +kernel DTS file for PCIe must start at 16 MB offset. Otherwise U-Boot +crashes during loading of kernel DTB file. This bug is present only in +U-Boot code for Turris Mox and therefore other Armada 3700 devices are not +affected by this bug. Bug is fixed in U-Boot version 2021.07. + +To not break booting new kernels on existing versions of U-Boot on Turris +Mox, use first 16 MB range for IO and second range with rest of PCIe window +for MEM. + +Signed-off-by: Pali Rohár +Fixes: 76f6386b25cc ("arm64: dts: marvell: Add Aardvark PCIe support for Armada 3700") +Signed-off-by: Gregory CLEMENT +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi ++++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +@@ -347,8 +347,15 @@ + #interrupt-cells = <1>; + msi-parent = <&pcie0>; + msi-controller; +- ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ +- 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ ++ /* ++ * The 128 MiB address range [0xe8000000-0xf0000000] is ++ * dedicated for PCIe and can be assigned to 8 windows ++ * with size a power of two. Use one 64 KiB window for ++ * IO at the end and the remaining seven windows ++ * (totaling 127 MiB) for MEM. ++ */ ++ ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */ ++ 0x81000000 0 0xefff0000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */ + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, diff --git a/queue-4.14/pci-aardvark-fix-checking-for-pio-non-posted-request.patch b/queue-4.14/pci-aardvark-fix-checking-for-pio-non-posted-request.patch new file mode 100644 index 00000000000..77259e035d5 --- /dev/null +++ b/queue-4.14/pci-aardvark-fix-checking-for-pio-non-posted-request.patch @@ -0,0 +1,37 @@ +From 8ceeac307a79f68c0d0c72d6e48b82fa424204ec Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Thu, 24 Jun 2021 23:33:43 +0200 +Subject: PCI: aardvark: Fix checking for PIO Non-posted Request +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Pali Rohár + +commit 8ceeac307a79f68c0d0c72d6e48b82fa424204ec upstream. + +PIO_NON_POSTED_REQ for PIO_STAT register is incorrectly defined. Bit 10 in +register PIO_STAT indicates the response is to a non-posted request. + +Link: https://lore.kernel.org/r/20210624213345.3617-2-pali@kernel.org +Signed-off-by: Pali Rohár +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Marek Behún +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/host/pci-aardvark.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pci/host/pci-aardvark.c ++++ b/drivers/pci/host/pci-aardvark.c +@@ -55,7 +55,7 @@ + #define PIO_COMPLETION_STATUS_UR 1 + #define PIO_COMPLETION_STATUS_CRS 2 + #define PIO_COMPLETION_STATUS_CA 4 +-#define PIO_NON_POSTED_REQ BIT(0) ++#define PIO_NON_POSTED_REQ BIT(10) + #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) + #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) + #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) diff --git a/queue-4.14/pci-aardvark-fix-checking-for-pio-status.patch b/queue-4.14/pci-aardvark-fix-checking-for-pio-status.patch new file mode 100644 index 00000000000..41a956e31e9 --- /dev/null +++ b/queue-4.14/pci-aardvark-fix-checking-for-pio-status.patch @@ -0,0 +1,163 @@ +From fcb461e2bc8b83b7eaca20cb2221e8b940f2189c Mon Sep 17 00:00:00 2001 +From: Evan Wang +Date: Thu, 22 Jul 2021 16:40:38 +0200 +Subject: PCI: aardvark: Fix checking for PIO status +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Evan Wang + +commit fcb461e2bc8b83b7eaca20cb2221e8b940f2189c upstream. + +There is an issue that when PCIe switch is connected to an Armada 3700 +board, there will be lots of warnings about PIO errors when reading the +config space. According to Aardvark PIO read and write sequence in HW +specification, the current way to check PIO status has the following +issues: + +1) For PIO read operation, it reports the error message, which should be + avoided according to HW specification. + +2) For PIO read and write operations, it only checks PIO operation complete + status, which is not enough, and error status should also be checked. + +This patch aligns the code with Aardvark PIO read and write sequence in HW +specification on PIO status check and fix the warnings when reading config +space. + +[pali: Fix CRS handling when CRSSVE is not enabled] + +Link: https://lore.kernel.org/r/20210722144041.12661-2-pali@kernel.org +Tested-by: Victor Gu +Signed-off-by: Evan Wang +Signed-off-by: Pali Rohár +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Victor Gu +Reviewed-by: Marek Behún +Cc: stable@vger.kernel.org # b1bd5714472c ("PCI: aardvark: Indicate error in 'val' when config read fails") +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/host/pci-aardvark.c | 62 ++++++++++++++++++++++++++++++++++------ + 1 file changed, 54 insertions(+), 8 deletions(-) + +--- a/drivers/pci/host/pci-aardvark.c ++++ b/drivers/pci/host/pci-aardvark.c +@@ -56,6 +56,7 @@ + #define PIO_COMPLETION_STATUS_CRS 2 + #define PIO_COMPLETION_STATUS_CA 4 + #define PIO_NON_POSTED_REQ BIT(10) ++#define PIO_ERR_STATUS BIT(11) + #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) + #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) + #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) +@@ -374,7 +375,7 @@ static void advk_pcie_setup_hw(struct ad + advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); + } + +-static void advk_pcie_check_pio_status(struct advk_pcie *pcie) ++static int advk_pcie_check_pio_status(struct advk_pcie *pcie, u32 *val) + { + struct device *dev = &pcie->pdev->dev; + u32 reg; +@@ -385,14 +386,49 @@ static void advk_pcie_check_pio_status(s + status = (reg & PIO_COMPLETION_STATUS_MASK) >> + PIO_COMPLETION_STATUS_SHIFT; + +- if (!status) +- return; +- ++ /* ++ * According to HW spec, the PIO status check sequence as below: ++ * 1) even if COMPLETION_STATUS(bit9:7) indicates successful, ++ * it still needs to check Error Status(bit11), only when this bit ++ * indicates no error happen, the operation is successful. ++ * 2) value Unsupported Request(1) of COMPLETION_STATUS(bit9:7) only ++ * means a PIO write error, and for PIO read it is successful with ++ * a read value of 0xFFFFFFFF. ++ * 3) value Completion Retry Status(CRS) of COMPLETION_STATUS(bit9:7) ++ * only means a PIO write error, and for PIO read it is successful ++ * with a read value of 0xFFFF0001. ++ * 4) value Completer Abort (CA) of COMPLETION_STATUS(bit9:7) means ++ * error for both PIO read and PIO write operation. ++ * 5) other errors are indicated as 'unknown'. ++ */ + switch (status) { ++ case PIO_COMPLETION_STATUS_OK: ++ if (reg & PIO_ERR_STATUS) { ++ strcomp_status = "COMP_ERR"; ++ break; ++ } ++ /* Get the read result */ ++ if (val) ++ *val = advk_readl(pcie, PIO_RD_DATA); ++ /* No error */ ++ strcomp_status = NULL; ++ break; + case PIO_COMPLETION_STATUS_UR: + strcomp_status = "UR"; + break; + case PIO_COMPLETION_STATUS_CRS: ++ /* PCIe r4.0, sec 2.3.2, says: ++ * If CRS Software Visibility is not enabled, the Root Complex ++ * must re-issue the Configuration Request as a new Request. ++ * A Root Complex implementation may choose to limit the number ++ * of Configuration Request/CRS Completion Status loops before ++ * determining that something is wrong with the target of the ++ * Request and taking appropriate action, e.g., complete the ++ * Request to the host as a failed transaction. ++ * ++ * To simplify implementation do not re-issue the Configuration ++ * Request and complete the Request as a failed transaction. ++ */ + strcomp_status = "CRS"; + break; + case PIO_COMPLETION_STATUS_CA: +@@ -403,6 +439,9 @@ static void advk_pcie_check_pio_status(s + break; + } + ++ if (!strcomp_status) ++ return 0; ++ + if (reg & PIO_NON_POSTED_REQ) + str_posted = "Non-posted"; + else +@@ -410,6 +449,8 @@ static void advk_pcie_check_pio_status(s + + dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n", + str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); ++ ++ return -EFAULT; + } + + static int advk_pcie_wait_pio(struct advk_pcie *pcie) +@@ -502,10 +543,13 @@ static int advk_pcie_rd_conf(struct pci_ + if (ret < 0) + return PCIBIOS_SET_FAILED; + +- advk_pcie_check_pio_status(pcie); ++ /* Check PIO status and get the read result */ ++ ret = advk_pcie_check_pio_status(pcie, val); ++ if (ret < 0) { ++ *val = 0xffffffff; ++ return PCIBIOS_SET_FAILED; ++ } + +- /* Get the read result */ +- *val = advk_readl(pcie, PIO_RD_DATA); + if (size == 1) + *val = (*val >> (8 * (where & 3))) & 0xff; + else if (size == 2) +@@ -565,7 +609,9 @@ static int advk_pcie_wr_conf(struct pci_ + if (ret < 0) + return PCIBIOS_SET_FAILED; + +- advk_pcie_check_pio_status(pcie); ++ ret = advk_pcie_check_pio_status(pcie, NULL); ++ if (ret < 0) ++ return PCIBIOS_SET_FAILED; + + return PCIBIOS_SUCCESSFUL; + } diff --git a/queue-4.14/series b/queue-4.14/series index ab8796d3dc3..bf0af707e4b 100644 --- a/queue-4.14/series +++ b/queue-4.14/series @@ -34,3 +34,6 @@ arm64-mark-__stack_chk_guard-as-__ro_after_init.patch alpha-declare-virt_to_phys-and-virt_to_bus-parameter.patch net-6pack-fix-tx-timeout-and-slot-time.patch spi-fix-tegra20-build-with-config_pm-n.patch +arm64-dts-marvell-armada-37xx-extend-pcie-mem-space.patch +pci-aardvark-fix-checking-for-pio-non-posted-request.patch +pci-aardvark-fix-checking-for-pio-status.patch