From: Nathalie Chan King Choy Date: Wed, 9 Nov 2016 21:45:06 +0000 (-0800) Subject: ARM64: zcu100: Correct GT Ref clock source X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=0ddc9269dc8e629f820d8507d3a84d34b5ad053d;p=thirdparty%2Fu-boot.git ARM64: zcu100: Correct GT Ref clock source Choose ref clock sources to match ZCU100 schematic. Signed-off-by: Nathalie Chan King Choy Signed-off-by: Michal Simek --- diff --git a/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.c index deb81810d05..a1c775384b8 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.c @@ -10343,35 +10343,31 @@ unsigned long psu_serdes_init_data() { Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output. PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x0 - Bit 2 of lane 0 ref clock mux one hot sel. Set to 1 to select lane 2 slicer output from ref clock network - PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_2 0x1 + Bit 1 of lane 0 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network + PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_1 0x1 Lane0 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD402860, 0x00000084U ,0x00000004U) - RegMask = (SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK | SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_2_MASK | 0 ); + (OFFSET, MASK, VALUE) (0XFD402860, 0x00000082U ,0x00000002U) + RegMask = (SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK | SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_1_MASK | 0 ); RegVal = ((0x00000000U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT - | 0x00000001U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_2_SHIFT + | 0x00000001U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_1_SHIFT | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L0_REF_CLK_SEL_OFFSET ,0x00000084U ,0x00000004U); + PSU_Mask_Write (SERDES_L0_L0_REF_CLK_SEL_OFFSET ,0x00000082U ,0x00000002U); /*############################################################################################################################ */ /*Register : L0_L1_REF_CLK_SEL @ 0XFD402864

Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output. - PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0 - - Bit 2 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 2 slicer output from ref clock network - PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_2 0x1 + PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x1 Lane1 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD402864, 0x00000084U ,0x00000004U) - RegMask = (SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK | SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_2_MASK | 0 ); + (OFFSET, MASK, VALUE) (0XFD402864, 0x00000080U ,0x00000080U) + RegMask = (SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK | 0 ); - RegVal = ((0x00000000U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT - | 0x00000001U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_2_SHIFT + RegVal = ((0x00000001U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L1_REF_CLK_SEL_OFFSET ,0x00000084U ,0x00000004U); + PSU_Mask_Write (SERDES_L0_L1_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U); /*############################################################################################################################ */ /*Register : L0_L2_REF_CLK_SEL @ 0XFD402868

@@ -10379,31 +10375,35 @@ unsigned long psu_serdes_init_data() { Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output. PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x0 - Bit 3 of lane 2 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network - PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_3 0x1 + Bit 0 of lane 2 ref clock mux one hot sel. Set to 1 to select lane 0 slicer output from ref clock network + PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_0 0x1 Lane2 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD402868, 0x00000088U ,0x00000008U) - RegMask = (SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK | SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_3_MASK | 0 ); + (OFFSET, MASK, VALUE) (0XFD402868, 0x00000081U ,0x00000001U) + RegMask = (SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK | SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_0_MASK | 0 ); RegVal = ((0x00000000U << SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT - | 0x00000001U << SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_3_SHIFT + | 0x00000001U << SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_0_SHIFT | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L2_REF_CLK_SEL_OFFSET ,0x00000088U ,0x00000008U); + PSU_Mask_Write (SERDES_L0_L2_REF_CLK_SEL_OFFSET ,0x00000081U ,0x00000001U); /*############################################################################################################################ */ /*Register : L0_L3_REF_CLK_SEL @ 0XFD40286C

Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output. - PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x1 + PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0 + + Bit 0 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 0 slicer output from ref clock network + PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_0 0x1 Lane3 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK | 0 ); + (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000081U ,0x00000001U) + RegMask = (SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK | SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_0_MASK | 0 ); - RegVal = ((0x00000001U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT + RegVal = ((0x00000000U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT + | 0x00000001U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_0_SHIFT | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L3_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U); + PSU_Mask_Write (SERDES_L0_L3_REF_CLK_SEL_OFFSET ,0x00000081U ,0x00000001U); /*############################################################################################################################ */ // : ENABLE SPREAD SPECTRUM diff --git a/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.h b/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.h index c259cfc67c4..9a07ecfd901 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.h +++ b/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.h @@ -13246,13 +13246,13 @@ #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 7 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Bit 2 of lane 0 ref clock mux one hot sel. Set to 1 to select lane 2 slicer output from ref clock network*/ -#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_2_DEFVAL -#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_2_SHIFT -#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_2_MASK -#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_2_DEFVAL 0x00000080 -#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_2_SHIFT 2 -#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_2_MASK 0x00000004U +/*Bit 1 of lane 0 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network*/ +#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_1_DEFVAL +#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_1_SHIFT +#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_1_MASK +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_1_DEFVAL 0x00000080 +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_1_SHIFT 1 +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_1_MASK 0x00000002U /*Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.*/ #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL @@ -13262,14 +13262,6 @@ #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 7 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Bit 2 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 2 slicer output from ref clock network*/ -#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_2_DEFVAL -#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_2_SHIFT -#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_2_MASK -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_2_DEFVAL 0x00000080 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_2_SHIFT 2 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_2_MASK 0x00000004U - /*Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.*/ #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT @@ -13278,13 +13270,13 @@ #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 7 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Bit 3 of lane 2 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network*/ -#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_3_DEFVAL -#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_3_SHIFT -#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_3_MASK -#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_3_DEFVAL 0x00000080 -#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_3_SHIFT 3 -#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_3_MASK 0x00000008U +/*Bit 0 of lane 2 ref clock mux one hot sel. Set to 1 to select lane 0 slicer output from ref clock network*/ +#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_0_DEFVAL +#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_0_SHIFT +#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_0_MASK +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_0_DEFVAL 0x00000080 +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_0_SHIFT 0 +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_SEL_0_MASK 0x00000001U /*Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.*/ #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL @@ -13294,6 +13286,14 @@ #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 7 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 0x00000080U +/*Bit 0 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 0 slicer output from ref clock network*/ +#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_0_DEFVAL +#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_0_SHIFT +#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_0_MASK +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_0_DEFVAL 0x00000080 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_0_SHIFT 0 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_0_MASK 0x00000001U + /*Enable/Disable coarse code satureation limiting logic*/ #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT