From: Sasha Levin Date: Mon, 17 Jun 2024 11:30:33 +0000 (-0400) Subject: Fixes for 5.10 X-Git-Tag: v6.1.95~109 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=0f7e0ad96663f316e2a885d8751f2a3e416644dc;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.10 Signed-off-by: Sasha Levin --- diff --git a/queue-5.10/bluetooth-l2cap-fix-rejecting-l2cap_conn_param_updat.patch b/queue-5.10/bluetooth-l2cap-fix-rejecting-l2cap_conn_param_updat.patch new file mode 100644 index 00000000000..ab50c676111 --- /dev/null +++ b/queue-5.10/bluetooth-l2cap-fix-rejecting-l2cap_conn_param_updat.patch @@ -0,0 +1,108 @@ +From 82763139fc1bfc3a6bfbef859f8a8f97f835add1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 May 2024 16:03:07 -0400 +Subject: Bluetooth: L2CAP: Fix rejecting L2CAP_CONN_PARAM_UPDATE_REQ + +From: Luiz Augusto von Dentz + +[ Upstream commit 806a5198c05987b748b50f3d0c0cfb3d417381a4 ] + +This removes the bogus check for max > hcon->le_conn_max_interval since +the later is just the initial maximum conn interval not the maximum the +stack could support which is really 3200=4000ms. + +In order to pass GAP/CONN/CPUP/BV-05-C one shall probably enter values +of the following fields in IXIT that would cause hci_check_conn_params +to fail: + +TSPX_conn_update_int_min +TSPX_conn_update_int_max +TSPX_conn_update_peripheral_latency +TSPX_conn_update_supervision_timeout + +Link: https://github.com/bluez/bluez/issues/847 +Fixes: e4b019515f95 ("Bluetooth: Enforce validation on max value of connection interval") +Signed-off-by: Luiz Augusto von Dentz +Signed-off-by: Sasha Levin +--- + include/net/bluetooth/hci_core.h | 36 ++++++++++++++++++++++++++++---- + net/bluetooth/l2cap_core.c | 8 +------ + 2 files changed, 33 insertions(+), 11 deletions(-) + +diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h +index 33873266b2bc7..9128c0db11f88 100644 +--- a/include/net/bluetooth/hci_core.h ++++ b/include/net/bluetooth/hci_core.h +@@ -1625,18 +1625,46 @@ static inline int hci_check_conn_params(u16 min, u16 max, u16 latency, + { + u16 max_latency; + +- if (min > max || min < 6 || max > 3200) ++ if (min > max) { ++ BT_WARN("min %d > max %d", min, max); + return -EINVAL; ++ } ++ ++ if (min < 6) { ++ BT_WARN("min %d < 6", min); ++ return -EINVAL; ++ } ++ ++ if (max > 3200) { ++ BT_WARN("max %d > 3200", max); ++ return -EINVAL; ++ } ++ ++ if (to_multiplier < 10) { ++ BT_WARN("to_multiplier %d < 10", to_multiplier); ++ return -EINVAL; ++ } + +- if (to_multiplier < 10 || to_multiplier > 3200) ++ if (to_multiplier > 3200) { ++ BT_WARN("to_multiplier %d > 3200", to_multiplier); + return -EINVAL; ++ } + +- if (max >= to_multiplier * 8) ++ if (max >= to_multiplier * 8) { ++ BT_WARN("max %d >= to_multiplier %d * 8", max, to_multiplier); + return -EINVAL; ++ } + + max_latency = (to_multiplier * 4 / max) - 1; +- if (latency > 499 || latency > max_latency) ++ if (latency > 499) { ++ BT_WARN("latency %d > 499", latency); + return -EINVAL; ++ } ++ ++ if (latency > max_latency) { ++ BT_WARN("latency %d > max_latency %d", latency, max_latency); ++ return -EINVAL; ++ } + + return 0; + } +diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c +index da03ca6dd9221..9cc034e6074c1 100644 +--- a/net/bluetooth/l2cap_core.c ++++ b/net/bluetooth/l2cap_core.c +@@ -5612,13 +5612,7 @@ static inline int l2cap_conn_param_update_req(struct l2cap_conn *conn, + + memset(&rsp, 0, sizeof(rsp)); + +- if (max > hcon->le_conn_max_interval) { +- BT_DBG("requested connection interval exceeds current bounds."); +- err = -EINVAL; +- } else { +- err = hci_check_conn_params(min, max, latency, to_multiplier); +- } +- ++ err = hci_check_conn_params(min, max, latency, to_multiplier); + if (err) + rsp.result = cpu_to_le16(L2CAP_CONN_PARAM_REJECTED); + else +-- +2.43.0 + diff --git a/queue-5.10/clk-sifive-do-not-register-clkdevs-for-prci-clocks.patch b/queue-5.10/clk-sifive-do-not-register-clkdevs-for-prci-clocks.patch new file mode 100644 index 00000000000..cc801fa69ba --- /dev/null +++ b/queue-5.10/clk-sifive-do-not-register-clkdevs-for-prci-clocks.patch @@ -0,0 +1,62 @@ +From 4e248c24e73eb129235ddf9172597a6cee057dbd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 27 May 2024 17:14:12 -0700 +Subject: clk: sifive: Do not register clkdevs for PRCI clocks + +From: Samuel Holland + +[ Upstream commit 2607133196c35f31892ee199ce7ffa717bea4ad1 ] + +These clkdevs were unnecessary, because systems using this driver always +look up clocks using the devicetree. And as Russell King points out[1], +since the provided device name was truncated, lookups via clkdev would +never match. + +Recently, commit 8d532528ff6a ("clkdev: report over-sized strings when +creating clkdev entries") caused clkdev registration to fail due to the +truncation, and this now prevents the driver from probing. Fix the +driver by removing the clkdev registration. + +Link: https://lore.kernel.org/linux-clk/ZkfYqj+OcAxd9O2t@shell.armlinux.org.uk/ [1] +Fixes: 30b8e27e3b58 ("clk: sifive: add a driver for the SiFive FU540 PRCI IP block") +Fixes: 8d532528ff6a ("clkdev: report over-sized strings when creating clkdev entries") +Reported-by: Guenter Roeck +Closes: https://lore.kernel.org/linux-clk/7eda7621-0dde-4153-89e4-172e4c095d01@roeck-us.net/ +Suggested-by: Russell King +Signed-off-by: Samuel Holland +Link: https://lore.kernel.org/r/20240528001432.1200403-1-samuel.holland@sifive.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/sifive/sifive-prci.c | 8 -------- + 1 file changed, 8 deletions(-) + +diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c +index 70653d33f33fe..b043180ad3e5d 100644 +--- a/drivers/clk/sifive/sifive-prci.c ++++ b/drivers/clk/sifive/sifive-prci.c +@@ -4,7 +4,6 @@ + * Copyright (C) 2020 Zong Li + */ + +-#include + #include + #include + #include +@@ -317,13 +316,6 @@ static int __prci_register_clocks(struct device *dev, struct __prci_data *pd, + return r; + } + +- r = clk_hw_register_clkdev(&pic->hw, pic->name, dev_name(dev)); +- if (r) { +- dev_warn(dev, "Failed to register clkdev for %s: %d\n", +- init.name, r); +- return r; +- } +- + pd->hw_clks.hws[i] = &pic->hw; + } + +-- +2.43.0 + diff --git a/queue-5.10/clk-sifive-extract-prci-core-to-common-base.patch b/queue-5.10/clk-sifive-extract-prci-core-to-common-base.patch new file mode 100644 index 00000000000..c6ef251ce66 --- /dev/null +++ b/queue-5.10/clk-sifive-extract-prci-core-to-common-base.patch @@ -0,0 +1,1318 @@ +From 8fe0f6fb3c2cab46eaff8297d9043035d0ca3fd6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 9 Dec 2020 17:49:12 +0800 +Subject: clk: sifive: Extract prci core to common base + +From: Zong Li + +[ Upstream commit c816e1ddf2b60b31d121118488c5a854d9a2fad9 ] + +Extract common core of prci driver to an independent file, it could +allow other chips to reuse it. Separate SoCs-dependent code 'fu540' +from prci core, then we can easily add 'fu740' later. + +Almost these changes are code movement. The different is adding the +private data for each SoC use, so it needs to get match data in probe +callback function, then use the data for initialization. + +Signed-off-by: Zong Li +Reviewed-by: Pragnesh Patel +Acked-by: Palmer Dabbelt +Link: https://lore.kernel.org/r/20201209094916.17383-2-zong.li@sifive.com +[sboyd@kernel.org: Include header to silence sparse] +Signed-off-by: Stephen Boyd +Stable-dep-of: 2607133196c3 ("clk: sifive: Do not register clkdevs for PRCI clocks") +Signed-off-by: Sasha Levin +--- + drivers/clk/sifive/Makefile | 2 +- + drivers/clk/sifive/fu540-prci.c | 593 ++----------------------------- + drivers/clk/sifive/fu540-prci.h | 21 ++ + drivers/clk/sifive/sifive-prci.c | 395 ++++++++++++++++++++ + drivers/clk/sifive/sifive-prci.h | 201 +++++++++++ + 5 files changed, 641 insertions(+), 571 deletions(-) + create mode 100644 drivers/clk/sifive/fu540-prci.h + create mode 100644 drivers/clk/sifive/sifive-prci.c + create mode 100644 drivers/clk/sifive/sifive-prci.h + +diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile +index 0797f14fef6b6..51b6ebc359e44 100644 +--- a/drivers/clk/sifive/Makefile ++++ b/drivers/clk/sifive/Makefile +@@ -1,2 +1,2 @@ + # SPDX-License-Identifier: GPL-2.0-only +-obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += fu540-prci.o ++obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += sifive-prci.o fu540-prci.o +diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c +index a8901f90a61ac..83ced24b0b949 100644 +--- a/drivers/clk/sifive/fu540-prci.c ++++ b/drivers/clk/sifive/fu540-prci.c +@@ -1,17 +1,9 @@ + // SPDX-License-Identifier: GPL-2.0 + /* + * Copyright (C) 2018-2019 SiFive, Inc. +- * Wesley Terpstra +- * Paul Walmsley +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. ++ * Copyright (C) 2018-2019 Wesley Terpstra ++ * Copyright (C) 2018-2019 Paul Walmsley ++ * Copyright (C) 2020 Zong Li + * + * The FU540 PRCI implements clock and reset control for the SiFive + * FU540-C000 chip. This driver assumes that it has sole control +@@ -24,464 +16,47 @@ + * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset" + */ + +-#include +-#include +-#include +-#include +-#include +-#include +-#include + #include +-#include +-#include +-#include +-#include +- +-/* +- * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: +- * hfclk and rtcclk +- */ +-#define EXPECTED_CLK_PARENT_COUNT 2 +- +-/* +- * Register offsets and bitmasks +- */ +- +-/* COREPLLCFG0 */ +-#define PRCI_COREPLLCFG0_OFFSET 0x4 +-# define PRCI_COREPLLCFG0_DIVR_SHIFT 0 +-# define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT) +-# define PRCI_COREPLLCFG0_DIVF_SHIFT 6 +-# define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT) +-# define PRCI_COREPLLCFG0_DIVQ_SHIFT 15 +-# define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT) +-# define PRCI_COREPLLCFG0_RANGE_SHIFT 18 +-# define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT) +-# define PRCI_COREPLLCFG0_BYPASS_SHIFT 24 +-# define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT) +-# define PRCI_COREPLLCFG0_FSE_SHIFT 25 +-# define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT) +-# define PRCI_COREPLLCFG0_LOCK_SHIFT 31 +-# define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT) + +-/* DDRPLLCFG0 */ +-#define PRCI_DDRPLLCFG0_OFFSET 0xc +-# define PRCI_DDRPLLCFG0_DIVR_SHIFT 0 +-# define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT) +-# define PRCI_DDRPLLCFG0_DIVF_SHIFT 6 +-# define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT) +-# define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15 +-# define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT) +-# define PRCI_DDRPLLCFG0_RANGE_SHIFT 18 +-# define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT) +-# define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24 +-# define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) +-# define PRCI_DDRPLLCFG0_FSE_SHIFT 25 +-# define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT) +-# define PRCI_DDRPLLCFG0_LOCK_SHIFT 31 +-# define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT) +- +-/* DDRPLLCFG1 */ +-#define PRCI_DDRPLLCFG1_OFFSET 0x10 +-# define PRCI_DDRPLLCFG1_CKE_SHIFT 24 +-# define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) +- +-/* GEMGXLPLLCFG0 */ +-#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c +-# define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 +-# define PRCI_GEMGXLPLLCFG0_DIVR_MASK (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT) +-# define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6 +-# define PRCI_GEMGXLPLLCFG0_DIVF_MASK (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT) +-# define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15 +-# define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT) +-# define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18 +-# define PRCI_GEMGXLPLLCFG0_RANGE_MASK (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT) +-# define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24 +-# define PRCI_GEMGXLPLLCFG0_BYPASS_MASK (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT) +-# define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25 +-# define PRCI_GEMGXLPLLCFG0_FSE_MASK (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT) +-# define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31 +-# define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT) +- +-/* GEMGXLPLLCFG1 */ +-#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 +-# define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24 +-# define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) +- +-/* CORECLKSEL */ +-#define PRCI_CORECLKSEL_OFFSET 0x24 +-# define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0 +-# define PRCI_CORECLKSEL_CORECLKSEL_MASK (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT) +- +-/* DEVICESRESETREG */ +-#define PRCI_DEVICESRESETREG_OFFSET 0x28 +-# define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0 +-# define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT) +-# define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1 +-# define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT) +-# define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2 +-# define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT) +-# define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3 +-# define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT) +-# define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5 +-# define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT) ++#include + +-/* CLKMUXSTATUSREG */ +-#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c +-# define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 +-# define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT) ++#include "fu540-prci.h" ++#include "sifive-prci.h" + +-/* +- * Private structures +- */ ++/* PRCI integration data for each WRPLL instance */ + +-/** +- * struct __prci_data - per-device-instance data +- * @va: base virtual address of the PRCI IP block +- * @hw_clks: encapsulates struct clk_hw records +- * +- * PRCI per-device instance data +- */ +-struct __prci_data { +- void __iomem *va; +- struct clk_hw_onecell_data hw_clks; ++static struct __prci_wrpll_data __prci_corepll_data = { ++ .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, ++ .enable_bypass = sifive_prci_coreclksel_use_hfclk, ++ .disable_bypass = sifive_prci_coreclksel_use_corepll, + }; + +-/** +- * struct __prci_wrpll_data - WRPLL configuration and integration data +- * @c: WRPLL current configuration record +- * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL) +- * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL) +- * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address +- * +- * @enable_bypass and @disable_bypass are used for WRPLL instances +- * that contain a separate external glitchless clock mux downstream +- * from the PLL. The WRPLL internal bypass mux is not glitchless. +- */ +-struct __prci_wrpll_data { +- struct wrpll_cfg c; +- void (*enable_bypass)(struct __prci_data *pd); +- void (*disable_bypass)(struct __prci_data *pd); +- u8 cfg0_offs; ++static struct __prci_wrpll_data __prci_ddrpll_data = { ++ .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, + }; + +-/** +- * struct __prci_clock - describes a clock device managed by PRCI +- * @name: user-readable clock name string - should match the manual +- * @parent_name: parent name for this clock +- * @ops: struct clk_ops for the Linux clock framework to use for control +- * @hw: Linux-private clock data +- * @pwd: WRPLL-specific data, associated with this clock (if not NULL) +- * @pd: PRCI-specific data associated with this clock (if not NULL) +- * +- * PRCI clock data. Used by the PRCI driver to register PRCI-provided +- * clocks to the Linux clock infrastructure. +- */ +-struct __prci_clock { +- const char *name; +- const char *parent_name; +- const struct clk_ops *ops; +- struct clk_hw hw; +- struct __prci_wrpll_data *pwd; +- struct __prci_data *pd; ++static struct __prci_wrpll_data __prci_gemgxlpll_data = { ++ .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, + }; + +-#define clk_hw_to_prci_clock(pwd) container_of(pwd, struct __prci_clock, hw) +- +-/* +- * Private functions +- */ +- +-/** +- * __prci_readl() - read from a PRCI register +- * @pd: PRCI context +- * @offs: register offset to read from (in bytes, from PRCI base address) +- * +- * Read the register located at offset @offs from the base virtual +- * address of the PRCI register target described by @pd, and return +- * the value to the caller. +- * +- * Context: Any context. +- * +- * Return: the contents of the register described by @pd and @offs. +- */ +-static u32 __prci_readl(struct __prci_data *pd, u32 offs) +-{ +- return readl_relaxed(pd->va + offs); +-} +- +-static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd) +-{ +- writel_relaxed(v, pd->va + offs); +-} +- +-/* WRPLL-related private functions */ +- +-/** +- * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters +- * @c: ptr to a struct wrpll_cfg record to write config into +- * @r: value read from the PRCI PLL configuration register +- * +- * Given a value @r read from an FU540 PRCI PLL configuration register, +- * split it into fields and populate it into the WRPLL configuration record +- * pointed to by @c. +- * +- * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros +- * have the same register layout. +- * +- * Context: Any context. +- */ +-static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r) +-{ +- u32 v; +- +- v = r & PRCI_COREPLLCFG0_DIVR_MASK; +- v >>= PRCI_COREPLLCFG0_DIVR_SHIFT; +- c->divr = v; +- +- v = r & PRCI_COREPLLCFG0_DIVF_MASK; +- v >>= PRCI_COREPLLCFG0_DIVF_SHIFT; +- c->divf = v; +- +- v = r & PRCI_COREPLLCFG0_DIVQ_MASK; +- v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT; +- c->divq = v; +- +- v = r & PRCI_COREPLLCFG0_RANGE_MASK; +- v >>= PRCI_COREPLLCFG0_RANGE_SHIFT; +- c->range = v; +- +- c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK | +- WRPLL_FLAGS_EXT_FEEDBACK_MASK); +- +- /* external feedback mode not supported */ +- c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK; +-} +- +-/** +- * __prci_wrpll_pack() - pack PLL configuration parameters into a register value +- * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg +- * +- * Using a set of WRPLL configuration values pointed to by @c, +- * assemble a PRCI PLL configuration register value, and return it to +- * the caller. +- * +- * Context: Any context. Caller must ensure that the contents of the +- * record pointed to by @c do not change during the execution +- * of this function. +- * +- * Returns: a value suitable for writing into a PRCI PLL configuration +- * register +- */ +-static u32 __prci_wrpll_pack(const struct wrpll_cfg *c) +-{ +- u32 r = 0; +- +- r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT; +- r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT; +- r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT; +- r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT; +- +- /* external feedback mode not supported */ +- r |= PRCI_COREPLLCFG0_FSE_MASK; +- +- return r; +-} +- +-/** +- * __prci_wrpll_read_cfg() - read the WRPLL configuration from the PRCI +- * @pd: PRCI context +- * @pwd: PRCI WRPLL metadata +- * +- * Read the current configuration of the PLL identified by @pwd from +- * the PRCI identified by @pd, and store it into the local configuration +- * cache in @pwd. +- * +- * Context: Any context. Caller must prevent the records pointed to by +- * @pd and @pwd from changing during execution. +- */ +-static void __prci_wrpll_read_cfg(struct __prci_data *pd, +- struct __prci_wrpll_data *pwd) +-{ +- __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs)); +-} +- +-/** +- * __prci_wrpll_write_cfg() - write WRPLL configuration into the PRCI +- * @pd: PRCI context +- * @pwd: PRCI WRPLL metadata +- * @c: WRPLL configuration record to write +- * +- * Write the WRPLL configuration described by @c into the WRPLL +- * configuration register identified by @pwd in the PRCI instance +- * described by @c. Make a cached copy of the WRPLL's current +- * configuration so it can be used by other code. +- * +- * Context: Any context. Caller must prevent the records pointed to by +- * @pd and @pwd from changing during execution. +- */ +-static void __prci_wrpll_write_cfg(struct __prci_data *pd, +- struct __prci_wrpll_data *pwd, +- struct wrpll_cfg *c) +-{ +- __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd); +- +- memcpy(&pwd->c, c, sizeof(*c)); +-} +- +-/* Core clock mux control */ +- +-/** +- * __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK +- * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg +- * +- * Switch the CORECLK mux to the HFCLK input source; return once complete. +- * +- * Context: Any context. Caller must prevent concurrent changes to the +- * PRCI_CORECLKSEL_OFFSET register. +- */ +-static void __prci_coreclksel_use_hfclk(struct __prci_data *pd) +-{ +- u32 r; +- +- r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); +- r |= PRCI_CORECLKSEL_CORECLKSEL_MASK; +- __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); +- +- r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ +-} +- +-/** +- * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL +- * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg +- * +- * Switch the CORECLK mux to the PLL output clock; return once complete. +- * +- * Context: Any context. Caller must prevent concurrent changes to the +- * PRCI_CORECLKSEL_OFFSET register. +- */ +-static void __prci_coreclksel_use_corepll(struct __prci_data *pd) +-{ +- u32 r; +- +- r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); +- r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK; +- __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); +- +- r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ +-} +- +-/* +- * Linux clock framework integration +- * +- * See the Linux clock framework documentation for more information on +- * these functions. +- */ +- +-static unsigned long sifive_fu540_prci_wrpll_recalc_rate(struct clk_hw *hw, +- unsigned long parent_rate) +-{ +- struct __prci_clock *pc = clk_hw_to_prci_clock(hw); +- struct __prci_wrpll_data *pwd = pc->pwd; +- +- return wrpll_calc_output_rate(&pwd->c, parent_rate); +-} +- +-static long sifive_fu540_prci_wrpll_round_rate(struct clk_hw *hw, +- unsigned long rate, +- unsigned long *parent_rate) +-{ +- struct __prci_clock *pc = clk_hw_to_prci_clock(hw); +- struct __prci_wrpll_data *pwd = pc->pwd; +- struct wrpll_cfg c; +- +- memcpy(&c, &pwd->c, sizeof(c)); +- +- wrpll_configure_for_rate(&c, rate, *parent_rate); +- +- return wrpll_calc_output_rate(&c, *parent_rate); +-} +- +-static int sifive_fu540_prci_wrpll_set_rate(struct clk_hw *hw, +- unsigned long rate, +- unsigned long parent_rate) +-{ +- struct __prci_clock *pc = clk_hw_to_prci_clock(hw); +- struct __prci_wrpll_data *pwd = pc->pwd; +- struct __prci_data *pd = pc->pd; +- int r; +- +- r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate); +- if (r) +- return r; +- +- if (pwd->enable_bypass) +- pwd->enable_bypass(pd); +- +- __prci_wrpll_write_cfg(pd, pwd, &pwd->c); +- +- udelay(wrpll_calc_max_lock_us(&pwd->c)); +- +- if (pwd->disable_bypass) +- pwd->disable_bypass(pd); +- +- return 0; +-} ++/* Linux clock framework integration */ + + static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = { +- .set_rate = sifive_fu540_prci_wrpll_set_rate, +- .round_rate = sifive_fu540_prci_wrpll_round_rate, +- .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate, ++ .set_rate = sifive_prci_wrpll_set_rate, ++ .round_rate = sifive_prci_wrpll_round_rate, ++ .recalc_rate = sifive_prci_wrpll_recalc_rate, + }; + + static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = { +- .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate, ++ .recalc_rate = sifive_prci_wrpll_recalc_rate, + }; + +-/* TLCLKSEL clock integration */ +- +-static unsigned long sifive_fu540_prci_tlclksel_recalc_rate(struct clk_hw *hw, +- unsigned long parent_rate) +-{ +- struct __prci_clock *pc = clk_hw_to_prci_clock(hw); +- struct __prci_data *pd = pc->pd; +- u32 v; +- u8 div; +- +- v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET); +- v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK; +- div = v ? 1 : 2; +- +- return div_u64(parent_rate, div); +-} +- + static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = { +- .recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate, +-}; +- +-/* +- * PRCI integration data for each WRPLL instance +- */ +- +-static struct __prci_wrpll_data __prci_corepll_data = { +- .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, +- .enable_bypass = __prci_coreclksel_use_hfclk, +- .disable_bypass = __prci_coreclksel_use_corepll, +-}; +- +-static struct __prci_wrpll_data __prci_ddrpll_data = { +- .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, ++ .recalc_rate = sifive_prci_tlclksel_recalc_rate, + }; + +-static struct __prci_wrpll_data __prci_gemgxlpll_data = { +- .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, +-}; +- +-/* +- * List of clock controls provided by the PRCI +- */ +- +-static struct __prci_clock __prci_init_clocks[] = { ++/* List of clock controls provided by the PRCI */ ++struct __prci_clock __prci_init_clocks_fu540[] = { + [PRCI_CLK_COREPLL] = { + .name = "corepll", + .parent_name = "hfclk", +@@ -506,125 +81,3 @@ static struct __prci_clock __prci_init_clocks[] = { + .ops = &sifive_fu540_prci_tlclksel_clk_ops, + }, + }; +- +-/** +- * __prci_register_clocks() - register clock controls in the PRCI with Linux +- * @dev: Linux struct device * +- * +- * Register the list of clock controls described in __prci_init_plls[] with +- * the Linux clock framework. +- * +- * Return: 0 upon success or a negative error code upon failure. +- */ +-static int __prci_register_clocks(struct device *dev, struct __prci_data *pd) +-{ +- struct clk_init_data init = { }; +- struct __prci_clock *pic; +- int parent_count, i, r; +- +- parent_count = of_clk_get_parent_count(dev->of_node); +- if (parent_count != EXPECTED_CLK_PARENT_COUNT) { +- dev_err(dev, "expected only two parent clocks, found %d\n", +- parent_count); +- return -EINVAL; +- } +- +- /* Register PLLs */ +- for (i = 0; i < ARRAY_SIZE(__prci_init_clocks); ++i) { +- pic = &__prci_init_clocks[i]; +- +- init.name = pic->name; +- init.parent_names = &pic->parent_name; +- init.num_parents = 1; +- init.ops = pic->ops; +- pic->hw.init = &init; +- +- pic->pd = pd; +- +- if (pic->pwd) +- __prci_wrpll_read_cfg(pd, pic->pwd); +- +- r = devm_clk_hw_register(dev, &pic->hw); +- if (r) { +- dev_warn(dev, "Failed to register clock %s: %d\n", +- init.name, r); +- return r; +- } +- +- r = clk_hw_register_clkdev(&pic->hw, pic->name, dev_name(dev)); +- if (r) { +- dev_warn(dev, "Failed to register clkdev for %s: %d\n", +- init.name, r); +- return r; +- } +- +- pd->hw_clks.hws[i] = &pic->hw; +- } +- +- pd->hw_clks.num = i; +- +- r = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, +- &pd->hw_clks); +- if (r) { +- dev_err(dev, "could not add hw_provider: %d\n", r); +- return r; +- } +- +- return 0; +-} +- +-/* +- * Linux device model integration +- * +- * See the Linux device model documentation for more information about +- * these functions. +- */ +-static int sifive_fu540_prci_probe(struct platform_device *pdev) +-{ +- struct device *dev = &pdev->dev; +- struct resource *res; +- struct __prci_data *pd; +- int r; +- +- pd = devm_kzalloc(dev, +- struct_size(pd, hw_clks.hws, +- ARRAY_SIZE(__prci_init_clocks)), +- GFP_KERNEL); +- if (!pd) +- return -ENOMEM; +- +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- pd->va = devm_ioremap_resource(dev, res); +- if (IS_ERR(pd->va)) +- return PTR_ERR(pd->va); +- +- r = __prci_register_clocks(dev, pd); +- if (r) { +- dev_err(dev, "could not register clocks: %d\n", r); +- return r; +- } +- +- dev_dbg(dev, "SiFive FU540 PRCI probed\n"); +- +- return 0; +-} +- +-static const struct of_device_id sifive_fu540_prci_of_match[] = { +- { .compatible = "sifive,fu540-c000-prci", }, +- {} +-}; +-MODULE_DEVICE_TABLE(of, sifive_fu540_prci_of_match); +- +-static struct platform_driver sifive_fu540_prci_driver = { +- .driver = { +- .name = "sifive-fu540-prci", +- .of_match_table = sifive_fu540_prci_of_match, +- }, +- .probe = sifive_fu540_prci_probe, +-}; +- +-static int __init sifive_fu540_prci_init(void) +-{ +- return platform_driver_register(&sifive_fu540_prci_driver); +-} +-core_initcall(sifive_fu540_prci_init); +diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h +new file mode 100644 +index 0000000000000..c8271efa7bdc7 +--- /dev/null ++++ b/drivers/clk/sifive/fu540-prci.h +@@ -0,0 +1,21 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2020 SiFive, Inc. ++ * Zong Li ++ */ ++ ++#ifndef __SIFIVE_CLK_FU540_PRCI_H ++#define __SIFIVE_CLK_FU540_PRCI_H ++ ++#include "sifive-prci.h" ++ ++#define NUM_CLOCK_FU540 4 ++ ++extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540]; ++ ++static const struct prci_clk_desc prci_clk_fu540 = { ++ .clks = __prci_init_clocks_fu540, ++ .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), ++}; ++ ++#endif /* __SIFIVE_CLK_FU540_PRCI_H */ +diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c +new file mode 100644 +index 0000000000000..70653d33f33fe +--- /dev/null ++++ b/drivers/clk/sifive/sifive-prci.c +@@ -0,0 +1,395 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2020 SiFive, Inc. ++ * Copyright (C) 2020 Zong Li ++ */ ++ ++#include ++#include ++#include ++#include ++#include "sifive-prci.h" ++#include "fu540-prci.h" ++ ++/* ++ * Private functions ++ */ ++ ++/** ++ * __prci_readl() - read from a PRCI register ++ * @pd: PRCI context ++ * @offs: register offset to read from (in bytes, from PRCI base address) ++ * ++ * Read the register located at offset @offs from the base virtual ++ * address of the PRCI register target described by @pd, and return ++ * the value to the caller. ++ * ++ * Context: Any context. ++ * ++ * Return: the contents of the register described by @pd and @offs. ++ */ ++static u32 __prci_readl(struct __prci_data *pd, u32 offs) ++{ ++ return readl_relaxed(pd->va + offs); ++} ++ ++static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd) ++{ ++ writel_relaxed(v, pd->va + offs); ++} ++ ++/* WRPLL-related private functions */ ++ ++/** ++ * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters ++ * @c: ptr to a struct wrpll_cfg record to write config into ++ * @r: value read from the PRCI PLL configuration register ++ * ++ * Given a value @r read from an FU740 PRCI PLL configuration register, ++ * split it into fields and populate it into the WRPLL configuration record ++ * pointed to by @c. ++ * ++ * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros ++ * have the same register layout. ++ * ++ * Context: Any context. ++ */ ++static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r) ++{ ++ u32 v; ++ ++ v = r & PRCI_COREPLLCFG0_DIVR_MASK; ++ v >>= PRCI_COREPLLCFG0_DIVR_SHIFT; ++ c->divr = v; ++ ++ v = r & PRCI_COREPLLCFG0_DIVF_MASK; ++ v >>= PRCI_COREPLLCFG0_DIVF_SHIFT; ++ c->divf = v; ++ ++ v = r & PRCI_COREPLLCFG0_DIVQ_MASK; ++ v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT; ++ c->divq = v; ++ ++ v = r & PRCI_COREPLLCFG0_RANGE_MASK; ++ v >>= PRCI_COREPLLCFG0_RANGE_SHIFT; ++ c->range = v; ++ ++ c->flags &= ++ (WRPLL_FLAGS_INT_FEEDBACK_MASK | WRPLL_FLAGS_EXT_FEEDBACK_MASK); ++ ++ /* external feedback mode not supported */ ++ c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK; ++} ++ ++/** ++ * __prci_wrpll_pack() - pack PLL configuration parameters into a register value ++ * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg ++ * ++ * Using a set of WRPLL configuration values pointed to by @c, ++ * assemble a PRCI PLL configuration register value, and return it to ++ * the caller. ++ * ++ * Context: Any context. Caller must ensure that the contents of the ++ * record pointed to by @c do not change during the execution ++ * of this function. ++ * ++ * Returns: a value suitable for writing into a PRCI PLL configuration ++ * register ++ */ ++static u32 __prci_wrpll_pack(const struct wrpll_cfg *c) ++{ ++ u32 r = 0; ++ ++ r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT; ++ r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT; ++ r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT; ++ r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT; ++ ++ /* external feedback mode not supported */ ++ r |= PRCI_COREPLLCFG0_FSE_MASK; ++ ++ return r; ++} ++ ++/** ++ * __prci_wrpll_read_cfg() - read the WRPLL configuration from the PRCI ++ * @pd: PRCI context ++ * @pwd: PRCI WRPLL metadata ++ * ++ * Read the current configuration of the PLL identified by @pwd from ++ * the PRCI identified by @pd, and store it into the local configuration ++ * cache in @pwd. ++ * ++ * Context: Any context. Caller must prevent the records pointed to by ++ * @pd and @pwd from changing during execution. ++ */ ++static void __prci_wrpll_read_cfg(struct __prci_data *pd, ++ struct __prci_wrpll_data *pwd) ++{ ++ __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs)); ++} ++ ++/** ++ * __prci_wrpll_write_cfg() - write WRPLL configuration into the PRCI ++ * @pd: PRCI context ++ * @pwd: PRCI WRPLL metadata ++ * @c: WRPLL configuration record to write ++ * ++ * Write the WRPLL configuration described by @c into the WRPLL ++ * configuration register identified by @pwd in the PRCI instance ++ * described by @c. Make a cached copy of the WRPLL's current ++ * configuration so it can be used by other code. ++ * ++ * Context: Any context. Caller must prevent the records pointed to by ++ * @pd and @pwd from changing during execution. ++ */ ++static void __prci_wrpll_write_cfg(struct __prci_data *pd, ++ struct __prci_wrpll_data *pwd, ++ struct wrpll_cfg *c) ++{ ++ __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd); ++ ++ memcpy(&pwd->c, c, sizeof(*c)); ++} ++ ++/* ++ * Linux clock framework integration ++ * ++ * See the Linux clock framework documentation for more information on ++ * these functions. ++ */ ++ ++unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct __prci_clock *pc = clk_hw_to_prci_clock(hw); ++ struct __prci_wrpll_data *pwd = pc->pwd; ++ ++ return wrpll_calc_output_rate(&pwd->c, parent_rate); ++} ++ ++long sifive_prci_wrpll_round_rate(struct clk_hw *hw, ++ unsigned long rate, ++ unsigned long *parent_rate) ++{ ++ struct __prci_clock *pc = clk_hw_to_prci_clock(hw); ++ struct __prci_wrpll_data *pwd = pc->pwd; ++ struct wrpll_cfg c; ++ ++ memcpy(&c, &pwd->c, sizeof(c)); ++ ++ wrpll_configure_for_rate(&c, rate, *parent_rate); ++ ++ return wrpll_calc_output_rate(&c, *parent_rate); ++} ++ ++int sifive_prci_wrpll_set_rate(struct clk_hw *hw, ++ unsigned long rate, unsigned long parent_rate) ++{ ++ struct __prci_clock *pc = clk_hw_to_prci_clock(hw); ++ struct __prci_wrpll_data *pwd = pc->pwd; ++ struct __prci_data *pd = pc->pd; ++ int r; ++ ++ r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate); ++ if (r) ++ return r; ++ ++ if (pwd->enable_bypass) ++ pwd->enable_bypass(pd); ++ ++ __prci_wrpll_write_cfg(pd, pwd, &pwd->c); ++ ++ udelay(wrpll_calc_max_lock_us(&pwd->c)); ++ ++ if (pwd->disable_bypass) ++ pwd->disable_bypass(pd); ++ ++ return 0; ++} ++ ++/* TLCLKSEL clock integration */ ++ ++unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct __prci_clock *pc = clk_hw_to_prci_clock(hw); ++ struct __prci_data *pd = pc->pd; ++ u32 v; ++ u8 div; ++ ++ v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET); ++ v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK; ++ div = v ? 1 : 2; ++ ++ return div_u64(parent_rate, div); ++} ++ ++/* ++ * Core clock mux control ++ */ ++ ++/** ++ * sifive_prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK ++ * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg ++ * ++ * Switch the CORECLK mux to the HFCLK input source; return once complete. ++ * ++ * Context: Any context. Caller must prevent concurrent changes to the ++ * PRCI_CORECLKSEL_OFFSET register. ++ */ ++void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd) ++{ ++ u32 r; ++ ++ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); ++ r |= PRCI_CORECLKSEL_CORECLKSEL_MASK; ++ __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); ++ ++ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ ++} ++ ++/** ++ * sifive_prci_coreclksel_use_corepll() - switch the CORECLK mux to output ++ * COREPLL ++ * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg ++ * ++ * Switch the CORECLK mux to the COREPLL output clock; return once complete. ++ * ++ * Context: Any context. Caller must prevent concurrent changes to the ++ * PRCI_CORECLKSEL_OFFSET register. ++ */ ++void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd) ++{ ++ u32 r; ++ ++ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); ++ r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK; ++ __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); ++ ++ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ ++} ++ ++/** ++ * __prci_register_clocks() - register clock controls in the PRCI ++ * @dev: Linux struct device ++ * @pd: The pointer for PRCI per-device instance data ++ * @desc: The pointer for the information of clocks of each SoCs ++ * ++ * Register the list of clock controls described in __prci_init_clocks[] with ++ * the Linux clock framework. ++ * ++ * Return: 0 upon success or a negative error code upon failure. ++ */ ++static int __prci_register_clocks(struct device *dev, struct __prci_data *pd, ++ const struct prci_clk_desc *desc) ++{ ++ struct clk_init_data init = { }; ++ struct __prci_clock *pic; ++ int parent_count, i, r; ++ ++ parent_count = of_clk_get_parent_count(dev->of_node); ++ if (parent_count != EXPECTED_CLK_PARENT_COUNT) { ++ dev_err(dev, "expected only two parent clocks, found %d\n", ++ parent_count); ++ return -EINVAL; ++ } ++ ++ /* Register PLLs */ ++ for (i = 0; i < desc->num_clks; ++i) { ++ pic = &(desc->clks[i]); ++ ++ init.name = pic->name; ++ init.parent_names = &pic->parent_name; ++ init.num_parents = 1; ++ init.ops = pic->ops; ++ pic->hw.init = &init; ++ ++ pic->pd = pd; ++ ++ if (pic->pwd) ++ __prci_wrpll_read_cfg(pd, pic->pwd); ++ ++ r = devm_clk_hw_register(dev, &pic->hw); ++ if (r) { ++ dev_warn(dev, "Failed to register clock %s: %d\n", ++ init.name, r); ++ return r; ++ } ++ ++ r = clk_hw_register_clkdev(&pic->hw, pic->name, dev_name(dev)); ++ if (r) { ++ dev_warn(dev, "Failed to register clkdev for %s: %d\n", ++ init.name, r); ++ return r; ++ } ++ ++ pd->hw_clks.hws[i] = &pic->hw; ++ } ++ ++ pd->hw_clks.num = i; ++ ++ r = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, ++ &pd->hw_clks); ++ if (r) { ++ dev_err(dev, "could not add hw_provider: %d\n", r); ++ return r; ++ } ++ ++ return 0; ++} ++ ++/** ++ * sifive_prci_init() - initialize prci data and check parent count ++ * @pdev: platform device pointer for the prci ++ * ++ * Return: 0 upon success or a negative error code upon failure. ++ */ ++static int sifive_prci_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct resource *res; ++ struct __prci_data *pd; ++ const struct prci_clk_desc *desc; ++ int r; ++ ++ desc = of_device_get_match_data(&pdev->dev); ++ ++ pd = devm_kzalloc(dev, struct_size(pd, hw_clks.hws, desc->num_clks), GFP_KERNEL); ++ if (!pd) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ pd->va = devm_ioremap_resource(dev, res); ++ if (IS_ERR(pd->va)) ++ return PTR_ERR(pd->va); ++ ++ r = __prci_register_clocks(dev, pd, desc); ++ if (r) { ++ dev_err(dev, "could not register clocks: %d\n", r); ++ return r; ++ } ++ ++ dev_dbg(dev, "SiFive PRCI probed\n"); ++ ++ return 0; ++} ++ ++static const struct of_device_id sifive_prci_of_match[] = { ++ {.compatible = "sifive,fu540-c000-prci", .data = &prci_clk_fu540}, ++ {} ++}; ++ ++static struct platform_driver sifive_prci_driver = { ++ .driver = { ++ .name = "sifive-clk-prci", ++ .of_match_table = sifive_prci_of_match, ++ }, ++ .probe = sifive_prci_probe, ++}; ++ ++static int __init sifive_prci_init(void) ++{ ++ return platform_driver_register(&sifive_prci_driver); ++} ++core_initcall(sifive_prci_init); +diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h +new file mode 100644 +index 0000000000000..280df63b4b928 +--- /dev/null ++++ b/drivers/clk/sifive/sifive-prci.h +@@ -0,0 +1,201 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2018-2019 SiFive, Inc. ++ * Wesley Terpstra ++ * Paul Walmsley ++ * Zong Li ++ */ ++ ++#ifndef __SIFIVE_CLK_SIFIVE_PRCI_H ++#define __SIFIVE_CLK_SIFIVE_PRCI_H ++ ++#include ++#include ++#include ++ ++/* ++ * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: ++ * hfclk and rtcclk ++ */ ++#define EXPECTED_CLK_PARENT_COUNT 2 ++ ++/* ++ * Register offsets and bitmasks ++ */ ++ ++/* COREPLLCFG0 */ ++#define PRCI_COREPLLCFG0_OFFSET 0x4 ++#define PRCI_COREPLLCFG0_DIVR_SHIFT 0 ++#define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT) ++#define PRCI_COREPLLCFG0_DIVF_SHIFT 6 ++#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT) ++#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15 ++#define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT) ++#define PRCI_COREPLLCFG0_RANGE_SHIFT 18 ++#define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT) ++#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24 ++#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT) ++#define PRCI_COREPLLCFG0_FSE_SHIFT 25 ++#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT) ++#define PRCI_COREPLLCFG0_LOCK_SHIFT 31 ++#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT) ++ ++/* DDRPLLCFG0 */ ++#define PRCI_DDRPLLCFG0_OFFSET 0xc ++#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0 ++#define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT) ++#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6 ++#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT) ++#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15 ++#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT) ++#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18 ++#define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT) ++#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24 ++#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) ++#define PRCI_DDRPLLCFG0_FSE_SHIFT 25 ++#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT) ++#define PRCI_DDRPLLCFG0_LOCK_SHIFT 31 ++#define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT) ++ ++/* DDRPLLCFG1 */ ++#define PRCI_DDRPLLCFG1_OFFSET 0x10 ++#define PRCI_DDRPLLCFG1_CKE_SHIFT 24 ++#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) ++ ++/* GEMGXLPLLCFG0 */ ++#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c ++#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 ++#define PRCI_GEMGXLPLLCFG0_DIVR_MASK (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT) ++#define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6 ++#define PRCI_GEMGXLPLLCFG0_DIVF_MASK (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT) ++#define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15 ++#define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT) ++#define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18 ++#define PRCI_GEMGXLPLLCFG0_RANGE_MASK (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT) ++#define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24 ++#define PRCI_GEMGXLPLLCFG0_BYPASS_MASK (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT) ++#define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25 ++#define PRCI_GEMGXLPLLCFG0_FSE_MASK (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT) ++#define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31 ++#define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT) ++ ++/* GEMGXLPLLCFG1 */ ++#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 ++#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24 ++#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) ++ ++/* CORECLKSEL */ ++#define PRCI_CORECLKSEL_OFFSET 0x24 ++#define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0 ++#define PRCI_CORECLKSEL_CORECLKSEL_MASK \ ++ (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT) ++ ++/* DEVICESRESETREG */ ++#define PRCI_DEVICESRESETREG_OFFSET 0x28 ++#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0 ++#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \ ++ (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT) ++#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1 ++#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \ ++ (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT) ++#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2 ++#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \ ++ (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT) ++#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3 ++#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \ ++ (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT) ++#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5 ++#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \ ++ (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT) ++#define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT 6 ++#define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \ ++ (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT) ++ ++/* CLKMUXSTATUSREG */ ++#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c ++#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 ++#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \ ++ (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT) ++ ++/* ++ * Private structures ++ */ ++ ++/** ++ * struct __prci_data - per-device-instance data ++ * @va: base virtual address of the PRCI IP block ++ * @hw_clks: encapsulates struct clk_hw records ++ * ++ * PRCI per-device instance data ++ */ ++struct __prci_data { ++ void __iomem *va; ++ struct clk_hw_onecell_data hw_clks; ++}; ++ ++/** ++ * struct __prci_wrpll_data - WRPLL configuration and integration data ++ * @c: WRPLL current configuration record ++ * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL) ++ * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL) ++ * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address ++ * ++ * @enable_bypass and @disable_bypass are used for WRPLL instances ++ * that contain a separate external glitchless clock mux downstream ++ * from the PLL. The WRPLL internal bypass mux is not glitchless. ++ */ ++struct __prci_wrpll_data { ++ struct wrpll_cfg c; ++ void (*enable_bypass)(struct __prci_data *pd); ++ void (*disable_bypass)(struct __prci_data *pd); ++ u8 cfg0_offs; ++}; ++ ++/** ++ * struct __prci_clock - describes a clock device managed by PRCI ++ * @name: user-readable clock name string - should match the manual ++ * @parent_name: parent name for this clock ++ * @ops: struct clk_ops for the Linux clock framework to use for control ++ * @hw: Linux-private clock data ++ * @pwd: WRPLL-specific data, associated with this clock (if not NULL) ++ * @pd: PRCI-specific data associated with this clock (if not NULL) ++ * ++ * PRCI clock data. Used by the PRCI driver to register PRCI-provided ++ * clocks to the Linux clock infrastructure. ++ */ ++struct __prci_clock { ++ const char *name; ++ const char *parent_name; ++ const struct clk_ops *ops; ++ struct clk_hw hw; ++ struct __prci_wrpll_data *pwd; ++ struct __prci_data *pd; ++}; ++ ++#define clk_hw_to_prci_clock(pwd) container_of(pwd, struct __prci_clock, hw) ++ ++/* ++ * struct prci_clk_desc - describes the information of clocks of each SoCs ++ * @clks: point to a array of __prci_clock ++ * @num_clks: the number of element of clks ++ */ ++struct prci_clk_desc { ++ struct __prci_clock *clks; ++ size_t num_clks; ++}; ++ ++/* Core clock mux control */ ++void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd); ++void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd); ++ ++/* Linux clock framework integration */ ++long sifive_prci_wrpll_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *parent_rate); ++int sifive_prci_wrpll_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate); ++unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate); ++unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate); ++ ++#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */ +-- +2.43.0 + diff --git a/queue-5.10/drm-bridge-panel-fix-runtime-warning-on-panel-bridge.patch b/queue-5.10/drm-bridge-panel-fix-runtime-warning-on-panel-bridge.patch new file mode 100644 index 00000000000..8f964c3ceca --- /dev/null +++ b/queue-5.10/drm-bridge-panel-fix-runtime-warning-on-panel-bridge.patch @@ -0,0 +1,51 @@ +From 558b7128a1e938187dbd284e4c6fdfba1a35dd9f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 10 Jun 2024 11:27:39 +0100 +Subject: drm/bridge/panel: Fix runtime warning on panel bridge release + +From: Adam Miotk + +[ Upstream commit ce62600c4dbee8d43b02277669dd91785a9b81d9 ] + +Device managed panel bridge wrappers are created by calling to +drm_panel_bridge_add_typed() and registering a release handler for +clean-up when the device gets unbound. + +Since the memory for this bridge is also managed and linked to the panel +device, the release function should not try to free that memory. +Moreover, the call to devm_kfree() inside drm_panel_bridge_remove() will +fail in this case and emit a warning because the panel bridge resource +is no longer on the device resources list (it has been removed from +there before the call to release handlers). + +Fixes: 67022227ffb1 ("drm/bridge: Add a devm_ allocator for panel bridge.") +Signed-off-by: Adam Miotk +Signed-off-by: Maxime Ripard +Link: https://patchwork.freedesktop.org/patch/msgid/20240610102739.139852-1-adam.miotk@arm.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/panel.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c +index c916f4b8907ef..35a6d9c4e081e 100644 +--- a/drivers/gpu/drm/bridge/panel.c ++++ b/drivers/gpu/drm/bridge/panel.c +@@ -252,9 +252,12 @@ EXPORT_SYMBOL(drm_panel_bridge_remove); + + static void devm_drm_panel_bridge_release(struct device *dev, void *res) + { +- struct drm_bridge **bridge = res; ++ struct drm_bridge *bridge = *(struct drm_bridge **)res; + +- drm_panel_bridge_remove(*bridge); ++ if (!bridge) ++ return; ++ ++ drm_bridge_remove(bridge); + } + + /** +-- +2.43.0 + diff --git a/queue-5.10/drm-komeda-check-for-error-valued-pointer.patch b/queue-5.10/drm-komeda-check-for-error-valued-pointer.patch new file mode 100644 index 00000000000..9c37fe0165d --- /dev/null +++ b/queue-5.10/drm-komeda-check-for-error-valued-pointer.patch @@ -0,0 +1,37 @@ +From f9562c475b603a4cfdc4ed72c2c706dde4fbe55b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 10 Jun 2024 11:20:56 +0100 +Subject: drm/komeda: check for error-valued pointer + +From: Amjad Ouled-Ameur + +[ Upstream commit b880018edd3a577e50366338194dee9b899947e0 ] + +komeda_pipeline_get_state() may return an error-valued pointer, thus +check the pointer for negative or null value before dereferencing. + +Fixes: 502932a03fce ("drm/komeda: Add the initial scaler support for CORE") +Signed-off-by: Amjad Ouled-Ameur +Signed-off-by: Maxime Ripard +Link: https://patchwork.freedesktop.org/patch/msgid/20240610102056.40406-1-amjad.ouled-ameur@arm.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +index 1e922703e26b2..7cc891c091f84 100644 +--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c ++++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +@@ -259,7 +259,7 @@ komeda_component_get_avail_scaler(struct komeda_component *c, + u32 avail_scalers; + + pipe_st = komeda_pipeline_get_state(c->pipeline, state); +- if (!pipe_st) ++ if (IS_ERR_OR_NULL(pipe_st)) + return NULL; + + avail_scalers = (pipe_st->active_comps & KOMEDA_PIPELINE_SCALERS) ^ +-- +2.43.0 + diff --git a/queue-5.10/drm-vmwgfx-3d-disabled-should-not-effect-stdu-memory.patch b/queue-5.10/drm-vmwgfx-3d-disabled-should-not-effect-stdu-memory.patch new file mode 100644 index 00000000000..7a63f64d30e --- /dev/null +++ b/queue-5.10/drm-vmwgfx-3d-disabled-should-not-effect-stdu-memory.patch @@ -0,0 +1,45 @@ +From b6c55ae3cd23b7edac198258e3fcb40f3d8aa46b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 May 2024 13:47:18 -0500 +Subject: drm/vmwgfx: 3D disabled should not effect STDU memory limits + +From: Ian Forbes + +[ Upstream commit fb5e19d2dd03eb995ccd468d599b2337f7f66555 ] + +This limit became a hard cap starting with the change referenced below. +Surface creation on the device will fail if the requested size is larger +than this limit so altering the value arbitrarily will expose modes that +are too large for the device's hard limits. + +Fixes: 7ebb47c9f9ab ("drm/vmwgfx: Read new register for GB memory when available") + +Signed-off-by: Ian Forbes +Signed-off-by: Zack Rusin +Link: https://patchwork.freedesktop.org/patch/msgid/20240521184720.767-3-ian.forbes@broadcom.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 7 ------- + 1 file changed, 7 deletions(-) + +diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +index bdb7a5e965601..25a9c72cca806 100644 +--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ++++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +@@ -752,13 +752,6 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) + vmw_read(dev_priv, + SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); + +- /* +- * Workaround for low memory 2D VMs to compensate for the +- * allocation taken by fbdev +- */ +- if (!(dev_priv->capabilities & SVGA_CAP_3D)) +- mem_size *= 3; +- + dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; + dev_priv->prim_bb_mem = + vmw_read(dev_priv, +-- +2.43.0 + diff --git a/queue-5.10/geneve-fix-incorrect-inner-network-header-offset-whe.patch b/queue-5.10/geneve-fix-incorrect-inner-network-header-offset-whe.patch new file mode 100644 index 00000000000..15272cf7df3 --- /dev/null +++ b/queue-5.10/geneve-fix-incorrect-inner-network-header-offset-whe.patch @@ -0,0 +1,106 @@ +From 0adbbc66f9269b24f623e758d18c7d75ec444aaf Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 6 Jun 2024 23:32:48 +0300 +Subject: geneve: Fix incorrect inner network header offset when + innerprotoinherit is set + +From: Gal Pressman + +[ Upstream commit c6ae073f5903f6c6439d0ac855836a4da5c0a701 ] + +When innerprotoinherit is set, the tunneled packets do not have an inner +Ethernet header. +Change 'maclen' to not always assume the header length is ETH_HLEN, as +there might not be a MAC header. + +This resolves issues with drivers (e.g. mlx5, in +mlx5e_tx_tunnel_accel()) who rely on the skb inner network header offset +to be correct, and use it for TX offloads. + +Fixes: d8a6213d70ac ("geneve: fix header validation in geneve[6]_xmit_skb") +Signed-off-by: Gal Pressman +Signed-off-by: Tariq Toukan +Reviewed-by: Wojciech Drewek +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/geneve.c | 10 ++++++---- + include/net/ip_tunnels.h | 5 +++-- + 2 files changed, 9 insertions(+), 6 deletions(-) + +diff --git a/drivers/net/geneve.c b/drivers/net/geneve.c +index c4cc539fe3155..b3e998fa14897 100644 +--- a/drivers/net/geneve.c ++++ b/drivers/net/geneve.c +@@ -918,6 +918,7 @@ static int geneve_xmit_skb(struct sk_buff *skb, struct net_device *dev, + struct geneve_dev *geneve, + const struct ip_tunnel_info *info) + { ++ bool inner_proto_inherit = geneve->cfg.inner_proto_inherit; + bool xnet = !net_eq(geneve->net, dev_net(geneve->dev)); + struct geneve_sock *gs4 = rcu_dereference(geneve->sock4); + const struct ip_tunnel_key *key = &info->key; +@@ -929,7 +930,7 @@ static int geneve_xmit_skb(struct sk_buff *skb, struct net_device *dev, + __be16 sport; + int err; + +- if (!skb_vlan_inet_prepare(skb)) ++ if (!skb_vlan_inet_prepare(skb, inner_proto_inherit)) + return -EINVAL; + + sport = udp_flow_src_port(geneve->net, skb, 1, USHRT_MAX, true); +@@ -1002,7 +1003,7 @@ static int geneve_xmit_skb(struct sk_buff *skb, struct net_device *dev, + } + + err = geneve_build_skb(&rt->dst, skb, info, xnet, sizeof(struct iphdr), +- geneve->cfg.inner_proto_inherit); ++ inner_proto_inherit); + if (unlikely(err)) + return err; + +@@ -1018,6 +1019,7 @@ static int geneve6_xmit_skb(struct sk_buff *skb, struct net_device *dev, + struct geneve_dev *geneve, + const struct ip_tunnel_info *info) + { ++ bool inner_proto_inherit = geneve->cfg.inner_proto_inherit; + bool xnet = !net_eq(geneve->net, dev_net(geneve->dev)); + struct geneve_sock *gs6 = rcu_dereference(geneve->sock6); + const struct ip_tunnel_key *key = &info->key; +@@ -1027,7 +1029,7 @@ static int geneve6_xmit_skb(struct sk_buff *skb, struct net_device *dev, + __be16 sport; + int err; + +- if (!skb_vlan_inet_prepare(skb)) ++ if (!skb_vlan_inet_prepare(skb, inner_proto_inherit)) + return -EINVAL; + + sport = udp_flow_src_port(geneve->net, skb, 1, USHRT_MAX, true); +@@ -1082,7 +1084,7 @@ static int geneve6_xmit_skb(struct sk_buff *skb, struct net_device *dev, + ttl = ttl ? : ip6_dst_hoplimit(dst); + } + err = geneve_build_skb(dst, skb, info, xnet, sizeof(struct ipv6hdr), +- geneve->cfg.inner_proto_inherit); ++ inner_proto_inherit); + if (unlikely(err)) + return err; + +diff --git a/include/net/ip_tunnels.h b/include/net/ip_tunnels.h +index 1f016af0622bd..9c96c02f45b13 100644 +--- a/include/net/ip_tunnels.h ++++ b/include/net/ip_tunnels.h +@@ -335,9 +335,10 @@ static inline bool pskb_inet_may_pull(struct sk_buff *skb) + + /* Variant of pskb_inet_may_pull(). + */ +-static inline bool skb_vlan_inet_prepare(struct sk_buff *skb) ++static inline bool skb_vlan_inet_prepare(struct sk_buff *skb, ++ bool inner_proto_inherit) + { +- int nhlen = 0, maclen = ETH_HLEN; ++ int nhlen = 0, maclen = inner_proto_inherit ? 0 : ETH_HLEN; + __be16 type = skb->protocol; + + /* Essentially this is skb_protocol(skb, true) +-- +2.43.0 + diff --git a/queue-5.10/genirq-allow-the-pm-device-to-originate-from-irq-dom.patch b/queue-5.10/genirq-allow-the-pm-device-to-originate-from-irq-dom.patch new file mode 100644 index 00000000000..5fe6a192f12 --- /dev/null +++ b/queue-5.10/genirq-allow-the-pm-device-to-originate-from-irq-dom.patch @@ -0,0 +1,122 @@ +From 83cbf3efed47640d7e1875b000b9d39cac5a47fe Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 1 Feb 2022 12:02:59 +0000 +Subject: genirq: Allow the PM device to originate from irq domain + +From: Marc Zyngier + +[ Upstream commit 1f8863bfb5ca500ea1c7669b16b1931ba27fce20 ] + +As a preparation to moving the reference to the device used for +runtime power management, add a new 'dev' field to the irqdomain +structure for that exact purpose. + +The irq_chip_pm_{get,put}() helpers are made aware of the dual +location via a new private helper. + +No functional change intended. + +Signed-off-by: Marc Zyngier +Reviewed-by: Geert Uytterhoeven +Tested-by: Geert Uytterhoeven +Tested-by: Tony Lindgren +Acked-by: Bartosz Golaszewski +Link: https://lore.kernel.org/r/20220201120310.878267-2-maz@kernel.org +Stable-dep-of: 08af509efdf8 ("gpio: tqmx86: store IRQ trigger type and unmask status separately") +Signed-off-by: Sasha Levin +--- + include/linux/irqdomain.h | 10 ++++++++++ + kernel/irq/chip.c | 23 ++++++++++++++++++----- + 2 files changed, 28 insertions(+), 5 deletions(-) + +diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h +index 9b9743f7538c4..60f53eadfa422 100644 +--- a/include/linux/irqdomain.h ++++ b/include/linux/irqdomain.h +@@ -149,6 +149,8 @@ struct irq_domain_chip_generic; + * @gc: Pointer to a list of generic chips. There is a helper function for + * setting up one or more generic chips for interrupt controllers + * drivers using the generic chip library which uses this pointer. ++ * @dev: Pointer to a device that the domain represent, and that will be ++ * used for power management purposes. + * @parent: Pointer to parent irq_domain to support hierarchy irq_domains + * @debugfs_file: dentry for the domain debugfs file + * +@@ -171,6 +173,7 @@ struct irq_domain { + struct fwnode_handle *fwnode; + enum irq_domain_bus_token bus_token; + struct irq_domain_chip_generic *gc; ++ struct device *dev; + #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY + struct irq_domain *parent; + #endif +@@ -227,6 +230,13 @@ static inline struct device_node *irq_domain_get_of_node(struct irq_domain *d) + return to_of_node(d->fwnode); + } + ++static inline void irq_domain_set_pm_device(struct irq_domain *d, ++ struct device *dev) ++{ ++ if (d) ++ d->dev = dev; ++} ++ + #ifdef CONFIG_IRQ_DOMAIN + struct fwnode_handle *__irq_domain_alloc_fwnode(unsigned int type, int id, + const char *name, phys_addr_t *pa); +diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c +index e7d284261d450..b8aa9e22105f9 100644 +--- a/kernel/irq/chip.c ++++ b/kernel/irq/chip.c +@@ -1586,6 +1586,17 @@ int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) + return 0; + } + ++static struct device *irq_get_parent_device(struct irq_data *data) ++{ ++ if (data->chip->parent_device) ++ return data->chip->parent_device; ++ ++ if (data->domain) ++ return data->domain->dev; ++ ++ return NULL; ++} ++ + /** + * irq_chip_pm_get - Enable power for an IRQ chip + * @data: Pointer to interrupt specific data +@@ -1595,12 +1606,13 @@ int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) + */ + int irq_chip_pm_get(struct irq_data *data) + { ++ struct device *dev = irq_get_parent_device(data); + int retval; + +- if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) { +- retval = pm_runtime_get_sync(data->chip->parent_device); ++ if (IS_ENABLED(CONFIG_PM) && dev) { ++ retval = pm_runtime_get_sync(dev); + if (retval < 0) { +- pm_runtime_put_noidle(data->chip->parent_device); ++ pm_runtime_put_noidle(dev); + return retval; + } + } +@@ -1618,10 +1630,11 @@ int irq_chip_pm_get(struct irq_data *data) + */ + int irq_chip_pm_put(struct irq_data *data) + { ++ struct device *dev = irq_get_parent_device(data); + int retval = 0; + +- if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) +- retval = pm_runtime_put(data->chip->parent_device); ++ if (IS_ENABLED(CONFIG_PM) && dev) ++ retval = pm_runtime_put(dev); + + return (retval < 0) ? retval : 0; + } +-- +2.43.0 + diff --git a/queue-5.10/gpio-add-helpers-to-ease-the-transition-towards-immu.patch b/queue-5.10/gpio-add-helpers-to-ease-the-transition-towards-immu.patch new file mode 100644 index 00000000000..deac8af53af --- /dev/null +++ b/queue-5.10/gpio-add-helpers-to-ease-the-transition-towards-immu.patch @@ -0,0 +1,54 @@ +From d80c55be2678b053ad6251eb013a41c30f4da3c9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Apr 2022 15:18:39 +0100 +Subject: gpio: Add helpers to ease the transition towards immutable irq_chip + +From: Marc Zyngier + +[ Upstream commit 36b78aae4bfee749bbde73be570796bfd0f56bec ] + +Add a couple of new helpers to make it slightly simpler to convert +drivers to immutable irq_chip structures: + +- GPIOCHIP_IRQ_RESOURCE_HELPERS populates the irq_chip structure + with the resource management callbacks + +- gpio_irq_chip_set_chip() populates the gpio_irq_chip.chip + structure, avoiding the proliferation of ugly casts + +Reviewed-by: Andy Shevchenko +Reviewed-by: Bartosz Golaszewski +Signed-off-by: Marc Zyngier +Link: https://lore.kernel.org/r/20220419141846.598305-4-maz@kernel.org +Stable-dep-of: 08af509efdf8 ("gpio: tqmx86: store IRQ trigger type and unmask status separately") +Signed-off-by: Sasha Levin +--- + include/linux/gpio/driver.h | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h +index 38df53b541d53..897fc150552a2 100644 +--- a/include/linux/gpio/driver.h ++++ b/include/linux/gpio/driver.h +@@ -595,6 +595,18 @@ void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset); + int gpiochip_irq_reqres(struct irq_data *data); + void gpiochip_irq_relres(struct irq_data *data); + ++/* Paste this in your irq_chip structure */ ++#define GPIOCHIP_IRQ_RESOURCE_HELPERS \ ++ .irq_request_resources = gpiochip_irq_reqres, \ ++ .irq_release_resources = gpiochip_irq_relres ++ ++static inline void gpio_irq_chip_set_chip(struct gpio_irq_chip *girq, ++ const struct irq_chip *chip) ++{ ++ /* Yes, dropping const is ugly, but it isn't like we have a choice */ ++ girq->chip = (struct irq_chip *)chip; ++} ++ + /* Line status inquiry for drivers */ + bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset); + bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset); +-- +2.43.0 + diff --git a/queue-5.10/gpio-don-t-fiddle-with-irqchips-marked-as-immutable.patch b/queue-5.10/gpio-don-t-fiddle-with-irqchips-marked-as-immutable.patch new file mode 100644 index 00000000000..8e6776b70d4 --- /dev/null +++ b/queue-5.10/gpio-don-t-fiddle-with-irqchips-marked-as-immutable.patch @@ -0,0 +1,89 @@ +From bf6d3c4ecb105ceea189578556cd6a6523c8c332 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Apr 2022 15:18:37 +0100 +Subject: gpio: Don't fiddle with irqchips marked as immutable + +From: Marc Zyngier + +[ Upstream commit 6c846d026d490b2383d395bc8e7b06336219667b ] + +In order to move away from gpiolib messing with the internals of +unsuspecting irqchips, add a flag by which irqchips advertise +that they are not to be messed with, and do solemnly swear that +they correctly call into the gpiolib helpers when required. + +Also nudge the users into converting their drivers to the +new model. + +Reviewed-by: Andy Shevchenko +Reviewed-by: Bartosz Golaszewski +Signed-off-by: Marc Zyngier +Link: https://lore.kernel.org/r/20220419141846.598305-2-maz@kernel.org +Stable-dep-of: 08af509efdf8 ("gpio: tqmx86: store IRQ trigger type and unmask status separately") +Signed-off-by: Sasha Levin +--- + drivers/gpio/gpiolib.c | 7 ++++++- + include/linux/irq.h | 2 ++ + kernel/irq/debugfs.c | 1 + + 3 files changed, 9 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c +index 374bb9f432660..dcb9b95755cc4 100644 +--- a/drivers/gpio/gpiolib.c ++++ b/drivers/gpio/gpiolib.c +@@ -1491,6 +1491,11 @@ static void gpiochip_set_irq_hooks(struct gpio_chip *gc) + { + struct irq_chip *irqchip = gc->irq.chip; + ++ if (irqchip->flags & IRQCHIP_IMMUTABLE) ++ return; ++ ++ chip_warn(gc, "not an immutable chip, please consider fixing it!\n"); ++ + if (!irqchip->irq_request_resources && + !irqchip->irq_release_resources) { + irqchip->irq_request_resources = gpiochip_irq_reqres; +@@ -1667,7 +1672,7 @@ static void gpiochip_irqchip_remove(struct gpio_chip *gc) + irq_domain_remove(gc->irq.domain); + } + +- if (irqchip) { ++ if (irqchip && !(irqchip->flags & IRQCHIP_IMMUTABLE)) { + if (irqchip->irq_request_resources == gpiochip_irq_reqres) { + irqchip->irq_request_resources = NULL; + irqchip->irq_release_resources = NULL; +diff --git a/include/linux/irq.h b/include/linux/irq.h +index b89a8ac83d1bc..da4cd9fb3e5f3 100644 +--- a/include/linux/irq.h ++++ b/include/linux/irq.h +@@ -568,6 +568,7 @@ struct irq_chip { + * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs + * in the suspend path if they are in disabled state + * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup ++ * IRQCHIP_IMMUTABLE: Don't ever change anything in this chip + */ + enum { + IRQCHIP_SET_TYPE_MASKED = (1 << 0), +@@ -581,6 +582,7 @@ enum { + IRQCHIP_SUPPORTS_NMI = (1 << 8), + IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9), + IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10), ++ IRQCHIP_IMMUTABLE = (1 << 11), + }; + + #include +diff --git a/kernel/irq/debugfs.c b/kernel/irq/debugfs.c +index e4cff358b437e..7ff52d94b42c0 100644 +--- a/kernel/irq/debugfs.c ++++ b/kernel/irq/debugfs.c +@@ -58,6 +58,7 @@ static const struct irq_bit_descr irqchip_flags[] = { + BIT_MASK_DESCR(IRQCHIP_SUPPORTS_LEVEL_MSI), + BIT_MASK_DESCR(IRQCHIP_SUPPORTS_NMI), + BIT_MASK_DESCR(IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND), ++ BIT_MASK_DESCR(IRQCHIP_IMMUTABLE), + }; + + static void +-- +2.43.0 + diff --git a/queue-5.10/gpio-expose-the-gpiochip_irq_re-ql-res-helpers.patch b/queue-5.10/gpio-expose-the-gpiochip_irq_re-ql-res-helpers.patch new file mode 100644 index 00000000000..a413c934cb0 --- /dev/null +++ b/queue-5.10/gpio-expose-the-gpiochip_irq_re-ql-res-helpers.patch @@ -0,0 +1,70 @@ +From 909ab961748325ace965f8b2ed014861534a68cf Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Apr 2022 15:18:38 +0100 +Subject: gpio: Expose the gpiochip_irq_re[ql]res helpers + +From: Marc Zyngier + +[ Upstream commit 704f08753b6dcd0e08c1953af0b2c7f3fac87111 ] + +The GPIO subsystem has a couple of internal helpers to manage +resources on behalf of the irqchip. Expose them so that GPIO +drivers can use them directly. + +Reviewed-by: Andy Shevchenko +Reviewed-by: Bartosz Golaszewski +Signed-off-by: Marc Zyngier +Link: https://lore.kernel.org/r/20220419141846.598305-3-maz@kernel.org +Stable-dep-of: 08af509efdf8 ("gpio: tqmx86: store IRQ trigger type and unmask status separately") +Signed-off-by: Sasha Levin +--- + drivers/gpio/gpiolib.c | 6 ++++-- + include/linux/gpio/driver.h | 4 ++++ + 2 files changed, 8 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c +index dcb9b95755cc4..cfbf9dc85e365 100644 +--- a/drivers/gpio/gpiolib.c ++++ b/drivers/gpio/gpiolib.c +@@ -1439,19 +1439,21 @@ static int gpiochip_to_irq(struct gpio_chip *gc, unsigned offset) + return irq_create_mapping(domain, offset); + } + +-static int gpiochip_irq_reqres(struct irq_data *d) ++int gpiochip_irq_reqres(struct irq_data *d) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + return gpiochip_reqres_irq(gc, d->hwirq); + } ++EXPORT_SYMBOL(gpiochip_irq_reqres); + +-static void gpiochip_irq_relres(struct irq_data *d) ++void gpiochip_irq_relres(struct irq_data *d) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + gpiochip_relres_irq(gc, d->hwirq); + } ++EXPORT_SYMBOL(gpiochip_irq_relres); + + static void gpiochip_irq_mask(struct irq_data *d) + { +diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h +index 64c93a36a3a92..38df53b541d53 100644 +--- a/include/linux/gpio/driver.h ++++ b/include/linux/gpio/driver.h +@@ -591,6 +591,10 @@ void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset); + void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset); + void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset); + ++/* irq_data versions of the above */ ++int gpiochip_irq_reqres(struct irq_data *data); ++void gpiochip_irq_relres(struct irq_data *data); ++ + /* Line status inquiry for drivers */ + bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset); + bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset); +-- +2.43.0 + diff --git a/queue-5.10/gpio-tpmx86-move-pm-device-over-to-irq-domain.patch b/queue-5.10/gpio-tpmx86-move-pm-device-over-to-irq-domain.patch new file mode 100644 index 00000000000..306fe8d9dfc --- /dev/null +++ b/queue-5.10/gpio-tpmx86-move-pm-device-over-to-irq-domain.patch @@ -0,0 +1,44 @@ +From b2c6a4ea45397a74a3666d6acfc2fa979dea6e3f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 1 Feb 2022 12:03:07 +0000 +Subject: gpio: tpmx86: Move PM device over to irq domain + +From: Marc Zyngier + +[ Upstream commit 924610607f191bee4379bc3775b0fd025ad7e922 ] + +Move the reference to the device over to the irq domain. + +Signed-off-by: Marc Zyngier +Acked-by: Bartosz Golaszewski +Link: https://lore.kernel.org/r/20220201120310.878267-10-maz@kernel.org +Stable-dep-of: 08af509efdf8 ("gpio: tqmx86: store IRQ trigger type and unmask status separately") +Signed-off-by: Sasha Levin +--- + drivers/gpio/gpio-tqmx86.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c +index 3e7270e122bf1..e8360921ee23a 100644 +--- a/drivers/gpio/gpio-tqmx86.c ++++ b/drivers/gpio/gpio-tqmx86.c +@@ -285,7 +285,6 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) + u8 irq_status; + + irq_chip->name = chip->label; +- irq_chip->parent_device = &pdev->dev; + irq_chip->irq_mask = tqmx86_gpio_irq_mask; + irq_chip->irq_unmask = tqmx86_gpio_irq_unmask; + irq_chip->irq_set_type = tqmx86_gpio_irq_set_type; +@@ -320,6 +319,8 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) + goto out_pm_dis; + } + ++ irq_domain_set_pm_device(girq->domain, dev); ++ + dev_info(dev, "GPIO functionality initialized with %d pins\n", + chip->ngpio); + +-- +2.43.0 + diff --git a/queue-5.10/gpio-tqmx86-convert-to-immutable-irq_chip.patch b/queue-5.10/gpio-tqmx86-convert-to-immutable-irq_chip.patch new file mode 100644 index 00000000000..54f3d89d464 --- /dev/null +++ b/queue-5.10/gpio-tqmx86-convert-to-immutable-irq_chip.patch @@ -0,0 +1,108 @@ +From 373d1c7067ad2aad97d5174ed0ed8feb2b6d342a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Mar 2023 10:55:12 +0100 +Subject: gpio: tqmx86: Convert to immutable irq_chip + +From: Linus Walleij + +[ Upstream commit 8e43827b6ae727a745ce7a8cc19184b28905a965 ] + +Convert the driver to immutable irq-chip with a bit of +intuition. + +Cc: Marc Zyngier +Signed-off-by: Linus Walleij +Reviewed-by: Marc Zyngier +Signed-off-by: Bartosz Golaszewski +Stable-dep-of: 08af509efdf8 ("gpio: tqmx86: store IRQ trigger type and unmask status separately") +Signed-off-by: Sasha Levin +--- + drivers/gpio/gpio-tqmx86.c | 28 ++++++++++++++++++++-------- + 1 file changed, 20 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c +index e8360921ee23a..d58fd82b71a8d 100644 +--- a/drivers/gpio/gpio-tqmx86.c ++++ b/drivers/gpio/gpio-tqmx86.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + + #define TQMX86_NGPIO 8 +@@ -35,7 +36,6 @@ + + struct tqmx86_gpio_data { + struct gpio_chip chip; +- struct irq_chip irq_chip; + void __iomem *io_base; + int irq; + raw_spinlock_t spinlock; +@@ -119,6 +119,7 @@ static void tqmx86_gpio_irq_mask(struct irq_data *data) + gpiic &= ~mask; + tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); + raw_spin_unlock_irqrestore(&gpio->spinlock, flags); ++ gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(data)); + } + + static void tqmx86_gpio_irq_unmask(struct irq_data *data) +@@ -131,6 +132,7 @@ static void tqmx86_gpio_irq_unmask(struct irq_data *data) + + mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS); + ++ gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(data)); + raw_spin_lock_irqsave(&gpio->spinlock, flags); + gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); + gpiic &= ~mask; +@@ -225,6 +227,22 @@ static void tqmx86_init_irq_valid_mask(struct gpio_chip *chip, + clear_bit(3, valid_mask); + } + ++static void tqmx86_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p) ++{ ++ struct gpio_chip *gc = irq_data_get_irq_chip_data(d); ++ ++ seq_printf(p, gc->label); ++} ++ ++static const struct irq_chip tqmx86_gpio_irq_chip = { ++ .irq_mask = tqmx86_gpio_irq_mask, ++ .irq_unmask = tqmx86_gpio_irq_unmask, ++ .irq_set_type = tqmx86_gpio_irq_set_type, ++ .irq_print_chip = tqmx86_gpio_irq_print_chip, ++ .flags = IRQCHIP_IMMUTABLE, ++ GPIOCHIP_IRQ_RESOURCE_HELPERS, ++}; ++ + static int tqmx86_gpio_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; +@@ -281,14 +299,8 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) + pm_runtime_enable(&pdev->dev); + + if (irq > 0) { +- struct irq_chip *irq_chip = &gpio->irq_chip; + u8 irq_status; + +- irq_chip->name = chip->label; +- irq_chip->irq_mask = tqmx86_gpio_irq_mask; +- irq_chip->irq_unmask = tqmx86_gpio_irq_unmask; +- irq_chip->irq_set_type = tqmx86_gpio_irq_set_type; +- + /* Mask all interrupts */ + tqmx86_gpio_write(gpio, 0, TQMX86_GPIIC); + +@@ -297,7 +309,7 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) + tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS); + + girq = &chip->irq; +- girq->chip = irq_chip; ++ gpio_irq_chip_set_chip(girq, &tqmx86_gpio_irq_chip); + girq->parent_handler = tqmx86_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, +-- +2.43.0 + diff --git a/queue-5.10/gpio-tqmx86-fix-typo-in-kconfig-label.patch b/queue-5.10/gpio-tqmx86-fix-typo-in-kconfig-label.patch new file mode 100644 index 00000000000..4b8178d4f37 --- /dev/null +++ b/queue-5.10/gpio-tqmx86-fix-typo-in-kconfig-label.patch @@ -0,0 +1,38 @@ +From e657a1ee081bb70d87666cace4bb4ffe95b51fdc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 30 May 2024 12:19:59 +0200 +Subject: gpio: tqmx86: fix typo in Kconfig label + +From: Gregor Herburger + +[ Upstream commit 8c219e52ca4d9a67cd6a7074e91bf29b55edc075 ] + +Fix description for GPIO_TQMX86 from QTMX86 to TQMx86. + +Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") +Signed-off-by: Gregor Herburger +Signed-off-by: Matthias Schiffer +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/e0e38c9944ad6d281d9a662a45d289b88edc808e.1717063994.git.matthias.schiffer@ew.tq-group.com +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Sasha Levin +--- + drivers/gpio/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig +index 39f3e13664099..b7811dbe0ec28 100644 +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -1335,7 +1335,7 @@ config GPIO_TPS68470 + drivers are loaded. + + config GPIO_TQMX86 +- tristate "TQ-Systems QTMX86 GPIO" ++ tristate "TQ-Systems TQMx86 GPIO" + depends on MFD_TQMX86 || COMPILE_TEST + depends on HAS_IOPORT_MAP + select GPIOLIB_IRQCHIP +-- +2.43.0 + diff --git a/queue-5.10/gpio-tqmx86-introduce-shadow-register-for-gpio-outpu.patch b/queue-5.10/gpio-tqmx86-introduce-shadow-register-for-gpio-outpu.patch new file mode 100644 index 00000000000..44226b7cb5d --- /dev/null +++ b/queue-5.10/gpio-tqmx86-introduce-shadow-register-for-gpio-outpu.patch @@ -0,0 +1,89 @@ +From 5586ea72d9ac9a79f4eae2ffebb54e024ba1eee4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 30 May 2024 12:20:00 +0200 +Subject: gpio: tqmx86: introduce shadow register for GPIO output value + +From: Matthias Schiffer + +[ Upstream commit 9d6a811b522ba558bcb4ec01d12e72a0af8e9f6e ] + +The TQMx86 GPIO controller uses the same register address for input and +output data. Reading the register will always return current inputs +rather than the previously set outputs (regardless of the current +direction setting). Therefore, using a RMW pattern does not make sense +when setting output values. Instead, the previously set output register +value needs to be stored as a shadow register. + +As there is no reliable way to get the current output values from the +hardware, also initialize all channels to 0, to ensure that stored and +actual output values match. This should usually not have any effect in +practise, as the TQMx86 UEFI sets all outputs to 0 during boot. + +Also prepare for extension of the driver to more than 8 GPIOs by using +DECLARE_BITMAP. + +Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") +Signed-off-by: Matthias Schiffer +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/d0555933becd45fa92a85675d26e4d59343ddc01.1717063994.git.matthias.schiffer@ew.tq-group.com +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Sasha Levin +--- + drivers/gpio/gpio-tqmx86.c | 18 +++++++++++------- + 1 file changed, 11 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c +index 670cbd0435e3c..3e7270e122bf1 100644 +--- a/drivers/gpio/gpio-tqmx86.c ++++ b/drivers/gpio/gpio-tqmx86.c +@@ -6,6 +6,7 @@ + * Vadim V.Vlasov + */ + ++#include + #include + #include + #include +@@ -38,6 +39,7 @@ struct tqmx86_gpio_data { + void __iomem *io_base; + int irq; + raw_spinlock_t spinlock; ++ DECLARE_BITMAP(output, TQMX86_NGPIO); + u8 irq_type[TQMX86_NGPI]; + }; + +@@ -64,15 +66,10 @@ static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset, + { + struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); + unsigned long flags; +- u8 val; + + raw_spin_lock_irqsave(&gpio->spinlock, flags); +- val = tqmx86_gpio_read(gpio, TQMX86_GPIOD); +- if (value) +- val |= BIT(offset); +- else +- val &= ~BIT(offset); +- tqmx86_gpio_write(gpio, val, TQMX86_GPIOD); ++ __assign_bit(offset, gpio->output, value); ++ tqmx86_gpio_write(gpio, bitmap_get_value8(gpio->output, 0), TQMX86_GPIOD); + raw_spin_unlock_irqrestore(&gpio->spinlock, flags); + } + +@@ -261,6 +258,13 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) + + tqmx86_gpio_write(gpio, (u8)~TQMX86_DIR_INPUT_MASK, TQMX86_GPIODD); + ++ /* ++ * Reading the previous output state is not possible with TQMx86 hardware. ++ * Initialize all outputs to 0 to have a defined state that matches the ++ * shadow register. ++ */ ++ tqmx86_gpio_write(gpio, 0, TQMX86_GPIOD); ++ + chip = &gpio->chip; + chip->label = "gpio-tqmx86"; + chip->owner = THIS_MODULE; +-- +2.43.0 + diff --git a/queue-5.10/gpio-tqmx86-remove-unneeded-call-to-platform_set_drv.patch b/queue-5.10/gpio-tqmx86-remove-unneeded-call-to-platform_set_drv.patch new file mode 100644 index 00000000000..25a2b6e6c24 --- /dev/null +++ b/queue-5.10/gpio-tqmx86-remove-unneeded-call-to-platform_set_drv.patch @@ -0,0 +1,40 @@ +From 622b0df4f077bd9b3025e16edcb7df05ba577123 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 1 Aug 2023 23:38:39 +0300 +Subject: gpio: tqmx86: remove unneeded call to platform_set_drvdata() + +From: Andrei Coardos + +[ Upstream commit 0a5e9306b812fe3517548fab92b3d3d6ce7576e5 ] + +This function call was found to be unnecessary as there is no equivalent +platform_get_drvdata() call to access the private data of the driver. Also, +the private data is defined in this driver, so there is no risk of it being +accessed outside of this driver file. + +Reviewed-by: Alexandru Ardelean +Signed-off-by: Andrei Coardos +Reviewed-by: Andy Shevchenko +Signed-off-by: Bartosz Golaszewski +Stable-dep-of: 9d6a811b522b ("gpio: tqmx86: introduce shadow register for GPIO output value") +Signed-off-by: Sasha Levin +--- + drivers/gpio/gpio-tqmx86.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c +index 0f5d17f343f1e..670cbd0435e3c 100644 +--- a/drivers/gpio/gpio-tqmx86.c ++++ b/drivers/gpio/gpio-tqmx86.c +@@ -261,8 +261,6 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) + + tqmx86_gpio_write(gpio, (u8)~TQMX86_DIR_INPUT_MASK, TQMX86_GPIODD); + +- platform_set_drvdata(pdev, gpio); +- + chip = &gpio->chip; + chip->label = "gpio-tqmx86"; + chip->owner = THIS_MODULE; +-- +2.43.0 + diff --git a/queue-5.10/gpio-tqmx86-store-irq-trigger-type-and-unmask-status.patch b/queue-5.10/gpio-tqmx86-store-irq-trigger-type-and-unmask-status.patch new file mode 100644 index 00000000000..829b4cdf9e0 --- /dev/null +++ b/queue-5.10/gpio-tqmx86-store-irq-trigger-type-and-unmask-status.patch @@ -0,0 +1,137 @@ +From 9ad00cebca3b4083468a92595d5a4ef0b4782bd8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 30 May 2024 12:20:01 +0200 +Subject: gpio: tqmx86: store IRQ trigger type and unmask status separately + +From: Matthias Schiffer + +[ Upstream commit 08af509efdf8dad08e972b48de0e2c2a7919ea8b ] + +irq_set_type() should not implicitly unmask the IRQ. + +All accesses to the interrupt configuration register are moved to a new +helper tqmx86_gpio_irq_config(). We also introduce the new rule that +accessing irq_type must happen while locked, which will become +significant for fixing EDGE_BOTH handling. + +Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") +Signed-off-by: Matthias Schiffer +Link: https://lore.kernel.org/r/6aa4f207f77cb58ef64ffb947e91949b0f753ccd.1717063994.git.matthias.schiffer@ew.tq-group.com +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Sasha Levin +--- + drivers/gpio/gpio-tqmx86.c | 48 ++++++++++++++++++++++---------------- + 1 file changed, 28 insertions(+), 20 deletions(-) + +diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c +index d58fd82b71a8d..e932cc803c24d 100644 +--- a/drivers/gpio/gpio-tqmx86.c ++++ b/drivers/gpio/gpio-tqmx86.c +@@ -29,15 +29,19 @@ + #define TQMX86_GPIIC 3 /* GPI Interrupt Configuration Register */ + #define TQMX86_GPIIS 4 /* GPI Interrupt Status Register */ + ++#define TQMX86_GPII_NONE 0 + #define TQMX86_GPII_FALLING BIT(0) + #define TQMX86_GPII_RISING BIT(1) + #define TQMX86_GPII_MASK (BIT(0) | BIT(1)) + #define TQMX86_GPII_BITS 2 ++/* Stored in irq_type with GPII bits */ ++#define TQMX86_INT_UNMASKED BIT(2) + + struct tqmx86_gpio_data { + struct gpio_chip chip; + void __iomem *io_base; + int irq; ++ /* Lock must be held for accessing output and irq_type fields */ + raw_spinlock_t spinlock; + DECLARE_BITMAP(output, TQMX86_NGPIO); + u8 irq_type[TQMX86_NGPI]; +@@ -104,21 +108,32 @@ static int tqmx86_gpio_get_direction(struct gpio_chip *chip, + return GPIO_LINE_DIRECTION_OUT; + } + ++static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int offset) ++ __must_hold(&gpio->spinlock) ++{ ++ u8 type = TQMX86_GPII_NONE, gpiic; ++ ++ if (gpio->irq_type[offset] & TQMX86_INT_UNMASKED) ++ type = gpio->irq_type[offset] & TQMX86_GPII_MASK; ++ ++ gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); ++ gpiic &= ~(TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS)); ++ gpiic |= type << (offset * TQMX86_GPII_BITS); ++ tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); ++} ++ + static void tqmx86_gpio_irq_mask(struct irq_data *data) + { + unsigned int offset = (data->hwirq - TQMX86_NGPO); + struct tqmx86_gpio_data *gpio = gpiochip_get_data( + irq_data_get_irq_chip_data(data)); + unsigned long flags; +- u8 gpiic, mask; +- +- mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS); + + raw_spin_lock_irqsave(&gpio->spinlock, flags); +- gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); +- gpiic &= ~mask; +- tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); ++ gpio->irq_type[offset] &= ~TQMX86_INT_UNMASKED; ++ tqmx86_gpio_irq_config(gpio, offset); + raw_spin_unlock_irqrestore(&gpio->spinlock, flags); ++ + gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(data)); + } + +@@ -128,16 +143,12 @@ static void tqmx86_gpio_irq_unmask(struct irq_data *data) + struct tqmx86_gpio_data *gpio = gpiochip_get_data( + irq_data_get_irq_chip_data(data)); + unsigned long flags; +- u8 gpiic, mask; +- +- mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS); + + gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(data)); ++ + raw_spin_lock_irqsave(&gpio->spinlock, flags); +- gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); +- gpiic &= ~mask; +- gpiic |= gpio->irq_type[offset] << (offset * TQMX86_GPII_BITS); +- tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); ++ gpio->irq_type[offset] |= TQMX86_INT_UNMASKED; ++ tqmx86_gpio_irq_config(gpio, offset); + raw_spin_unlock_irqrestore(&gpio->spinlock, flags); + } + +@@ -148,7 +159,7 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) + unsigned int offset = (data->hwirq - TQMX86_NGPO); + unsigned int edge_type = type & IRQF_TRIGGER_MASK; + unsigned long flags; +- u8 new_type, gpiic; ++ u8 new_type; + + switch (edge_type) { + case IRQ_TYPE_EDGE_RISING: +@@ -164,13 +175,10 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) + return -EINVAL; /* not supported */ + } + +- gpio->irq_type[offset] = new_type; +- + raw_spin_lock_irqsave(&gpio->spinlock, flags); +- gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); +- gpiic &= ~((TQMX86_GPII_MASK) << (offset * TQMX86_GPII_BITS)); +- gpiic |= new_type << (offset * TQMX86_GPII_BITS); +- tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); ++ gpio->irq_type[offset] &= ~TQMX86_GPII_MASK; ++ gpio->irq_type[offset] |= new_type; ++ tqmx86_gpio_irq_config(gpio, offset); + raw_spin_unlock_irqrestore(&gpio->spinlock, flags); + + return 0; +-- +2.43.0 + diff --git a/queue-5.10/hid-core-remove-unnecessary-warn_on-in-implement.patch b/queue-5.10/hid-core-remove-unnecessary-warn_on-in-implement.patch new file mode 100644 index 00000000000..e3462ccfc97 --- /dev/null +++ b/queue-5.10/hid-core-remove-unnecessary-warn_on-in-implement.patch @@ -0,0 +1,67 @@ +From b59015927db5500ef1cb409f9b265848f8a00582 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 17 May 2024 07:19:14 -0700 +Subject: HID: core: remove unnecessary WARN_ON() in implement() + +From: Nikita Zhandarovich + +[ Upstream commit 4aa2dcfbad538adf7becd0034a3754e1bd01b2b5 ] + +Syzkaller hit a warning [1] in a call to implement() when trying +to write a value into a field of smaller size in an output report. + +Since implement() already has a warn message printed out with the +help of hid_warn() and value in question gets trimmed with: + ... + value &= m; + ... +WARN_ON may be considered superfluous. Remove it to suppress future +syzkaller triggers. + +[1] +WARNING: CPU: 0 PID: 5084 at drivers/hid/hid-core.c:1451 implement drivers/hid/hid-core.c:1451 [inline] +WARNING: CPU: 0 PID: 5084 at drivers/hid/hid-core.c:1451 hid_output_report+0x548/0x760 drivers/hid/hid-core.c:1863 +Modules linked in: +CPU: 0 PID: 5084 Comm: syz-executor424 Not tainted 6.9.0-rc7-syzkaller-00183-gcf87f46fd34d #0 +Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 04/02/2024 +RIP: 0010:implement drivers/hid/hid-core.c:1451 [inline] +RIP: 0010:hid_output_report+0x548/0x760 drivers/hid/hid-core.c:1863 +... +Call Trace: + + __usbhid_submit_report drivers/hid/usbhid/hid-core.c:591 [inline] + usbhid_submit_report+0x43d/0x9e0 drivers/hid/usbhid/hid-core.c:636 + hiddev_ioctl+0x138b/0x1f00 drivers/hid/usbhid/hiddev.c:726 + vfs_ioctl fs/ioctl.c:51 [inline] + __do_sys_ioctl fs/ioctl.c:904 [inline] + __se_sys_ioctl+0xfc/0x170 fs/ioctl.c:890 + do_syscall_x64 arch/x86/entry/common.c:52 [inline] + do_syscall_64+0xf5/0x240 arch/x86/entry/common.c:83 + entry_SYSCALL_64_after_hwframe+0x77/0x7f +... + +Fixes: 95d1c8951e5b ("HID: simplify implement() a bit") +Reported-by: +Suggested-by: Alan Stern +Signed-off-by: Nikita Zhandarovich +Signed-off-by: Jiri Kosina +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-core.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c +index 476967ab6294c..5281d693b32d2 100644 +--- a/drivers/hid/hid-core.c ++++ b/drivers/hid/hid-core.c +@@ -1446,7 +1446,6 @@ static void implement(const struct hid_device *hid, u8 *report, + hid_warn(hid, + "%s() called with too large value %d (n: %d)! (%s)\n", + __func__, value, n, current->comm); +- WARN_ON(1); + value &= m; + } + } +-- +2.43.0 + diff --git a/queue-5.10/hid-logitech-dj-fix-memory-leak-in-logi_dj_recv_swit.patch b/queue-5.10/hid-logitech-dj-fix-memory-leak-in-logi_dj_recv_swit.patch new file mode 100644 index 00000000000..9aa38236463 --- /dev/null +++ b/queue-5.10/hid-logitech-dj-fix-memory-leak-in-logi_dj_recv_swit.patch @@ -0,0 +1,41 @@ +From 69f016cc3efdeca259216c6bd84177edd0fc97a5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 24 May 2024 15:05:39 +0200 +Subject: HID: logitech-dj: Fix memory leak in logi_dj_recv_switch_to_dj_mode() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: José Expósito + +[ Upstream commit ce3af2ee95170b7d9e15fff6e500d67deab1e7b3 ] + +Fix a memory leak on logi_dj_recv_send_report() error path. + +Fixes: 6f20d3261265 ("HID: logitech-dj: Fix error handling in logi_dj_recv_switch_to_dj_mode()") +Signed-off-by: José Expósito +Signed-off-by: Jiri Kosina +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-logitech-dj.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/hid/hid-logitech-dj.c b/drivers/hid/hid-logitech-dj.c +index f4d79ec826797..bda9150aa372a 100644 +--- a/drivers/hid/hid-logitech-dj.c ++++ b/drivers/hid/hid-logitech-dj.c +@@ -1218,8 +1218,10 @@ static int logi_dj_recv_switch_to_dj_mode(struct dj_receiver_dev *djrcv_dev, + */ + msleep(50); + +- if (retval) ++ if (retval) { ++ kfree(dj_report); + return retval; ++ } + } + + /* +-- +2.43.0 + diff --git a/queue-5.10/iommu-amd-fix-sysfs-leak-in-iommu-init.patch b/queue-5.10/iommu-amd-fix-sysfs-leak-in-iommu-init.patch new file mode 100644 index 00000000000..ae87d9d9688 --- /dev/null +++ b/queue-5.10/iommu-amd-fix-sysfs-leak-in-iommu-init.patch @@ -0,0 +1,47 @@ +From d3a2ce835fa034155b9e0d9443c982cd3fed67c4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 May 2024 08:42:20 +0800 +Subject: iommu/amd: Fix sysfs leak in iommu init + +From: Kun(llfl) + +[ Upstream commit a295ec52c8624883885396fde7b4df1a179627c3 ] + +During the iommu initialization, iommu_init_pci() adds sysfs nodes. +However, these nodes aren't remove in free_iommu_resources() subsequently. + +Fixes: 39ab9555c241 ("iommu: Add sysfs bindings for struct iommu_device") +Signed-off-by: Kun(llfl) +Reviewed-by: Suravee Suthikulpanit +Link: https://lore.kernel.org/r/c8e0d11c6ab1ee48299c288009cf9c5dae07b42d.1715215003.git.llfl@linux.alibaba.com +Signed-off-by: Joerg Roedel +Signed-off-by: Sasha Levin +--- + drivers/iommu/amd/init.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c +index 22d28dbe092ee..917ee5a67e787 100644 +--- a/drivers/iommu/amd/init.c ++++ b/drivers/iommu/amd/init.c +@@ -1494,8 +1494,17 @@ static void __init free_pci_segments(void) + } + } + ++static void __init free_sysfs(struct amd_iommu *iommu) ++{ ++ if (iommu->iommu.dev) { ++ iommu_device_unregister(&iommu->iommu); ++ iommu_device_sysfs_remove(&iommu->iommu); ++ } ++} ++ + static void __init free_iommu_one(struct amd_iommu *iommu) + { ++ free_sysfs(iommu); + free_cwwb_sem(iommu); + free_command_buffer(iommu); + free_event_buffer(iommu); +-- +2.43.0 + diff --git a/queue-5.10/iommu-amd-introduce-pci-segment-structure.patch b/queue-5.10/iommu-amd-introduce-pci-segment-structure.patch new file mode 100644 index 00000000000..d659621a1a9 --- /dev/null +++ b/queue-5.10/iommu-amd-introduce-pci-segment-structure.patch @@ -0,0 +1,182 @@ +From f2763f14ec4d6e69ac0ee82a9071c21d88128180 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 6 Jul 2022 17:07:52 +0530 +Subject: iommu/amd: Introduce pci segment structure + +From: Vasant Hegde + +[ Upstream commit 404ec4e4c169fb64da6b2a38b471c13ac0897c76 ] + +Newer AMD systems can support multiple PCI segments, where each segment +contains one or more IOMMU instances. However, an IOMMU instance can only +support a single PCI segment. + +Current code assumes that system contains only one pci segment (segment 0) +and creates global data structures such as device table, rlookup table, +etc. + +Introducing per PCI segment data structure, which contains segment +specific data structures. This will eventually replace the global +data structures. + +Also update `amd_iommu->pci_seg` variable to point to PCI segment +structure instead of PCI segment ID. + +Co-developed-by: Suravee Suthikulpanit +Signed-off-by: Suravee Suthikulpanit +Signed-off-by: Vasant Hegde +Link: https://lore.kernel.org/r/20220706113825.25582-3-vasant.hegde@amd.com +Signed-off-by: Joerg Roedel +Stable-dep-of: a295ec52c862 ("iommu/amd: Fix sysfs leak in iommu init") +Signed-off-by: Sasha Levin +--- + drivers/iommu/amd/amd_iommu_types.h | 24 ++++++++++++++- + drivers/iommu/amd/init.c | 46 ++++++++++++++++++++++++++++- + 2 files changed, 68 insertions(+), 2 deletions(-) + +diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h +index 4a8791e037b84..c4b1a652c2c7f 100644 +--- a/drivers/iommu/amd/amd_iommu_types.h ++++ b/drivers/iommu/amd/amd_iommu_types.h +@@ -435,6 +435,11 @@ extern bool amd_iommu_irq_remap; + /* kmem_cache to get tables with 128 byte alignement */ + extern struct kmem_cache *amd_iommu_irq_cache; + ++/* Make iterating over all pci segment easier */ ++#define for_each_pci_segment(pci_seg) \ ++ list_for_each_entry((pci_seg), &amd_iommu_pci_seg_list, list) ++#define for_each_pci_segment_safe(pci_seg, next) \ ++ list_for_each_entry_safe((pci_seg), (next), &amd_iommu_pci_seg_list, list) + /* + * Make iterating over all IOMMUs easier + */ +@@ -494,6 +499,17 @@ struct domain_pgtable { + u64 *root; + }; + ++/* ++ * This structure contains information about one PCI segment in the system. ++ */ ++struct amd_iommu_pci_seg { ++ /* List with all PCI segments in the system */ ++ struct list_head list; ++ ++ /* PCI segment number */ ++ u16 id; ++}; ++ + /* + * Structure where we save information about one hardware AMD IOMMU in the + * system. +@@ -545,7 +561,7 @@ struct amd_iommu { + u16 cap_ptr; + + /* pci domain of this IOMMU */ +- u16 pci_seg; ++ struct amd_iommu_pci_seg *pci_seg; + + /* start of exclusion range of that IOMMU */ + u64 exclusion_start; +@@ -676,6 +692,12 @@ extern struct list_head ioapic_map; + extern struct list_head hpet_map; + extern struct list_head acpihid_map; + ++/* ++ * List with all PCI segments in the system. This list is not locked because ++ * it is only written at driver initialization time ++ */ ++extern struct list_head amd_iommu_pci_seg_list; ++ + /* + * List with all IOMMUs in the system. This list is not locked because it is + * only written and read at driver initialization or suspend time +diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c +index 91cc3a5643caf..22d28dbe092ee 100644 +--- a/drivers/iommu/amd/init.c ++++ b/drivers/iommu/amd/init.c +@@ -165,6 +165,7 @@ LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings + we find in ACPI */ + bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ + ++LIST_HEAD(amd_iommu_pci_seg_list); /* list of all PCI segments */ + LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the + system */ + +@@ -1456,6 +1457,43 @@ static int __init init_iommu_from_acpi(struct amd_iommu *iommu, + return 0; + } + ++/* Allocate PCI segment data structure */ ++static struct amd_iommu_pci_seg *__init alloc_pci_segment(u16 id) ++{ ++ struct amd_iommu_pci_seg *pci_seg; ++ ++ pci_seg = kzalloc(sizeof(struct amd_iommu_pci_seg), GFP_KERNEL); ++ if (pci_seg == NULL) ++ return NULL; ++ ++ pci_seg->id = id; ++ list_add_tail(&pci_seg->list, &amd_iommu_pci_seg_list); ++ ++ return pci_seg; ++} ++ ++static struct amd_iommu_pci_seg *__init get_pci_segment(u16 id) ++{ ++ struct amd_iommu_pci_seg *pci_seg; ++ ++ for_each_pci_segment(pci_seg) { ++ if (pci_seg->id == id) ++ return pci_seg; ++ } ++ ++ return alloc_pci_segment(id); ++} ++ ++static void __init free_pci_segments(void) ++{ ++ struct amd_iommu_pci_seg *pci_seg, *next; ++ ++ for_each_pci_segment_safe(pci_seg, next) { ++ list_del(&pci_seg->list); ++ kfree(pci_seg); ++ } ++} ++ + static void __init free_iommu_one(struct amd_iommu *iommu) + { + free_cwwb_sem(iommu); +@@ -1542,8 +1580,14 @@ static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) + */ + static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) + { ++ struct amd_iommu_pci_seg *pci_seg; + int ret; + ++ pci_seg = get_pci_segment(h->pci_seg); ++ if (pci_seg == NULL) ++ return -ENOMEM; ++ iommu->pci_seg = pci_seg; ++ + raw_spin_lock_init(&iommu->lock); + iommu->cmd_sem_val = 0; + +@@ -1564,7 +1608,6 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) + */ + iommu->devid = h->devid; + iommu->cap_ptr = h->cap_ptr; +- iommu->pci_seg = h->pci_seg; + iommu->mmio_phys = h->mmio_phys; + + switch (h->type) { +@@ -2511,6 +2554,7 @@ static void __init free_iommu_resources(void) + amd_iommu_dev_table = NULL; + + free_iommu_all(); ++ free_pci_segments(); + } + + /* SB IOAPIC is always on this device in AMD systems */ +-- +2.43.0 + diff --git a/queue-5.10/iommu-return-right-value-in-iommu_sva_bind_device.patch b/queue-5.10/iommu-return-right-value-in-iommu_sva_bind_device.patch new file mode 100644 index 00000000000..3f7babbecd9 --- /dev/null +++ b/queue-5.10/iommu-return-right-value-in-iommu_sva_bind_device.patch @@ -0,0 +1,49 @@ +From ecb33f8a45ed512da2623acbb9c03db765638c08 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 May 2024 12:25:28 +0800 +Subject: iommu: Return right value in iommu_sva_bind_device() + +From: Lu Baolu + +[ Upstream commit 89e8a2366e3bce584b6c01549d5019c5cda1205e ] + +iommu_sva_bind_device() should return either a sva bond handle or an +ERR_PTR value in error cases. Existing drivers (idxd and uacce) only +check the return value with IS_ERR(). This could potentially lead to +a kernel NULL pointer dereference issue if the function returns NULL +instead of an error pointer. + +In reality, this doesn't cause any problems because iommu_sva_bind_device() +only returns NULL when the kernel is not configured with CONFIG_IOMMU_SVA. +In this case, iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_SVA) will +return an error, and the device drivers won't call iommu_sva_bind_device() +at all. + +Fixes: 26b25a2b98e4 ("iommu: Bind process address spaces to devices") +Signed-off-by: Lu Baolu +Reviewed-by: Jean-Philippe Brucker +Reviewed-by: Kevin Tian +Reviewed-by: Vasant Hegde +Link: https://lore.kernel.org/r/20240528042528.71396-1-baolu.lu@linux.intel.com +Signed-off-by: Joerg Roedel +Signed-off-by: Sasha Levin +--- + include/linux/iommu.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/linux/iommu.h b/include/linux/iommu.h +index e90c267e7f3e1..2698dd231298c 100644 +--- a/include/linux/iommu.h ++++ b/include/linux/iommu.h +@@ -1026,7 +1026,7 @@ iommu_aux_get_pasid(struct iommu_domain *domain, struct device *dev) + static inline struct iommu_sva * + iommu_sva_bind_device(struct device *dev, struct mm_struct *mm, void *drvdata) + { +- return NULL; ++ return ERR_PTR(-ENODEV); + } + + static inline void iommu_sva_unbind_device(struct iommu_sva *handle) +-- +2.43.0 + diff --git a/queue-5.10/ionic-fix-use-after-netif_napi_del.patch b/queue-5.10/ionic-fix-use-after-netif_napi_del.patch new file mode 100644 index 00000000000..21b86baac70 --- /dev/null +++ b/queue-5.10/ionic-fix-use-after-netif_napi_del.patch @@ -0,0 +1,97 @@ +From 02619aa5238d07aaef9d9619c3a0694b8fe76c60 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 12 Jun 2024 06:04:46 +0000 +Subject: ionic: fix use after netif_napi_del() + +From: Taehee Yoo + +[ Upstream commit 79f18a41dd056115d685f3b0a419c7cd40055e13 ] + +When queues are started, netif_napi_add() and napi_enable() are called. +If there are 4 queues and only 3 queues are used for the current +configuration, only 3 queues' napi should be registered and enabled. +The ionic_qcq_enable() checks whether the .poll pointer is not NULL for +enabling only the using queue' napi. Unused queues' napi will not be +registered by netif_napi_add(), so the .poll pointer indicates NULL. +But it couldn't distinguish whether the napi was unregistered or not +because netif_napi_del() doesn't reset the .poll pointer to NULL. +So, ionic_qcq_enable() calls napi_enable() for the queue, which was +unregistered by netif_napi_del(). + +Reproducer: + ethtool -L rx 1 tx 1 combined 0 + ethtool -L rx 0 tx 0 combined 1 + ethtool -L rx 0 tx 0 combined 4 + +Splat looks like: +kernel BUG at net/core/dev.c:6666! +Oops: invalid opcode: 0000 [#1] PREEMPT SMP NOPTI +CPU: 3 PID: 1057 Comm: kworker/3:3 Not tainted 6.10.0-rc2+ #16 +Workqueue: events ionic_lif_deferred_work [ionic] +RIP: 0010:napi_enable+0x3b/0x40 +Code: 48 89 c2 48 83 e2 f6 80 b9 61 09 00 00 00 74 0d 48 83 bf 60 01 00 00 00 74 03 80 ce 01 f0 4f +RSP: 0018:ffffb6ed83227d48 EFLAGS: 00010246 +RAX: 0000000000000000 RBX: ffff97560cda0828 RCX: 0000000000000029 +RDX: 0000000000000001 RSI: 0000000000000000 RDI: ffff97560cda0a28 +RBP: ffffb6ed83227d50 R08: 0000000000000400 R09: 0000000000000001 +R10: 0000000000000001 R11: 0000000000000001 R12: 0000000000000000 +R13: ffff97560ce3c1a0 R14: 0000000000000000 R15: ffff975613ba0a20 +FS: 0000000000000000(0000) GS:ffff975d5f780000(0000) knlGS:0000000000000000 +CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 +CR2: 00007f8f734ee200 CR3: 0000000103e50000 CR4: 00000000007506f0 +PKRU: 55555554 +Call Trace: + + ? die+0x33/0x90 + ? do_trap+0xd9/0x100 + ? napi_enable+0x3b/0x40 + ? do_error_trap+0x83/0xb0 + ? napi_enable+0x3b/0x40 + ? napi_enable+0x3b/0x40 + ? exc_invalid_op+0x4e/0x70 + ? napi_enable+0x3b/0x40 + ? asm_exc_invalid_op+0x16/0x20 + ? napi_enable+0x3b/0x40 + ionic_qcq_enable+0xb7/0x180 [ionic 59bdfc8a035436e1c4224ff7d10789e3f14643f8] + ionic_start_queues+0xc4/0x290 [ionic 59bdfc8a035436e1c4224ff7d10789e3f14643f8] + ionic_link_status_check+0x11c/0x170 [ionic 59bdfc8a035436e1c4224ff7d10789e3f14643f8] + ionic_lif_deferred_work+0x129/0x280 [ionic 59bdfc8a035436e1c4224ff7d10789e3f14643f8] + process_one_work+0x145/0x360 + worker_thread+0x2bb/0x3d0 + ? __pfx_worker_thread+0x10/0x10 + kthread+0xcc/0x100 + ? __pfx_kthread+0x10/0x10 + ret_from_fork+0x2d/0x50 + ? __pfx_kthread+0x10/0x10 + ret_from_fork_asm+0x1a/0x30 + +Fixes: 0f3154e6bcb3 ("ionic: Add Tx and Rx handling") +Signed-off-by: Taehee Yoo +Reviewed-by: Brett Creeley +Reviewed-by: Shannon Nelson +Link: https://lore.kernel.org/r/20240612060446.1754392-1-ap420073@gmail.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/pensando/ionic/ionic_lif.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c +index a37ca4b1e5665..324ef6990e9a7 100644 +--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c ++++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c +@@ -272,10 +272,8 @@ static int ionic_qcq_enable(struct ionic_qcq *qcq) + if (ret) + return ret; + +- if (qcq->napi.poll) +- napi_enable(&qcq->napi); +- + if (qcq->flags & IONIC_QCQ_F_INTR) { ++ napi_enable(&qcq->napi); + irq_set_affinity_hint(qcq->intr.vector, + &qcq->intr.affinity_mask); + ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, +-- +2.43.0 + diff --git a/queue-5.10/liquidio-adjust-a-null-pointer-handling-path-in-lio_.patch b/queue-5.10/liquidio-adjust-a-null-pointer-handling-path-in-lio_.patch new file mode 100644 index 00000000000..f5b836c53e7 --- /dev/null +++ b/queue-5.10/liquidio-adjust-a-null-pointer-handling-path-in-lio_.patch @@ -0,0 +1,69 @@ +From 3112a516bda2be7a9d70133e1b01fce86c34914b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 5 Jun 2024 13:11:35 +0300 +Subject: liquidio: Adjust a NULL pointer handling path in + lio_vf_rep_copy_packet + +From: Aleksandr Mishin + +[ Upstream commit c44711b78608c98a3e6b49ce91678cd0917d5349 ] + +In lio_vf_rep_copy_packet() pg_info->page is compared to a NULL value, +but then it is unconditionally passed to skb_add_rx_frag() which looks +strange and could lead to null pointer dereference. + +lio_vf_rep_copy_packet() call trace looks like: + octeon_droq_process_packets + octeon_droq_fast_process_packets + octeon_droq_dispatch_pkt + octeon_create_recv_info + ...search in the dispatch_list... + ->disp_fn(rdisp->rinfo, ...) + lio_vf_rep_pkt_recv(struct octeon_recv_info *recv_info, ...) +In this path there is no code which sets pg_info->page to NULL. +So this check looks unneeded and doesn't solve potential problem. +But I guess the author had reason to add a check and I have no such card +and can't do real test. +In addition, the code in the function liquidio_push_packet() in +liquidio/lio_core.c does exactly the same. + +Based on this, I consider the most acceptable compromise solution to +adjust this issue by moving skb_add_rx_frag() into conditional scope. + +Found by Linux Verification Center (linuxtesting.org) with SVACE. + +Fixes: 1f233f327913 ("liquidio: switchdev support for LiquidIO NIC") +Signed-off-by: Aleksandr Mishin +Reviewed-by: Simon Horman +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/cavium/liquidio/lio_vf_rep.c | 11 +++++------ + 1 file changed, 5 insertions(+), 6 deletions(-) + +diff --git a/drivers/net/ethernet/cavium/liquidio/lio_vf_rep.c b/drivers/net/ethernet/cavium/liquidio/lio_vf_rep.c +index 600de587d7a98..e70b9ccca380e 100644 +--- a/drivers/net/ethernet/cavium/liquidio/lio_vf_rep.c ++++ b/drivers/net/ethernet/cavium/liquidio/lio_vf_rep.c +@@ -272,13 +272,12 @@ lio_vf_rep_copy_packet(struct octeon_device *oct, + pg_info->page_offset; + memcpy(skb->data, va, MIN_SKB_SIZE); + skb_put(skb, MIN_SKB_SIZE); ++ skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, ++ pg_info->page, ++ pg_info->page_offset + MIN_SKB_SIZE, ++ len - MIN_SKB_SIZE, ++ LIO_RXBUFFER_SZ); + } +- +- skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, +- pg_info->page, +- pg_info->page_offset + MIN_SKB_SIZE, +- len - MIN_SKB_SIZE, +- LIO_RXBUFFER_SZ); + } else { + struct octeon_skb_page_info *pg_info = + ((struct octeon_skb_page_info *)(skb->cb)); +-- +2.43.0 + diff --git a/queue-5.10/net-geneve-support-ipv4-ipv6-as-inner-protocol.patch b/queue-5.10/net-geneve-support-ipv4-ipv6-as-inner-protocol.patch new file mode 100644 index 00000000000..3a7b5e91139 --- /dev/null +++ b/queue-5.10/net-geneve-support-ipv4-ipv6-as-inner-protocol.patch @@ -0,0 +1,237 @@ +From 292aedc50f4ca600cd3274b7c077c38d6ae9ff41 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 16 Mar 2022 08:15:57 +0200 +Subject: net: geneve: support IPv4/IPv6 as inner protocol + +From: Eyal Birger + +[ Upstream commit 435fe1c0c1f74b682dba85641406abf4337aade6 ] + +This patch adds support for encapsulating IPv4/IPv6 within GENEVE. + +In order to use this, a new IFLA_GENEVE_INNER_PROTO_INHERIT flag needs +to be provided at device creation. This property cannot be changed for +the time being. + +In case IP traffic is received on a non-tun device the drop count is +increased. + +Signed-off-by: Eyal Birger +Link: https://lore.kernel.org/r/20220316061557.431872-1-eyal.birger@gmail.com +Signed-off-by: Paolo Abeni +Stable-dep-of: c6ae073f5903 ("geneve: Fix incorrect inner network header offset when innerprotoinherit is set") +Signed-off-by: Sasha Levin +--- + drivers/net/geneve.c | 82 +++++++++++++++++++++++++++--------- + include/uapi/linux/if_link.h | 1 + + 2 files changed, 64 insertions(+), 19 deletions(-) + +diff --git a/drivers/net/geneve.c b/drivers/net/geneve.c +index af35361a3dcee..c4cc539fe3155 100644 +--- a/drivers/net/geneve.c ++++ b/drivers/net/geneve.c +@@ -54,6 +54,7 @@ struct geneve_config { + bool use_udp6_rx_checksums; + bool ttl_inherit; + enum ifla_geneve_df df; ++ bool inner_proto_inherit; + }; + + /* Pseudo network device */ +@@ -249,17 +250,24 @@ static void geneve_rx(struct geneve_dev *geneve, struct geneve_sock *gs, + } + } + +- skb_reset_mac_header(skb); +- skb->protocol = eth_type_trans(skb, geneve->dev); +- skb_postpull_rcsum(skb, eth_hdr(skb), ETH_HLEN); +- + if (tun_dst) + skb_dst_set(skb, &tun_dst->dst); + +- /* Ignore packet loops (and multicast echo) */ +- if (ether_addr_equal(eth_hdr(skb)->h_source, geneve->dev->dev_addr)) { +- geneve->dev->stats.rx_errors++; +- goto drop; ++ if (gnvh->proto_type == htons(ETH_P_TEB)) { ++ skb_reset_mac_header(skb); ++ skb->protocol = eth_type_trans(skb, geneve->dev); ++ skb_postpull_rcsum(skb, eth_hdr(skb), ETH_HLEN); ++ ++ /* Ignore packet loops (and multicast echo) */ ++ if (ether_addr_equal(eth_hdr(skb)->h_source, ++ geneve->dev->dev_addr)) { ++ geneve->dev->stats.rx_errors++; ++ goto drop; ++ } ++ } else { ++ skb_reset_mac_header(skb); ++ skb->dev = geneve->dev; ++ skb->pkt_type = PACKET_HOST; + } + + /* Save offset of outer header relative to skb->head, +@@ -357,6 +365,7 @@ static int geneve_udp_encap_recv(struct sock *sk, struct sk_buff *skb) + struct genevehdr *geneveh; + struct geneve_dev *geneve; + struct geneve_sock *gs; ++ __be16 inner_proto; + int opts_len; + + /* Need UDP and Geneve header to be present */ +@@ -368,7 +377,11 @@ static int geneve_udp_encap_recv(struct sock *sk, struct sk_buff *skb) + if (unlikely(geneveh->ver != GENEVE_VER)) + goto drop; + +- if (unlikely(geneveh->proto_type != htons(ETH_P_TEB))) ++ inner_proto = geneveh->proto_type; ++ ++ if (unlikely((inner_proto != htons(ETH_P_TEB) && ++ inner_proto != htons(ETH_P_IP) && ++ inner_proto != htons(ETH_P_IPV6)))) + goto drop; + + gs = rcu_dereference_sk_user_data(sk); +@@ -379,9 +392,14 @@ static int geneve_udp_encap_recv(struct sock *sk, struct sk_buff *skb) + if (!geneve) + goto drop; + ++ if (unlikely((!geneve->cfg.inner_proto_inherit && ++ inner_proto != htons(ETH_P_TEB)))) { ++ geneve->dev->stats.rx_dropped++; ++ goto drop; ++ } ++ + opts_len = geneveh->opt_len * 4; +- if (iptunnel_pull_header(skb, GENEVE_BASE_HLEN + opts_len, +- htons(ETH_P_TEB), ++ if (iptunnel_pull_header(skb, GENEVE_BASE_HLEN + opts_len, inner_proto, + !net_eq(geneve->net, dev_net(geneve->dev)))) { + geneve->dev->stats.rx_dropped++; + goto drop; +@@ -734,7 +752,8 @@ static int geneve_stop(struct net_device *dev) + } + + static void geneve_build_header(struct genevehdr *geneveh, +- const struct ip_tunnel_info *info) ++ const struct ip_tunnel_info *info, ++ __be16 inner_proto) + { + geneveh->ver = GENEVE_VER; + geneveh->opt_len = info->options_len / 4; +@@ -742,7 +761,7 @@ static void geneve_build_header(struct genevehdr *geneveh, + geneveh->critical = !!(info->key.tun_flags & TUNNEL_CRIT_OPT); + geneveh->rsvd1 = 0; + tunnel_id_to_vni(info->key.tun_id, geneveh->vni); +- geneveh->proto_type = htons(ETH_P_TEB); ++ geneveh->proto_type = inner_proto; + geneveh->rsvd2 = 0; + + if (info->key.tun_flags & TUNNEL_GENEVE_OPT) +@@ -751,10 +770,12 @@ static void geneve_build_header(struct genevehdr *geneveh, + + static int geneve_build_skb(struct dst_entry *dst, struct sk_buff *skb, + const struct ip_tunnel_info *info, +- bool xnet, int ip_hdr_len) ++ bool xnet, int ip_hdr_len, ++ bool inner_proto_inherit) + { + bool udp_sum = !!(info->key.tun_flags & TUNNEL_CSUM); + struct genevehdr *gnvh; ++ __be16 inner_proto; + int min_headroom; + int err; + +@@ -772,8 +793,9 @@ static int geneve_build_skb(struct dst_entry *dst, struct sk_buff *skb, + goto free_dst; + + gnvh = __skb_push(skb, sizeof(*gnvh) + info->options_len); +- geneve_build_header(gnvh, info); +- skb_set_inner_protocol(skb, htons(ETH_P_TEB)); ++ inner_proto = inner_proto_inherit ? skb->protocol : htons(ETH_P_TEB); ++ geneve_build_header(gnvh, info, inner_proto); ++ skb_set_inner_protocol(skb, inner_proto); + return 0; + + free_dst: +@@ -979,7 +1001,8 @@ static int geneve_xmit_skb(struct sk_buff *skb, struct net_device *dev, + } + } + +- err = geneve_build_skb(&rt->dst, skb, info, xnet, sizeof(struct iphdr)); ++ err = geneve_build_skb(&rt->dst, skb, info, xnet, sizeof(struct iphdr), ++ geneve->cfg.inner_proto_inherit); + if (unlikely(err)) + return err; + +@@ -1058,7 +1081,8 @@ static int geneve6_xmit_skb(struct sk_buff *skb, struct net_device *dev, + ttl = key->ttl; + ttl = ttl ? : ip6_dst_hoplimit(dst); + } +- err = geneve_build_skb(dst, skb, info, xnet, sizeof(struct ipv6hdr)); ++ err = geneve_build_skb(dst, skb, info, xnet, sizeof(struct ipv6hdr), ++ geneve->cfg.inner_proto_inherit); + if (unlikely(err)) + return err; + +@@ -1407,6 +1431,14 @@ static int geneve_configure(struct net *net, struct net_device *dev, + dst_cache_reset(&geneve->cfg.info.dst_cache); + memcpy(&geneve->cfg, cfg, sizeof(*cfg)); + ++ if (geneve->cfg.inner_proto_inherit) { ++ dev->header_ops = NULL; ++ dev->type = ARPHRD_NONE; ++ dev->hard_header_len = 0; ++ dev->addr_len = 0; ++ dev->flags = IFF_NOARP; ++ } ++ + err = register_netdevice(dev); + if (err) + return err; +@@ -1580,10 +1612,18 @@ static int geneve_nl2info(struct nlattr *tb[], struct nlattr *data[], + #endif + } + ++ if (data[IFLA_GENEVE_INNER_PROTO_INHERIT]) { ++ if (changelink) { ++ attrtype = IFLA_GENEVE_INNER_PROTO_INHERIT; ++ goto change_notsup; ++ } ++ cfg->inner_proto_inherit = true; ++ } ++ + return 0; + change_notsup: + NL_SET_ERR_MSG_ATTR(extack, data[attrtype], +- "Changing VNI, Port, endpoint IP address family, external, and UDP checksum attributes are not supported"); ++ "Changing VNI, Port, endpoint IP address family, external, inner_proto_inherit, and UDP checksum attributes are not supported"); + return -EOPNOTSUPP; + } + +@@ -1818,6 +1858,10 @@ static int geneve_fill_info(struct sk_buff *skb, const struct net_device *dev) + if (nla_put_u8(skb, IFLA_GENEVE_TTL_INHERIT, ttl_inherit)) + goto nla_put_failure; + ++ if (geneve->cfg.inner_proto_inherit && ++ nla_put_flag(skb, IFLA_GENEVE_INNER_PROTO_INHERIT)) ++ goto nla_put_failure; ++ + return 0; + + nla_put_failure: +diff --git a/include/uapi/linux/if_link.h b/include/uapi/linux/if_link.h +index c4b23f06f69e0..9334f2128bb2e 100644 +--- a/include/uapi/linux/if_link.h ++++ b/include/uapi/linux/if_link.h +@@ -761,6 +761,7 @@ enum { + IFLA_GENEVE_LABEL, + IFLA_GENEVE_TTL_INHERIT, + IFLA_GENEVE_DF, ++ IFLA_GENEVE_INNER_PROTO_INHERIT, + __IFLA_GENEVE_MAX + }; + #define IFLA_GENEVE_MAX (__IFLA_GENEVE_MAX - 1) +-- +2.43.0 + diff --git a/queue-5.10/net-hns3-add-cond_resched-to-hns3-ring-buffer-init-p.patch b/queue-5.10/net-hns3-add-cond_resched-to-hns3-ring-buffer-init-p.patch new file mode 100644 index 00000000000..6dd0fcdff3c --- /dev/null +++ b/queue-5.10/net-hns3-add-cond_resched-to-hns3-ring-buffer-init-p.patch @@ -0,0 +1,64 @@ +From 7713beb69c107dc98239f8392f57f813f7f43aa9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 5 Jun 2024 15:20:58 +0800 +Subject: net: hns3: add cond_resched() to hns3 ring buffer init process + +From: Jie Wang + +[ Upstream commit 968fde83841a8c23558dfbd0a0c69d636db52b55 ] + +Currently hns3 ring buffer init process would hold cpu too long with big +Tx/Rx ring depth. This could cause soft lockup. + +So this patch adds cond_resched() to the process. Then cpu can break to +run other tasks instead of busy looping. + +Fixes: a723fb8efe29 ("net: hns3: refine for set ring parameters") +Signed-off-by: Jie Wang +Signed-off-by: Jijie Shao +Reviewed-by: Simon Horman +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 4 ++++ + drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 2 ++ + 2 files changed, 6 insertions(+) + +diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c +index a4ab3e7efa5e4..f8275534205a7 100644 +--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c ++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c +@@ -2513,6 +2513,9 @@ static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) + ret = hns3_alloc_and_attach_buffer(ring, i); + if (ret) + goto out_buffer_fail; ++ ++ if (!(i % HNS3_RESCHED_BD_NUM)) ++ cond_resched(); + } + + return 0; +@@ -3946,6 +3949,7 @@ int hns3_init_all_ring(struct hns3_nic_priv *priv) + } + + u64_stats_init(&priv->ring[i].syncp); ++ cond_resched(); + } + + return 0; +diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h +index 54d02ea4aaa7c..669cd30b9871b 100644 +--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h ++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h +@@ -182,6 +182,8 @@ enum hns3_nic_state { + + #define HNS3_RING_EN_B 0 + ++#define HNS3_RESCHED_BD_NUM 1024 ++ + enum hns3_pkt_l2t_type { + HNS3_L2_TYPE_UNICAST, + HNS3_L2_TYPE_MULTICAST, +-- +2.43.0 + diff --git a/queue-5.10/net-ipv6-fix-the-rt-cache-flush-via-sysctl-using-a-p.patch b/queue-5.10/net-ipv6-fix-the-rt-cache-flush-via-sysctl-using-a-p.patch new file mode 100644 index 00000000000..134105b0e73 --- /dev/null +++ b/queue-5.10/net-ipv6-fix-the-rt-cache-flush-via-sysctl-using-a-p.patch @@ -0,0 +1,53 @@ +From dab68f9353b0dd9b81ca19ef6c14cf6891bda718 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 7 Jun 2024 13:28:28 +0200 +Subject: net/ipv6: Fix the RT cache flush via sysctl using a previous delay + +From: Petr Pavlu + +[ Upstream commit 14a20e5b4ad998793c5f43b0330d9e1388446cf3 ] + +The net.ipv6.route.flush system parameter takes a value which specifies +a delay used during the flush operation for aging exception routes. The +written value is however not used in the currently requested flush and +instead utilized only in the next one. + +A problem is that ipv6_sysctl_rtcache_flush() first reads the old value +of net->ipv6.sysctl.flush_delay into a local delay variable and then +calls proc_dointvec() which actually updates the sysctl based on the +provided input. + +Fix the problem by switching the order of the two operations. + +Fixes: 4990509f19e8 ("[NETNS][IPV6]: Make sysctls route per namespace.") +Signed-off-by: Petr Pavlu +Reviewed-by: David Ahern +Link: https://lore.kernel.org/r/20240607112828.30285-1-petr.pavlu@suse.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + net/ipv6/route.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/net/ipv6/route.c b/net/ipv6/route.c +index 62eaaf9532e1c..00e3daaafed82 100644 +--- a/net/ipv6/route.c ++++ b/net/ipv6/route.c +@@ -6181,12 +6181,12 @@ static int ipv6_sysctl_rtcache_flush(struct ctl_table *ctl, int write, + if (!write) + return -EINVAL; + +- net = (struct net *)ctl->extra1; +- delay = net->ipv6.sysctl.flush_delay; + ret = proc_dointvec(ctl, write, buffer, lenp, ppos); + if (ret) + return ret; + ++ net = (struct net *)ctl->extra1; ++ delay = net->ipv6.sysctl.flush_delay; + fib6_run_gc(delay <= 0 ? 0 : (unsigned long)delay, net, delay > 0); + return 0; + } +-- +2.43.0 + diff --git a/queue-5.10/net-mlx5e-fix-features-validation-check-for-tunneled.patch b/queue-5.10/net-mlx5e-fix-features-validation-check-for-tunneled.patch new file mode 100644 index 00000000000..2dfbc12f95d --- /dev/null +++ b/queue-5.10/net-mlx5e-fix-features-validation-check-for-tunneled.patch @@ -0,0 +1,53 @@ +From 5d22012754688d9622460aba4849cdf828e67426 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 6 Jun 2024 23:32:49 +0300 +Subject: net/mlx5e: Fix features validation check for tunneled UDP (non-VXLAN) + packets + +From: Gal Pressman + +[ Upstream commit 791b4089e326271424b78f2fae778b20e53d071b ] + +Move the vxlan_features_check() call to after we verified the packet is +a tunneled VXLAN packet. + +Without this, tunneled UDP non-VXLAN packets (for ex. GENENVE) might +wrongly not get offloaded. +In some cases, it worked by chance as GENEVE header is the same size as +VXLAN, but it is obviously incorrect. + +Fixes: e3cfc7e6b7bd ("net/mlx5e: TX, Add geneve tunnel stateless offload support") +Signed-off-by: Gal Pressman +Reviewed-by: Dragos Tatulea +Signed-off-by: Tariq Toukan +Reviewed-by: Wojciech Drewek +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +index f1834853872da..aeb8bb3c549a1 100644 +--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c ++++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +@@ -4393,7 +4393,7 @@ static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv, + + /* Verify if UDP port is being offloaded by HW */ + if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port)) +- return features; ++ return vxlan_features_check(skb, features); + + #if IS_ENABLED(CONFIG_GENEVE) + /* Support Geneve offload for default UDP port */ +@@ -4414,7 +4414,6 @@ netdev_features_t mlx5e_features_check(struct sk_buff *skb, + struct mlx5e_priv *priv = netdev_priv(netdev); + + features = vlan_features_check(skb, features); +- features = vxlan_features_check(skb, features); + + #ifdef CONFIG_MLX5_EN_IPSEC + if (mlx5e_ipsec_feature_check(skb, netdev, features)) +-- +2.43.0 + diff --git a/queue-5.10/net-sfp-always-call-sfp_sm_mod_remove-on-remove.patch b/queue-5.10/net-sfp-always-call-sfp_sm_mod_remove-on-remove.patch new file mode 100644 index 00000000000..304e26a4217 --- /dev/null +++ b/queue-5.10/net-sfp-always-call-sfp_sm_mod_remove-on-remove.patch @@ -0,0 +1,45 @@ +From 70c3056b85464c4b56638cb11956e705245d8a8a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 5 Jun 2024 10:42:51 +0200 +Subject: net: sfp: Always call `sfp_sm_mod_remove()` on remove +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Csókás, Bence + +[ Upstream commit e96b2933152fd87b6a41765b2f58b158fde855b6 ] + +If the module is in SFP_MOD_ERROR, `sfp_sm_mod_remove()` will +not be run. As a consequence, `sfp_hwmon_remove()` is not getting +run either, leaving a stale `hwmon` device behind. `sfp_sm_mod_remove()` +itself checks `sfp->sm_mod_state` anyways, so this check was not +really needed in the first place. + +Fixes: d2e816c0293f ("net: sfp: handle module remove outside state machine") +Signed-off-by: "Csókás, Bence" +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/20240605084251.63502-1-csokas.bence@prolan.hu +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/phy/sfp.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c +index 6a5f40f11db3f..d08990437f3e7 100644 +--- a/drivers/net/phy/sfp.c ++++ b/drivers/net/phy/sfp.c +@@ -1952,8 +1952,7 @@ static void sfp_sm_module(struct sfp *sfp, unsigned int event) + + /* Handle remove event globally, it resets this state machine */ + if (event == SFP_E_REMOVE) { +- if (sfp->sm_mod_state > SFP_MOD_PROBE) +- sfp_sm_mod_remove(sfp); ++ sfp_sm_mod_remove(sfp); + sfp_sm_mod_next(sfp, SFP_MOD_EMPTY, 0); + return; + } +-- +2.43.0 + diff --git a/queue-5.10/net-stmmac-replace-priv-speed-with-the-porttransmitr.patch b/queue-5.10/net-stmmac-replace-priv-speed-with-the-porttransmitr.patch new file mode 100644 index 00000000000..a0389a0705b --- /dev/null +++ b/queue-5.10/net-stmmac-replace-priv-speed-with-the-porttransmitr.patch @@ -0,0 +1,101 @@ +From dbfb0e827b2c9fd796428c571a8e091a95dfcb15 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 8 Jun 2024 22:35:24 +0800 +Subject: net: stmmac: replace priv->speed with the portTransmitRate from the + tc-cbs parameters + +From: Xiaolei Wang + +[ Upstream commit be27b896529787e23a35ae4befb6337ce73fcca0 ] + +The current cbs parameter depends on speed after uplinking, +which is not needed and will report a configuration error +if the port is not initially connected. The UAPI exposed by +tc-cbs requires userspace to recalculate the send slope anyway, +because the formula depends on port_transmit_rate (see man tc-cbs), +which is not an invariant from tc's perspective. Therefore, we +use offload->sendslope and offload->idleslope to derive the +original port_transmit_rate from the CBS formula. + +Fixes: 1f705bc61aee ("net: stmmac: Add support for CBS QDISC") +Signed-off-by: Xiaolei Wang +Reviewed-by: Wojciech Drewek +Reviewed-by: Vladimir Oltean +Link: https://lore.kernel.org/r/20240608143524.2065736-1-xiaolei.wang@windriver.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + .../net/ethernet/stmicro/stmmac/stmmac_tc.c | 25 ++++++++----------- + 1 file changed, 11 insertions(+), 14 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c +index 43165c662740d..6b93a7614ad98 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c +@@ -310,10 +310,11 @@ static int tc_setup_cbs(struct stmmac_priv *priv, + struct tc_cbs_qopt_offload *qopt) + { + u32 tx_queues_count = priv->plat->tx_queues_to_use; ++ s64 port_transmit_rate_kbps; + u32 queue = qopt->queue; +- u32 ptr, speed_div; + u32 mode_to_use; + u64 value; ++ u32 ptr; + int ret; + + /* Queue 0 is not AVB capable */ +@@ -322,30 +323,26 @@ static int tc_setup_cbs(struct stmmac_priv *priv, + if (!priv->dma_cap.av) + return -EOPNOTSUPP; + ++ port_transmit_rate_kbps = qopt->idleslope - qopt->sendslope; ++ + /* Port Transmit Rate and Speed Divider */ +- switch (priv->speed) { ++ switch (div_s64(port_transmit_rate_kbps, 1000)) { + case SPEED_10000: +- ptr = 32; +- speed_div = 10000000; +- break; + case SPEED_5000: + ptr = 32; +- speed_div = 5000000; + break; + case SPEED_2500: +- ptr = 8; +- speed_div = 2500000; +- break; + case SPEED_1000: + ptr = 8; +- speed_div = 1000000; + break; + case SPEED_100: + ptr = 4; +- speed_div = 100000; + break; + default: +- return -EOPNOTSUPP; ++ netdev_err(priv->dev, ++ "Invalid portTransmitRate %lld (idleSlope - sendSlope)\n", ++ port_transmit_rate_kbps); ++ return -EINVAL; + } + + mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; +@@ -365,10 +362,10 @@ static int tc_setup_cbs(struct stmmac_priv *priv, + } + + /* Final adjustments for HW */ +- value = div_s64(qopt->idleslope * 1024ll * ptr, speed_div); ++ value = div_s64(qopt->idleslope * 1024ll * ptr, port_transmit_rate_kbps); + priv->plat->tx_queues_cfg[queue].idle_slope = value & GENMASK(31, 0); + +- value = div_s64(-qopt->sendslope * 1024ll * ptr, speed_div); ++ value = div_s64(-qopt->sendslope * 1024ll * ptr, port_transmit_rate_kbps); + priv->plat->tx_queues_cfg[queue].send_slope = value & GENMASK(31, 0); + + value = qopt->hicredit * 1024ll * 8; +-- +2.43.0 + diff --git a/queue-5.10/netfilter-ipset-fix-race-between-namespace-cleanup-a.patch b/queue-5.10/netfilter-ipset-fix-race-between-namespace-cleanup-a.patch new file mode 100644 index 00000000000..304a3e75054 --- /dev/null +++ b/queue-5.10/netfilter-ipset-fix-race-between-namespace-cleanup-a.patch @@ -0,0 +1,289 @@ +From ee511d590f5807ac369a674a2732660359e3a3e4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Jun 2024 15:58:03 +0200 +Subject: netfilter: ipset: Fix race between namespace cleanup and gc in the + list:set type + +From: Jozsef Kadlecsik + +[ Upstream commit 4e7aaa6b82d63e8ddcbfb56b4fd3d014ca586f10 ] + +Lion Ackermann reported that there is a race condition between namespace cleanup +in ipset and the garbage collection of the list:set type. The namespace +cleanup can destroy the list:set type of sets while the gc of the set type is +waiting to run in rcu cleanup. The latter uses data from the destroyed set which +thus leads use after free. The patch contains the following parts: + +- When destroying all sets, first remove the garbage collectors, then wait + if needed and then destroy the sets. +- Fix the badly ordered "wait then remove gc" for the destroy a single set + case. +- Fix the missing rcu locking in the list:set type in the userspace test + case. +- Use proper RCU list handlings in the list:set type. + +The patch depends on c1193d9bbbd3 (netfilter: ipset: Add list flush to cancel_gc). + +Fixes: 97f7cf1cd80e (netfilter: ipset: fix performance regression in swap operation) +Reported-by: Lion Ackermann +Tested-by: Lion Ackermann +Signed-off-by: Jozsef Kadlecsik +Signed-off-by: Pablo Neira Ayuso +Signed-off-by: Sasha Levin +--- + net/netfilter/ipset/ip_set_core.c | 81 +++++++++++++++------------ + net/netfilter/ipset/ip_set_list_set.c | 30 +++++----- + 2 files changed, 60 insertions(+), 51 deletions(-) + +diff --git a/net/netfilter/ipset/ip_set_core.c b/net/netfilter/ipset/ip_set_core.c +index cc04c4d7956c5..ecd693fca224f 100644 +--- a/net/netfilter/ipset/ip_set_core.c ++++ b/net/netfilter/ipset/ip_set_core.c +@@ -1176,23 +1176,50 @@ ip_set_setname_policy[IPSET_ATTR_CMD_MAX + 1] = { + .len = IPSET_MAXNAMELEN - 1 }, + }; + ++/* In order to return quickly when destroying a single set, it is split ++ * into two stages: ++ * - Cancel garbage collector ++ * - Destroy the set itself via call_rcu() ++ */ ++ + static void +-ip_set_destroy_set(struct ip_set *set) ++ip_set_destroy_set_rcu(struct rcu_head *head) + { +- pr_debug("set: %s\n", set->name); ++ struct ip_set *set = container_of(head, struct ip_set, rcu); + +- /* Must call it without holding any lock */ + set->variant->destroy(set); + module_put(set->type->me); + kfree(set); + } + + static void +-ip_set_destroy_set_rcu(struct rcu_head *head) ++_destroy_all_sets(struct ip_set_net *inst) + { +- struct ip_set *set = container_of(head, struct ip_set, rcu); ++ struct ip_set *set; ++ ip_set_id_t i; ++ bool need_wait = false; + +- ip_set_destroy_set(set); ++ /* First cancel gc's: set:list sets are flushed as well */ ++ for (i = 0; i < inst->ip_set_max; i++) { ++ set = ip_set(inst, i); ++ if (set) { ++ set->variant->cancel_gc(set); ++ if (set->type->features & IPSET_TYPE_NAME) ++ need_wait = true; ++ } ++ } ++ /* Must wait for flush to be really finished */ ++ if (need_wait) ++ rcu_barrier(); ++ for (i = 0; i < inst->ip_set_max; i++) { ++ set = ip_set(inst, i); ++ if (set) { ++ ip_set(inst, i) = NULL; ++ set->variant->destroy(set); ++ module_put(set->type->me); ++ kfree(set); ++ } ++ } + } + + static int ip_set_destroy(struct net *net, struct sock *ctnl, +@@ -1208,11 +1235,10 @@ static int ip_set_destroy(struct net *net, struct sock *ctnl, + if (unlikely(protocol_min_failed(attr))) + return -IPSET_ERR_PROTOCOL; + +- + /* Commands are serialized and references are + * protected by the ip_set_ref_lock. + * External systems (i.e. xt_set) must call +- * ip_set_put|get_nfnl_* functions, that way we ++ * ip_set_nfnl_get_* functions, that way we + * can safely check references here. + * + * list:set timer can only decrement the reference +@@ -1220,8 +1246,6 @@ static int ip_set_destroy(struct net *net, struct sock *ctnl, + * without holding the lock. + */ + if (!attr[IPSET_ATTR_SETNAME]) { +- /* Must wait for flush to be really finished in list:set */ +- rcu_barrier(); + read_lock_bh(&ip_set_ref_lock); + for (i = 0; i < inst->ip_set_max; i++) { + s = ip_set(inst, i); +@@ -1232,15 +1256,7 @@ static int ip_set_destroy(struct net *net, struct sock *ctnl, + } + inst->is_destroyed = true; + read_unlock_bh(&ip_set_ref_lock); +- for (i = 0; i < inst->ip_set_max; i++) { +- s = ip_set(inst, i); +- if (s) { +- ip_set(inst, i) = NULL; +- /* Must cancel garbage collectors */ +- s->variant->cancel_gc(s); +- ip_set_destroy_set(s); +- } +- } ++ _destroy_all_sets(inst); + /* Modified by ip_set_destroy() only, which is serialized */ + inst->is_destroyed = false; + } else { +@@ -1259,12 +1275,12 @@ static int ip_set_destroy(struct net *net, struct sock *ctnl, + features = s->type->features; + ip_set(inst, i) = NULL; + read_unlock_bh(&ip_set_ref_lock); ++ /* Must cancel garbage collectors */ ++ s->variant->cancel_gc(s); + if (features & IPSET_TYPE_NAME) { + /* Must wait for flush to be really finished */ + rcu_barrier(); + } +- /* Must cancel garbage collectors */ +- s->variant->cancel_gc(s); + call_rcu(&s->rcu, ip_set_destroy_set_rcu); + } + return 0; +@@ -2400,30 +2416,25 @@ ip_set_net_init(struct net *net) + } + + static void __net_exit +-ip_set_net_exit(struct net *net) ++ip_set_net_pre_exit(struct net *net) + { + struct ip_set_net *inst = ip_set_pernet(net); + +- struct ip_set *set = NULL; +- ip_set_id_t i; +- + inst->is_deleted = true; /* flag for ip_set_nfnl_put */ ++} + +- nfnl_lock(NFNL_SUBSYS_IPSET); +- for (i = 0; i < inst->ip_set_max; i++) { +- set = ip_set(inst, i); +- if (set) { +- ip_set(inst, i) = NULL; +- set->variant->cancel_gc(set); +- ip_set_destroy_set(set); +- } +- } +- nfnl_unlock(NFNL_SUBSYS_IPSET); ++static void __net_exit ++ip_set_net_exit(struct net *net) ++{ ++ struct ip_set_net *inst = ip_set_pernet(net); ++ ++ _destroy_all_sets(inst); + kvfree(rcu_dereference_protected(inst->ip_set_list, 1)); + } + + static struct pernet_operations ip_set_net_ops = { + .init = ip_set_net_init, ++ .pre_exit = ip_set_net_pre_exit, + .exit = ip_set_net_exit, + .id = &ip_set_net_id, + .size = sizeof(struct ip_set_net), +diff --git a/net/netfilter/ipset/ip_set_list_set.c b/net/netfilter/ipset/ip_set_list_set.c +index 6bc7019982b05..e839c356bcb56 100644 +--- a/net/netfilter/ipset/ip_set_list_set.c ++++ b/net/netfilter/ipset/ip_set_list_set.c +@@ -79,7 +79,7 @@ list_set_kadd(struct ip_set *set, const struct sk_buff *skb, + struct set_elem *e; + int ret; + +- list_for_each_entry(e, &map->members, list) { ++ list_for_each_entry_rcu(e, &map->members, list) { + if (SET_WITH_TIMEOUT(set) && + ip_set_timeout_expired(ext_timeout(e, set))) + continue; +@@ -99,7 +99,7 @@ list_set_kdel(struct ip_set *set, const struct sk_buff *skb, + struct set_elem *e; + int ret; + +- list_for_each_entry(e, &map->members, list) { ++ list_for_each_entry_rcu(e, &map->members, list) { + if (SET_WITH_TIMEOUT(set) && + ip_set_timeout_expired(ext_timeout(e, set))) + continue; +@@ -188,9 +188,10 @@ list_set_utest(struct ip_set *set, void *value, const struct ip_set_ext *ext, + struct list_set *map = set->data; + struct set_adt_elem *d = value; + struct set_elem *e, *next, *prev = NULL; +- int ret; ++ int ret = 0; + +- list_for_each_entry(e, &map->members, list) { ++ rcu_read_lock(); ++ list_for_each_entry_rcu(e, &map->members, list) { + if (SET_WITH_TIMEOUT(set) && + ip_set_timeout_expired(ext_timeout(e, set))) + continue; +@@ -201,6 +202,7 @@ list_set_utest(struct ip_set *set, void *value, const struct ip_set_ext *ext, + + if (d->before == 0) { + ret = 1; ++ goto out; + } else if (d->before > 0) { + next = list_next_entry(e, list); + ret = !list_is_last(&e->list, &map->members) && +@@ -208,9 +210,11 @@ list_set_utest(struct ip_set *set, void *value, const struct ip_set_ext *ext, + } else { + ret = prev && prev->id == d->refid; + } +- return ret; ++ goto out; + } +- return 0; ++out: ++ rcu_read_unlock(); ++ return ret; + } + + static void +@@ -239,7 +243,7 @@ list_set_uadd(struct ip_set *set, void *value, const struct ip_set_ext *ext, + + /* Find where to add the new entry */ + n = prev = next = NULL; +- list_for_each_entry(e, &map->members, list) { ++ list_for_each_entry_rcu(e, &map->members, list) { + if (SET_WITH_TIMEOUT(set) && + ip_set_timeout_expired(ext_timeout(e, set))) + continue; +@@ -316,9 +320,9 @@ list_set_udel(struct ip_set *set, void *value, const struct ip_set_ext *ext, + { + struct list_set *map = set->data; + struct set_adt_elem *d = value; +- struct set_elem *e, *next, *prev = NULL; ++ struct set_elem *e, *n, *next, *prev = NULL; + +- list_for_each_entry(e, &map->members, list) { ++ list_for_each_entry_safe(e, n, &map->members, list) { + if (SET_WITH_TIMEOUT(set) && + ip_set_timeout_expired(ext_timeout(e, set))) + continue; +@@ -424,14 +428,8 @@ static void + list_set_destroy(struct ip_set *set) + { + struct list_set *map = set->data; +- struct set_elem *e, *n; + +- list_for_each_entry_safe(e, n, &map->members, list) { +- list_del(&e->list); +- ip_set_put_byindex(map->net, e->id); +- ip_set_ext_destroy(set, e); +- kfree(e); +- } ++ WARN_ON_ONCE(!list_empty(&map->members)); + kfree(map); + + set->data = NULL; +-- +2.43.0 + diff --git a/queue-5.10/netfilter-use-flowlabel-flow-key-when-re-routing-man.patch b/queue-5.10/netfilter-use-flowlabel-flow-key-when-re-routing-man.patch new file mode 100644 index 00000000000..1680481a954 --- /dev/null +++ b/queue-5.10/netfilter-use-flowlabel-flow-key-when-re-routing-man.patch @@ -0,0 +1,41 @@ +From 162dce55343613c51ed97a047df9c5b0f61b138c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 6 Jun 2024 12:23:31 +0200 +Subject: netfilter: Use flowlabel flow key when re-routing mangled packets + +From: Florian Westphal + +[ Upstream commit 6f8f132cc7bac2ac76911e47d5baa378aafda4cb ] + +'ip6 dscp set $v' in an nftables outpute route chain has no effect. +While nftables does detect the dscp change and calls the reroute hook. +But ip6_route_me_harder never sets the dscp/flowlabel: +flowlabel/dsfield routing rules are ignored and no reroute takes place. + +Thanks to Yi Chen for an excellent reproducer script that I used +to validate this change. + +Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") +Reported-by: Yi Chen +Signed-off-by: Florian Westphal +Signed-off-by: Pablo Neira Ayuso +Signed-off-by: Sasha Levin +--- + net/ipv6/netfilter.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/net/ipv6/netfilter.c b/net/ipv6/netfilter.c +index ab9a279dd6d47..ef06d248c3c3d 100644 +--- a/net/ipv6/netfilter.c ++++ b/net/ipv6/netfilter.c +@@ -35,6 +35,7 @@ int ip6_route_me_harder(struct net *net, struct sock *sk_partial, struct sk_buff + .flowi6_uid = sock_net_uid(net, sk), + .daddr = iph->daddr, + .saddr = iph->saddr, ++ .flowlabel = ip6_flowinfo(iph), + }; + int err; + +-- +2.43.0 + diff --git a/queue-5.10/series b/queue-5.10/series index d8d818825c6..1633050051c 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -65,3 +65,37 @@ xhci-apply-broken-streams-quirk-to-etron-ej188-xhci-host.patch scsi-mpt3sas-avoid-test-set_bit-operating-in-non-allocated-memory.patch powerpc-uaccess-fix-build-errors-seen-with-gcc-13-14.patch input-try-trimming-too-long-modalias-strings.patch +clk-sifive-extract-prci-core-to-common-base.patch +clk-sifive-do-not-register-clkdevs-for-prci-clocks.patch +sunrpc-return-proper-error-from-gss_wrap_req_priv.patch +gpio-tqmx86-fix-typo-in-kconfig-label.patch +gpio-tqmx86-remove-unneeded-call-to-platform_set_drv.patch +gpio-tqmx86-introduce-shadow-register-for-gpio-outpu.patch +genirq-allow-the-pm-device-to-originate-from-irq-dom.patch +gpio-tpmx86-move-pm-device-over-to-irq-domain.patch +gpio-don-t-fiddle-with-irqchips-marked-as-immutable.patch +gpio-expose-the-gpiochip_irq_re-ql-res-helpers.patch +gpio-add-helpers-to-ease-the-transition-towards-immu.patch +gpio-tqmx86-convert-to-immutable-irq_chip.patch +gpio-tqmx86-store-irq-trigger-type-and-unmask-status.patch +hid-core-remove-unnecessary-warn_on-in-implement.patch +iommu-amd-introduce-pci-segment-structure.patch +iommu-amd-fix-sysfs-leak-in-iommu-init.patch +iommu-return-right-value-in-iommu_sva_bind_device.patch +hid-logitech-dj-fix-memory-leak-in-logi_dj_recv_swit.patch +drm-vmwgfx-3d-disabled-should-not-effect-stdu-memory.patch +net-sfp-always-call-sfp_sm_mod_remove-on-remove.patch +net-hns3-add-cond_resched-to-hns3-ring-buffer-init-p.patch +liquidio-adjust-a-null-pointer-handling-path-in-lio_.patch +drm-komeda-check-for-error-valued-pointer.patch +drm-bridge-panel-fix-runtime-warning-on-panel-bridge.patch +tcp-fix-race-in-tcp_v6_syn_recv_sock.patch +net-geneve-support-ipv4-ipv6-as-inner-protocol.patch +geneve-fix-incorrect-inner-network-header-offset-whe.patch +net-mlx5e-fix-features-validation-check-for-tunneled.patch +bluetooth-l2cap-fix-rejecting-l2cap_conn_param_updat.patch +netfilter-ipset-fix-race-between-namespace-cleanup-a.patch +netfilter-use-flowlabel-flow-key-when-re-routing-man.patch +net-stmmac-replace-priv-speed-with-the-porttransmitr.patch +net-ipv6-fix-the-rt-cache-flush-via-sysctl-using-a-p.patch +ionic-fix-use-after-netif_napi_del.patch diff --git a/queue-5.10/sunrpc-return-proper-error-from-gss_wrap_req_priv.patch b/queue-5.10/sunrpc-return-proper-error-from-gss_wrap_req_priv.patch new file mode 100644 index 00000000000..3058fa86700 --- /dev/null +++ b/queue-5.10/sunrpc-return-proper-error-from-gss_wrap_req_priv.patch @@ -0,0 +1,40 @@ +From dd71d24e9009020320cd6e88f8f42dd058fb3275 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 23 May 2024 16:47:16 +0800 +Subject: SUNRPC: return proper error from gss_wrap_req_priv + +From: Chen Hanxiao + +[ Upstream commit 33c94d7e3cb84f6d130678d6d59ba475a6c489cf ] + +don't return 0 if snd_buf->len really greater than snd_buf->buflen + +Signed-off-by: Chen Hanxiao +Fixes: 0c77668ddb4e ("SUNRPC: Introduce trace points in rpc_auth_gss.ko") +Reviewed-by: Benjamin Coddington +Reviewed-by: Chuck Lever +Signed-off-by: Trond Myklebust +Signed-off-by: Sasha Levin +--- + net/sunrpc/auth_gss/auth_gss.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/net/sunrpc/auth_gss/auth_gss.c b/net/sunrpc/auth_gss/auth_gss.c +index 2ff66a6a7e54c..7ce4a6b7cfae6 100644 +--- a/net/sunrpc/auth_gss/auth_gss.c ++++ b/net/sunrpc/auth_gss/auth_gss.c +@@ -1855,8 +1855,10 @@ gss_wrap_req_priv(struct rpc_cred *cred, struct gss_cl_ctx *ctx, + offset = (u8 *)p - (u8 *)snd_buf->head[0].iov_base; + maj_stat = gss_wrap(ctx->gc_gss_ctx, offset, snd_buf, inpages); + /* slack space should prevent this ever happening: */ +- if (unlikely(snd_buf->len > snd_buf->buflen)) ++ if (unlikely(snd_buf->len > snd_buf->buflen)) { ++ status = -EIO; + goto wrap_failed; ++ } + /* We're assuming that when GSS_S_CONTEXT_EXPIRED, the encryption was + * done anyway, so it's safe to put the request on the wire: */ + if (maj_stat == GSS_S_CONTEXT_EXPIRED) +-- +2.43.0 + diff --git a/queue-5.10/tcp-fix-race-in-tcp_v6_syn_recv_sock.patch b/queue-5.10/tcp-fix-race-in-tcp_v6_syn_recv_sock.patch new file mode 100644 index 00000000000..bc593431a4d --- /dev/null +++ b/queue-5.10/tcp-fix-race-in-tcp_v6_syn_recv_sock.patch @@ -0,0 +1,54 @@ +From 6203bf74a5606a740184fa736af8208ba3facb8a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 6 Jun 2024 15:46:51 +0000 +Subject: tcp: fix race in tcp_v6_syn_recv_sock() + +From: Eric Dumazet + +[ Upstream commit d37fe4255abe8e7b419b90c5847e8ec2b8debb08 ] + +tcp_v6_syn_recv_sock() calls ip6_dst_store() before +inet_sk(newsk)->pinet6 has been set up. + +This means ip6_dst_store() writes over the parent (listener) +np->dst_cookie. + +This is racy because multiple threads could share the same +parent and their final np->dst_cookie could be wrong. + +Move ip6_dst_store() call after inet_sk(newsk)->pinet6 +has been changed and after the copy of parent ipv6_pinfo. + +Fixes: e994b2f0fb92 ("tcp: do not lock listener to process SYN packets") +Signed-off-by: Eric Dumazet +Reviewed-by: Simon Horman +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + net/ipv6/tcp_ipv6.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c +index 79d6f6ea3c546..003221d6f52e9 100644 +--- a/net/ipv6/tcp_ipv6.c ++++ b/net/ipv6/tcp_ipv6.c +@@ -1311,7 +1311,6 @@ static struct sock *tcp_v6_syn_recv_sock(const struct sock *sk, struct sk_buff * + */ + + newsk->sk_gso_type = SKB_GSO_TCPV6; +- ip6_dst_store(newsk, dst, NULL, NULL); + inet6_sk_rx_dst_set(newsk, skb); + + inet_sk(newsk)->pinet6 = tcp_inet6_sk(newsk); +@@ -1322,6 +1321,8 @@ static struct sock *tcp_v6_syn_recv_sock(const struct sock *sk, struct sk_buff * + + memcpy(newnp, np, sizeof(struct ipv6_pinfo)); + ++ ip6_dst_store(newsk, dst, NULL, NULL); ++ + newsk->sk_v6_daddr = ireq->ir_v6_rmt_addr; + newnp->saddr = ireq->ir_v6_loc_addr; + newsk->sk_v6_rcv_saddr = ireq->ir_v6_loc_addr; +-- +2.43.0 +