From: Greg Kroah-Hartman Date: Sat, 23 May 2020 12:28:57 +0000 (+0200) Subject: 4.19-stable patches X-Git-Tag: v4.4.225~44 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=0fa5f7c88b6beb8d477df1cac326724049e8a9f5;p=thirdparty%2Fkernel%2Fstable-queue.git 4.19-stable patches added patches: drm-i915-gvt-init-dpll-ddi-vreg-for-virtual-display-instead-of-inheritance.patch --- diff --git a/queue-4.19/drm-i915-gvt-init-dpll-ddi-vreg-for-virtual-display-instead-of-inheritance.patch b/queue-4.19/drm-i915-gvt-init-dpll-ddi-vreg-for-virtual-display-instead-of-inheritance.patch new file mode 100644 index 00000000000..3547c2eefac --- /dev/null +++ b/queue-4.19/drm-i915-gvt-init-dpll-ddi-vreg-for-virtual-display-instead-of-inheritance.patch @@ -0,0 +1,103 @@ +From f965b68188ab59a40a421ced1b05a2fea638465c Mon Sep 17 00:00:00 2001 +From: Colin Xu +Date: Fri, 8 May 2020 14:05:06 +0800 +Subject: drm/i915/gvt: Init DPLL/DDI vreg for virtual display instead of inheritance. + +From: Colin Xu + +commit f965b68188ab59a40a421ced1b05a2fea638465c upstream. + +Init value of some display vregs rea inherited from host pregs. When +host display in different status, i.e. all monitors unpluged, different +display configurations, etc., GVT virtual display setup don't consistent +thus may lead to guest driver consider display goes malfunctional. + +The added init vreg values are based on PRMs and fixed by calcuation +from current configuration (only PIPE_A) and the virtual EDID. + +Fixes: 04d348ae3f0a ("drm/i915/gvt: vGPU display virtualization") +Acked-by: Zhenyu Wang +Signed-off-by: Colin Xu +Signed-off-by: Zhenyu Wang +Link: http://patchwork.freedesktop.org/patch/msgid/20200508060506.216250-1-colin.xu@intel.com +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/gvt/display.c | 49 +++++++++++++++++++++++++++++++++---- + 1 file changed, 44 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/i915/gvt/display.c ++++ b/drivers/gpu/drm/i915/gvt/display.c +@@ -206,14 +206,41 @@ static void emulate_monitor_status_chang + SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | + SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | + SKL_FUSE_PG_DIST_STATUS(SKL_PG2); +- vgpu_vreg_t(vgpu, LCPLL1_CTL) |= +- LCPLL_PLL_ENABLE | +- LCPLL_PLL_LOCK; +- vgpu_vreg_t(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE; +- ++ /* ++ * Only 1 PIPE enabled in current vGPU display and PIPE_A is ++ * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, ++ * TRANSCODER_A can be enabled. PORT_x depends on the input of ++ * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x ++ * so we fixed to DPLL0 here. ++ * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode ++ */ ++ vgpu_vreg_t(vgpu, DPLL_CTRL1) = ++ DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0); ++ vgpu_vreg_t(vgpu, DPLL_CTRL1) |= ++ DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0); ++ vgpu_vreg_t(vgpu, LCPLL1_CTL) = ++ LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; ++ vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); ++ /* ++ * Golden M/N are calculated based on: ++ * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), ++ * DP link clk 1620 MHz and non-constant_n. ++ * TODO: calculate DP link symbol clk and stream clk m/n. ++ */ ++ vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT; ++ vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; ++ vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; ++ vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; ++ vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; + } + + if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { ++ vgpu_vreg_t(vgpu, DPLL_CTRL2) &= ++ ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); ++ vgpu_vreg_t(vgpu, DPLL_CTRL2) |= ++ DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B); ++ vgpu_vreg_t(vgpu, DPLL_CTRL2) |= ++ DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); + vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= + ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | +@@ -234,6 +261,12 @@ static void emulate_monitor_status_chang + } + + if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { ++ vgpu_vreg_t(vgpu, DPLL_CTRL2) &= ++ ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C); ++ vgpu_vreg_t(vgpu, DPLL_CTRL2) |= ++ DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C); ++ vgpu_vreg_t(vgpu, DPLL_CTRL2) |= ++ DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C); + vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= + ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | +@@ -254,6 +287,12 @@ static void emulate_monitor_status_chang + } + + if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { ++ vgpu_vreg_t(vgpu, DPLL_CTRL2) &= ++ ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D); ++ vgpu_vreg_t(vgpu, DPLL_CTRL2) |= ++ DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D); ++ vgpu_vreg_t(vgpu, DPLL_CTRL2) |= ++ DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D); + vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= + ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | diff --git a/queue-4.19/series b/queue-4.19/series index b4dfc4d3ccc..7089bce54ce 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -43,3 +43,4 @@ apparmor-fix-potential-label-refcnt-leak-in-aa_change_profile.patch apparmor-fix-aa_label-refcnt-leak-in-policy_update.patch dmaengine-tegra210-adma-fix-an-error-handling-path-in-tegra_adma_probe.patch dmaengine-owl-use-correct-lock-in-owl_dma_get_pchan.patch +drm-i915-gvt-init-dpll-ddi-vreg-for-virtual-display-instead-of-inheritance.patch