From: Arun R Murthy Date: Mon, 16 Feb 2026 04:59:39 +0000 (+0530) Subject: drm/i915/cx0_phy_regs: Include SoC and OS turnaround time X-Git-Tag: v7.1-rc1~167^2~24^2~129 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=122439234f6ae2583a3701d7619f9a8242748547;p=thirdparty%2Flinux.git drm/i915/cx0_phy_regs: Include SoC and OS turnaround time The port refclk enable timeout and the soc ready timeout value mentioned in the spec is the PHY timings and doesn't include the turnaround time from the SoC or OS. So add an overhead timeout value on top of the recommended timeouts from the PHY spec. The overhead value is based on the stress test results with multiple available panels. Reported-by: Cole Leavitt Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14713 Signed-off-by: Arun R Murthy Reviewed-by: Suraj Kandpal Signed-off-by: Suraj Kandpal Link: https://patch.msgid.link/20260216-timeout-v3-1-055522c22560@intel.com --- diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index 658890f735153..152a4e751bdcf 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -78,10 +78,10 @@ #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200 #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20 #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100 -#define XELPDP_PORT_RESET_START_TIMEOUT_US 5 +#define XELPDP_PORT_RESET_START_TIMEOUT_US 10 #define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS 2 #define XELPDP_PORT_RESET_END_TIMEOUT_MS 15 -#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1 +#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 10 #define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004 #define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104