From: Sasha Levin Date: Fri, 6 Oct 2023 14:12:46 +0000 (-0400) Subject: Fixes for 6.5 X-Git-Tag: v4.14.327~87 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=13a914acf4ec5dd18a196b3ef668d0b8e9f19f98;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 6.5 Signed-off-by: Sasha Levin --- diff --git a/queue-6.5/iommu-arm-smmu-v3-avoid-constructing-invalid-range-c.patch b/queue-6.5/iommu-arm-smmu-v3-avoid-constructing-invalid-range-c.patch new file mode 100644 index 00000000000..51416dc6b35 --- /dev/null +++ b/queue-6.5/iommu-arm-smmu-v3-avoid-constructing-invalid-range-c.patch @@ -0,0 +1,65 @@ +From 01677bb10dd0d92b48a6f1636bef92118c34f9cc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 11 Sep 2023 12:57:04 +0100 +Subject: iommu/arm-smmu-v3: Avoid constructing invalid range commands + +From: Robin Murphy + +[ Upstream commit eb6c97647be227822c7ce23655482b05e348fba5 ] + +Although io-pgtable's non-leaf invalidations are always for full tables, +I missed that SVA also uses non-leaf invalidations, while being at the +mercy of whatever range the MMU notifier throws at it. This means it +definitely wants the previous TTL fix as well, since it also doesn't +know exactly which leaf level(s) may need invalidating, but it can also +give us less-aligned ranges wherein certain corners may lead to building +an invalid command where TTL, Num and Scale are all 0. It should be fine +to handle this by over-invalidating an extra page, since falling back to +a non-range command opens up a whole can of errata-flavoured worms. + +Fixes: 6833b8f2e199 ("iommu/arm-smmu-v3: Set TTL invalidation hint better") +Reported-by: Rui Zhu +Signed-off-by: Robin Murphy +Link: https://lore.kernel.org/r/b99cfe71af2bd93a8a2930f20967fb2a4f7748dd.1694432734.git.robin.murphy@arm.com +Signed-off-by: Will Deacon +Signed-off-by: Sasha Levin +--- + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 15 ++++++++++----- + 1 file changed, 10 insertions(+), 5 deletions(-) + +diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +index 9b0dc35056019..6ccbae9b93a14 100644 +--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c ++++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +@@ -1895,18 +1895,23 @@ static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, + /* Get the leaf page size */ + tg = __ffs(smmu_domain->domain.pgsize_bitmap); + ++ num_pages = size >> tg; ++ + /* Convert page size of 12,14,16 (log2) to 1,2,3 */ + cmd->tlbi.tg = (tg - 10) / 2; + + /* +- * Determine what level the granule is at. For non-leaf, io-pgtable +- * assumes .tlb_flush_walk can invalidate multiple levels at once, +- * so ignore the nominal last-level granule and leave TTL=0. ++ * Determine what level the granule is at. For non-leaf, both ++ * io-pgtable and SVA pass a nominal last-level granule because ++ * they don't know what level(s) actually apply, so ignore that ++ * and leave TTL=0. However for various errata reasons we still ++ * want to use a range command, so avoid the SVA corner case ++ * where both scale and num could be 0 as well. + */ + if (cmd->tlbi.leaf) + cmd->tlbi.ttl = 4 - ((ilog2(granule) - 3) / (tg - 3)); +- +- num_pages = size >> tg; ++ else if ((num_pages & CMDQ_TLBI_RANGE_NUM_MAX) == 1) ++ num_pages++; + } + + cmds.num = 0; +-- +2.40.1 + diff --git a/queue-6.5/series b/queue-6.5/series index 3e5de618262..28fe3719714 100644 --- a/queue-6.5/series +++ b/queue-6.5/series @@ -17,3 +17,4 @@ btrfs-remove-end_extent_writepage.patch btrfs-don-t-clear-uptodate-on-write-errors.patch arm64-add-hwcap-for-feat_hbc-hinted-conditional-bran.patch arm64-cpufeature-fix-clrbhb-and-bc-detection.patch +iommu-arm-smmu-v3-avoid-constructing-invalid-range-c.patch