From: Greg Kroah-Hartman Date: Mon, 17 May 2021 13:05:57 +0000 (+0200) Subject: 4.9-stable patches X-Git-Tag: v5.4.120~9 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=1450841d19c09aad3fd95001ff607d7994a46424;p=thirdparty%2Fkernel%2Fstable-queue.git 4.9-stable patches added patches: clk-exynos7-mark-aclk_fsys1_200-as-critical.patch --- diff --git a/queue-4.9/clk-exynos7-mark-aclk_fsys1_200-as-critical.patch b/queue-4.9/clk-exynos7-mark-aclk_fsys1_200-as-critical.patch new file mode 100644 index 00000000000..cc004b175dd --- /dev/null +++ b/queue-4.9/clk-exynos7-mark-aclk_fsys1_200-as-critical.patch @@ -0,0 +1,50 @@ +From 34138a59b92c1a30649a18ec442d2e61f3bc34dd Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pawe=C5=82=20Chmiel?= +Date: Sat, 24 Oct 2020 17:43:46 +0200 +Subject: clk: exynos7: Mark aclk_fsys1_200 as critical +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Paweł Chmiel + +commit 34138a59b92c1a30649a18ec442d2e61f3bc34dd upstream. + +This clock must be always enabled to allow access to any registers in +fsys1 CMU. Until proper solution based on runtime PM is applied +(similar to what was done for Exynos5433), mark that clock as critical +so it won't be disabled. + +It was observed on Samsung Galaxy S6 device (based on Exynos7420), where +UFS module is probed before pmic used to power that device. +In this case defer probe was happening and that clock was disabled by +UFS driver, causing whole boot to hang on next CMU access. + +Fixes: 753195a749a6 ("clk: samsung: exynos7: Correct CMU_FSYS1 clocks names") +Signed-off-by: Paweł Chmiel +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/linux-clk/20201024154346.9589-1-pawel.mikolaj.chmiel@gmail.com +[s.nawrocki: Added comment in the code] +Signed-off-by: Sylwester Nawrocki +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/samsung/clk-exynos7.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +--- a/drivers/clk/samsung/clk-exynos7.c ++++ b/drivers/clk/samsung/clk-exynos7.c +@@ -541,8 +541,13 @@ static const struct samsung_gate_clock t + GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200", + ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL, 0), ++ /* ++ * This clock is required for the CMU_FSYS1 registers access, keep it ++ * enabled permanently until proper runtime PM support is added. ++ */ + GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200", +- ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0), ++ ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT | ++ CLK_IS_CRITICAL, 0), + + GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m", + "dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11, diff --git a/queue-4.9/series b/queue-4.9/series index 5b6a65b2dbe..0b0cdd16c39 100644 --- a/queue-4.9/series +++ b/queue-4.9/series @@ -220,3 +220,4 @@ thermal-core-fair-share-lock-the-thermal-zone-while-looping-over-instances.patch dm-ioctl-fix-out-of-bounds-array-access-when-no-devices.patch kobject_uevent-remove-warning-in-init_uevent_argv.patch netfilter-conntrack-make-global-sysctls-readonly-in-non-init-netns.patch +clk-exynos7-mark-aclk_fsys1_200-as-critical.patch