From: Greg Kroah-Hartman Date: Fri, 21 Jul 2023 06:35:19 +0000 (+0200) Subject: 4.19-stable patches X-Git-Tag: v5.15.121~67 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=168a32a8bb4989a7d1c76639824e4f7f3f754a4d;p=thirdparty%2Fkernel%2Fstable-queue.git 4.19-stable patches added patches: ext4-fix-to-check-return-value-of-freeze_bdev-in-ext4_shutdown.patch ext4-fix-wrong-unit-use-in-ext4_mb_clear_bb.patch ext4-only-update-i_reserved_data_blocks-on-successful-block-allocation.patch jfs-jfs_dmap-validate-db_l2nbperpage-while-mounting.patch pci-acpiphp-reassign-resources-on-bridge-if-necessary.patch pci-add-function-1-dma-alias-quirk-for-marvell-88se9235.patch pci-pm-avoid-putting-elopos-e2-s2-h2-pcie-ports-in-d3cold.patch pci-qcom-disable-write-access-to-read-only-registers-for-ip-v2.3.3.patch pci-rockchip-add-poll-and-timeout-to-wait-for-phy-plls-to-be-locked.patch pci-rockchip-assert-pci-configuration-enable-bit-after-probe.patch pci-rockchip-fix-legacy-irq-generation-for-rk3399-pcie-endpoint-core.patch pci-rockchip-use-u32-variable-to-access-32-bit-registers.patch pci-rockchip-write-pci-device-id-to-correct-register.patch --- diff --git a/queue-4.19/ext4-fix-to-check-return-value-of-freeze_bdev-in-ext4_shutdown.patch b/queue-4.19/ext4-fix-to-check-return-value-of-freeze_bdev-in-ext4_shutdown.patch new file mode 100644 index 00000000000..2d7511bc7e1 --- /dev/null +++ b/queue-4.19/ext4-fix-to-check-return-value-of-freeze_bdev-in-ext4_shutdown.patch @@ -0,0 +1,43 @@ +From c4d13222afd8a64bf11bc7ec68645496ee8b54b9 Mon Sep 17 00:00:00 2001 +From: Chao Yu +Date: Tue, 6 Jun 2023 15:32:03 +0800 +Subject: ext4: fix to check return value of freeze_bdev() in ext4_shutdown() + +From: Chao Yu + +commit c4d13222afd8a64bf11bc7ec68645496ee8b54b9 upstream. + +freeze_bdev() can fail due to a lot of reasons, it needs to check its +reason before later process. + +Fixes: 783d94854499 ("ext4: add EXT4_IOC_GOINGDOWN ioctl") +Cc: stable@kernel.org +Signed-off-by: Chao Yu +Link: https://lore.kernel.org/r/20230606073203.1310389-1-chao@kernel.org +Signed-off-by: Theodore Ts'o +Signed-off-by: Greg Kroah-Hartman +--- + fs/ext4/ioctl.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/fs/ext4/ioctl.c ++++ b/fs/ext4/ioctl.c +@@ -561,6 +561,7 @@ static int ext4_shutdown(struct super_bl + { + struct ext4_sb_info *sbi = EXT4_SB(sb); + __u32 flags; ++ int ret; + + if (!capable(CAP_SYS_ADMIN)) + return -EPERM; +@@ -579,7 +580,9 @@ static int ext4_shutdown(struct super_bl + + switch (flags) { + case EXT4_GOING_FLAGS_DEFAULT: +- freeze_bdev(sb->s_bdev); ++ ret = freeze_bdev(sb->s_bdev); ++ if (ret) ++ return ret; + set_bit(EXT4_FLAGS_SHUTDOWN, &sbi->s_ext4_flags); + thaw_bdev(sb->s_bdev, sb); + break; diff --git a/queue-4.19/ext4-fix-wrong-unit-use-in-ext4_mb_clear_bb.patch b/queue-4.19/ext4-fix-wrong-unit-use-in-ext4_mb_clear_bb.patch new file mode 100644 index 00000000000..e95434c2809 --- /dev/null +++ b/queue-4.19/ext4-fix-wrong-unit-use-in-ext4_mb_clear_bb.patch @@ -0,0 +1,35 @@ +From 247c3d214c23dfeeeb892e91a82ac1188bdaec9f Mon Sep 17 00:00:00 2001 +From: Kemeng Shi +Date: Sat, 3 Jun 2023 23:03:18 +0800 +Subject: ext4: fix wrong unit use in ext4_mb_clear_bb + +From: Kemeng Shi + +commit 247c3d214c23dfeeeb892e91a82ac1188bdaec9f upstream. + +Function ext4_issue_discard need count in cluster. Pass count_clusters +instead of count to fix the mismatch. + +Signed-off-by: Kemeng Shi +Cc: stable@kernel.org +Reviewed-by: Ojaswin Mujoo +Link: https://lore.kernel.org/r/20230603150327.3596033-11-shikemeng@huaweicloud.com +Signed-off-by: Theodore Ts'o +Signed-off-by: Greg Kroah-Hartman +--- + fs/ext4/mballoc.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/fs/ext4/mballoc.c ++++ b/fs/ext4/mballoc.c +@@ -4948,8 +4948,8 @@ do_more: + * them with group lock_held + */ + if (test_opt(sb, DISCARD)) { +- err = ext4_issue_discard(sb, block_group, bit, count, +- NULL); ++ err = ext4_issue_discard(sb, block_group, bit, ++ count_clusters, NULL); + if (err && err != -EOPNOTSUPP) + ext4_msg(sb, KERN_WARNING, "discard request in" + " group:%d block:%d count:%lu failed" diff --git a/queue-4.19/ext4-only-update-i_reserved_data_blocks-on-successful-block-allocation.patch b/queue-4.19/ext4-only-update-i_reserved_data_blocks-on-successful-block-allocation.patch new file mode 100644 index 00000000000..b3c565d8dd9 --- /dev/null +++ b/queue-4.19/ext4-only-update-i_reserved_data_blocks-on-successful-block-allocation.patch @@ -0,0 +1,92 @@ +From de25d6e9610a8b30cce9bbb19b50615d02ebca02 Mon Sep 17 00:00:00 2001 +From: Baokun Li +Date: Mon, 24 Apr 2023 11:38:35 +0800 +Subject: ext4: only update i_reserved_data_blocks on successful block allocation + +From: Baokun Li + +commit de25d6e9610a8b30cce9bbb19b50615d02ebca02 upstream. + +In our fault injection test, we create an ext4 file, migrate it to +non-extent based file, then punch a hole and finally trigger a WARN_ON +in the ext4_da_update_reserve_space(): + +EXT4-fs warning (device sda): ext4_da_update_reserve_space:369: +ino 14, used 11 with only 10 reserved data blocks + +When writing back a non-extent based file, if we enable delalloc, the +number of reserved blocks will be subtracted from the number of blocks +mapped by ext4_ind_map_blocks(), and the extent status tree will be +updated. We update the extent status tree by first removing the old +extent_status and then inserting the new extent_status. If the block range +we remove happens to be in an extent, then we need to allocate another +extent_status with ext4_es_alloc_extent(). + + use old to remove to add new + |----------|------------|------------| + old extent_status + +The problem is that the allocation of a new extent_status failed due to a +fault injection, and __es_shrink() did not get free memory, resulting in +a return of -ENOMEM. Then do_writepages() retries after receiving -ENOMEM, +we map to the same extent again, and the number of reserved blocks is again +subtracted from the number of blocks in that extent. Since the blocks in +the same extent are subtracted twice, we end up triggering WARN_ON at +ext4_da_update_reserve_space() because used > ei->i_reserved_data_blocks. + +For non-extent based file, we update the number of reserved blocks after +ext4_ind_map_blocks() is executed, which causes a problem that when we call +ext4_ind_map_blocks() to create a block, it doesn't always create a block, +but we always reduce the number of reserved blocks. So we move the logic +for updating reserved blocks to ext4_ind_map_blocks() to ensure that the +number of reserved blocks is updated only after we do succeed in allocating +some new blocks. + +Fixes: 5f634d064c70 ("ext4: Fix quota accounting error with fallocate") +Cc: stable@kernel.org +Signed-off-by: Baokun Li +Reviewed-by: Jan Kara +Link: https://lore.kernel.org/r/20230424033846.4732-2-libaokun1@huawei.com +Signed-off-by: Theodore Ts'o +Signed-off-by: Greg Kroah-Hartman +--- + fs/ext4/indirect.c | 8 ++++++++ + fs/ext4/inode.c | 10 ---------- + 2 files changed, 8 insertions(+), 10 deletions(-) + +--- a/fs/ext4/indirect.c ++++ b/fs/ext4/indirect.c +@@ -642,6 +642,14 @@ int ext4_ind_map_blocks(handle_t *handle + + ext4_update_inode_fsync_trans(handle, inode, 1); + count = ar.len; ++ ++ /* ++ * Update reserved blocks/metadata blocks after successful block ++ * allocation which had been deferred till now. ++ */ ++ if (flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE) ++ ext4_da_update_reserve_space(inode, count, 1); ++ + got_it: + map->m_flags |= EXT4_MAP_MAPPED; + map->m_pblk = le32_to_cpu(chain[depth-1].key); +--- a/fs/ext4/inode.c ++++ b/fs/ext4/inode.c +@@ -668,16 +668,6 @@ found: + */ + ext4_clear_inode_state(inode, EXT4_STATE_EXT_MIGRATE); + } +- +- /* +- * Update reserved blocks/metadata blocks after successful +- * block allocation which had been deferred till now. We don't +- * support fallocate for non extent files. So we can update +- * reserve space here. +- */ +- if ((retval > 0) && +- (flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE)) +- ext4_da_update_reserve_space(inode, retval, 1); + } + + if (retval > 0) { diff --git a/queue-4.19/jfs-jfs_dmap-validate-db_l2nbperpage-while-mounting.patch b/queue-4.19/jfs-jfs_dmap-validate-db_l2nbperpage-while-mounting.patch new file mode 100644 index 00000000000..a53faad56d0 --- /dev/null +++ b/queue-4.19/jfs-jfs_dmap-validate-db_l2nbperpage-while-mounting.patch @@ -0,0 +1,66 @@ +From 11509910c599cbd04585ec35a6d5e1a0053d84c1 Mon Sep 17 00:00:00 2001 +From: Siddh Raman Pant +Date: Tue, 20 Jun 2023 22:17:00 +0530 +Subject: jfs: jfs_dmap: Validate db_l2nbperpage while mounting + +From: Siddh Raman Pant + +commit 11509910c599cbd04585ec35a6d5e1a0053d84c1 upstream. + +In jfs_dmap.c at line 381, BLKTODMAP is used to get a logical block +number inside dbFree(). db_l2nbperpage, which is the log2 number of +blocks per page, is passed as an argument to BLKTODMAP which uses it +for shifting. + +Syzbot reported a shift out-of-bounds crash because db_l2nbperpage is +too big. This happens because the large value is set without any +validation in dbMount() at line 181. + +Thus, make sure that db_l2nbperpage is correct while mounting. + +Max number of blocks per page = Page size / Min block size +=> log2(Max num_block per page) = log2(Page size / Min block size) + = log2(Page size) - log2(Min block size) + +=> Max db_l2nbperpage = L2PSIZE - L2MINBLOCKSIZE + +Reported-and-tested-by: syzbot+d2cd27dcf8e04b232eb2@syzkaller.appspotmail.com +Closes: https://syzkaller.appspot.com/bug?id=2a70a453331db32ed491f5cbb07e81bf2d225715 +Cc: stable@vger.kernel.org +Suggested-by: Dave Kleikamp +Signed-off-by: Siddh Raman Pant +Signed-off-by: Dave Kleikamp +Signed-off-by: Greg Kroah-Hartman +--- + fs/jfs/jfs_dmap.c | 6 ++++++ + fs/jfs/jfs_filsys.h | 2 ++ + 2 files changed, 8 insertions(+) + +--- a/fs/jfs/jfs_dmap.c ++++ b/fs/jfs/jfs_dmap.c +@@ -191,7 +191,13 @@ int dbMount(struct inode *ipbmap) + dbmp_le = (struct dbmap_disk *) mp->data; + bmp->db_mapsize = le64_to_cpu(dbmp_le->dn_mapsize); + bmp->db_nfree = le64_to_cpu(dbmp_le->dn_nfree); ++ + bmp->db_l2nbperpage = le32_to_cpu(dbmp_le->dn_l2nbperpage); ++ if (bmp->db_l2nbperpage > L2PSIZE - L2MINBLOCKSIZE) { ++ err = -EINVAL; ++ goto err_release_metapage; ++ } ++ + bmp->db_numag = le32_to_cpu(dbmp_le->dn_numag); + if (!bmp->db_numag) { + err = -EINVAL; +--- a/fs/jfs/jfs_filsys.h ++++ b/fs/jfs/jfs_filsys.h +@@ -135,7 +135,9 @@ + #define NUM_INODE_PER_IAG INOSPERIAG + + #define MINBLOCKSIZE 512 ++#define L2MINBLOCKSIZE 9 + #define MAXBLOCKSIZE 4096 ++#define L2MAXBLOCKSIZE 12 + #define MAXFILESIZE ((s64)1 << 52) + + #define JFS_LINK_MAX 0xffffffff diff --git a/queue-4.19/pci-acpiphp-reassign-resources-on-bridge-if-necessary.patch b/queue-4.19/pci-acpiphp-reassign-resources-on-bridge-if-necessary.patch new file mode 100644 index 00000000000..f33c7cbda64 --- /dev/null +++ b/queue-4.19/pci-acpiphp-reassign-resources-on-bridge-if-necessary.patch @@ -0,0 +1,78 @@ +From 40613da52b13fb21c5566f10b287e0ca8c12c4e9 Mon Sep 17 00:00:00 2001 +From: Igor Mammedov +Date: Mon, 24 Apr 2023 21:15:57 +0200 +Subject: PCI: acpiphp: Reassign resources on bridge if necessary + +From: Igor Mammedov + +commit 40613da52b13fb21c5566f10b287e0ca8c12c4e9 upstream. + +When using ACPI PCI hotplug, hotplugging a device with large BARs may fail +if bridge windows programmed by firmware are not large enough. + +Reproducer: + $ qemu-kvm -monitor stdio -M q35 -m 4G \ + -global ICH9-LPC.acpi-pci-hotplug-with-bridge-support=on \ + -device id=rp1,pcie-root-port,bus=pcie.0,chassis=4 \ + disk_image + + wait till linux guest boots, then hotplug device: + (qemu) device_add qxl,bus=rp1 + + hotplug on guest side fails with: + pci 0000:01:00.0: [1b36:0100] type 00 class 0x038000 + pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x03ffffff] + pci 0000:01:00.0: reg 0x14: [mem 0x00000000-0x03ffffff] + pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00001fff] + pci 0000:01:00.0: reg 0x1c: [io 0x0000-0x001f] + pci 0000:01:00.0: BAR 0: no space for [mem size 0x04000000] + pci 0000:01:00.0: BAR 0: failed to assign [mem size 0x04000000] + pci 0000:01:00.0: BAR 1: no space for [mem size 0x04000000] + pci 0000:01:00.0: BAR 1: failed to assign [mem size 0x04000000] + pci 0000:01:00.0: BAR 2: assigned [mem 0xfe800000-0xfe801fff] + pci 0000:01:00.0: BAR 3: assigned [io 0x1000-0x101f] + qxl 0000:01:00.0: enabling device (0000 -> 0003) + Unable to create vram_mapping + qxl: probe of 0000:01:00.0 failed with error -12 + +However when using native PCIe hotplug + '-global ICH9-LPC.acpi-pci-hotplug-with-bridge-support=off' +it works fine, since kernel attempts to reassign unused resources. + +Use the same machinery as native PCIe hotplug to (re)assign resources. + +Link: https://lore.kernel.org/r/20230424191557.2464760-1-imammedo@redhat.com +Signed-off-by: Igor Mammedov +Signed-off-by: Bjorn Helgaas +Acked-by: Michael S. Tsirkin +Acked-by: Rafael J. Wysocki +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/hotplug/acpiphp_glue.c | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +--- a/drivers/pci/hotplug/acpiphp_glue.c ++++ b/drivers/pci/hotplug/acpiphp_glue.c +@@ -496,7 +496,6 @@ static void enable_slot(struct acpiphp_s + acpiphp_native_scan_bridge(dev); + } + } else { +- LIST_HEAD(add_list); + int max, pass; + + acpiphp_rescan_slot(slot); +@@ -510,12 +509,10 @@ static void enable_slot(struct acpiphp_s + if (pass && dev->subordinate) { + check_hotplug_bridge(slot, dev); + pcibios_resource_survey_bus(dev->subordinate); +- __pci_bus_size_bridges(dev->subordinate, +- &add_list); + } + } + } +- __pci_bus_assign_resources(bus, &add_list, NULL); ++ pci_assign_unassigned_bridge_resources(bus->self); + } + + acpiphp_sanitize_bus(bus); diff --git a/queue-4.19/pci-add-function-1-dma-alias-quirk-for-marvell-88se9235.patch b/queue-4.19/pci-add-function-1-dma-alias-quirk-for-marvell-88se9235.patch new file mode 100644 index 00000000000..31ae4684215 --- /dev/null +++ b/queue-4.19/pci-add-function-1-dma-alias-quirk-for-marvell-88se9235.patch @@ -0,0 +1,36 @@ +From 88d341716b83abd355558523186ca488918627ee Mon Sep 17 00:00:00 2001 +From: Robin Murphy +Date: Wed, 7 Jun 2023 18:18:47 +0100 +Subject: PCI: Add function 1 DMA alias quirk for Marvell 88SE9235 + +From: Robin Murphy + +commit 88d341716b83abd355558523186ca488918627ee upstream. + +Marvell's own product brief implies the 92xx series are a closely related +family, and sure enough it turns out that 9235 seems to need the same quirk +as the other three, although possibly only when certain ports are used. + +Link: https://lore.kernel.org/linux-iommu/2a699a99-545c-1324-e052-7d2f41fed1ae@yahoo.co.uk/ +Link: https://lore.kernel.org/r/731507e05d70239aec96fcbfab6e65d8ce00edd2.1686157165.git.robin.murphy@arm.com +Reported-by: Jason Adriaanse +Signed-off-by: Robin Murphy +Signed-off-by: Bjorn Helgaas +Reviewed-by: Christoph Hellwig +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/quirks.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -4074,6 +4074,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_M + /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, + quirk_dma_func1_alias); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, ++ quirk_dma_func1_alias); + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, + quirk_dma_func1_alias); + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, diff --git a/queue-4.19/pci-pm-avoid-putting-elopos-e2-s2-h2-pcie-ports-in-d3cold.patch b/queue-4.19/pci-pm-avoid-putting-elopos-e2-s2-h2-pcie-ports-in-d3cold.patch new file mode 100644 index 00000000000..2a67c529051 --- /dev/null +++ b/queue-4.19/pci-pm-avoid-putting-elopos-e2-s2-h2-pcie-ports-in-d3cold.patch @@ -0,0 +1,46 @@ +From 9e30fd26f43b89cb6b4e850a86caa2e50dedb454 Mon Sep 17 00:00:00 2001 +From: Ondrej Zary +Date: Wed, 14 Jun 2023 09:42:53 +0200 +Subject: PCI/PM: Avoid putting EloPOS E2/S2/H2 PCIe Ports in D3cold + +From: Ondrej Zary + +commit 9e30fd26f43b89cb6b4e850a86caa2e50dedb454 upstream. + +The quirk for Elo i2 introduced in commit 92597f97a40b ("PCI/PM: Avoid +putting Elo i2 PCIe Ports in D3cold") is also needed by EloPOS E2/S2/H2 +which uses the same Continental Z2 board. + +Change the quirk to match the board instead of system. + +Link: https://bugzilla.kernel.org/show_bug.cgi?id=215715 +Link: https://lore.kernel.org/r/20230614074253.22318-1-linux@zary.sk +Signed-off-by: Ondrej Zary +Signed-off-by: Bjorn Helgaas +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/pci.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/drivers/pci/pci.c ++++ b/drivers/pci/pci.c +@@ -2521,13 +2521,13 @@ static const struct dmi_system_id bridge + { + /* + * Downstream device is not accessible after putting a root port +- * into D3cold and back into D0 on Elo i2. ++ * into D3cold and back into D0 on Elo Continental Z2 board + */ +- .ident = "Elo i2", ++ .ident = "Elo Continental Z2", + .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "Elo Touch Solutions"), +- DMI_MATCH(DMI_PRODUCT_NAME, "Elo i2"), +- DMI_MATCH(DMI_PRODUCT_VERSION, "RevB"), ++ DMI_MATCH(DMI_BOARD_VENDOR, "Elo Touch Solutions"), ++ DMI_MATCH(DMI_BOARD_NAME, "Geminilake"), ++ DMI_MATCH(DMI_BOARD_VERSION, "Continental Z2"), + }, + }, + #endif diff --git a/queue-4.19/pci-qcom-disable-write-access-to-read-only-registers-for-ip-v2.3.3.patch b/queue-4.19/pci-qcom-disable-write-access-to-read-only-registers-for-ip-v2.3.3.patch new file mode 100644 index 00000000000..5279a396ce6 --- /dev/null +++ b/queue-4.19/pci-qcom-disable-write-access-to-read-only-registers-for-ip-v2.3.3.patch @@ -0,0 +1,34 @@ +From a33d700e8eea76c62120cb3dbf5e01328f18319a Mon Sep 17 00:00:00 2001 +From: Manivannan Sadhasivam +Date: Mon, 19 Jun 2023 20:34:00 +0530 +Subject: PCI: qcom: Disable write access to read only registers for IP v2.3.3 + +From: Manivannan Sadhasivam + +commit a33d700e8eea76c62120cb3dbf5e01328f18319a upstream. + +In the post init sequence of v2.9.0, write access to read only registers +are not disabled after updating the registers. Fix it by disabling the +access after register update. + +Link: https://lore.kernel.org/r/20230619150408.8468-2-manivannan.sadhasivam@linaro.org +Fixes: 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller") +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Lorenzo Pieralisi +Cc: +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -758,6 +758,8 @@ static int qcom_pcie_get_resources_2_4_0 + if (IS_ERR(res->phy_ahb_reset)) + return PTR_ERR(res->phy_ahb_reset); + ++ dw_pcie_dbi_ro_wr_dis(pci); ++ + return 0; + } + diff --git a/queue-4.19/pci-rockchip-add-poll-and-timeout-to-wait-for-phy-plls-to-be-locked.patch b/queue-4.19/pci-rockchip-add-poll-and-timeout-to-wait-for-phy-plls-to-be-locked.patch new file mode 100644 index 00000000000..4dfcd00274a --- /dev/null +++ b/queue-4.19/pci-rockchip-add-poll-and-timeout-to-wait-for-phy-plls-to-be-locked.patch @@ -0,0 +1,81 @@ +From 9dd3c7c4c8c3f7f010d9cdb7c3f42506d93c9527 Mon Sep 17 00:00:00 2001 +From: Rick Wertenbroek +Date: Tue, 18 Apr 2023 09:46:51 +0200 +Subject: PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked + +From: Rick Wertenbroek + +commit 9dd3c7c4c8c3f7f010d9cdb7c3f42506d93c9527 upstream. + +The RK3399 PCIe controller should wait until the PHY PLLs are locked. +Add poll and timeout to wait for PHY PLLs to be locked. If they cannot +be locked generate error message and jump to error handler. Accessing +registers in the PHY clock domain when PLLs are not locked causes hang +The PHY PLLs status is checked through a side channel register. +This is documented in the TRM section 17.5.8.1 "PCIe Initialization +Sequence". + +Link: https://lore.kernel.org/r/20230418074700.1083505-5-rick.wertenbroek@gmail.com +Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") +Tested-by: Damien Le Moal +Signed-off-by: Rick Wertenbroek +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Damien Le Moal +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pcie-rockchip.c | 17 +++++++++++++++++ + drivers/pci/controller/pcie-rockchip.h | 2 ++ + 2 files changed, 19 insertions(+) + +--- a/drivers/pci/controller/pcie-rockchip.c ++++ b/drivers/pci/controller/pcie-rockchip.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -154,6 +155,12 @@ int rockchip_pcie_parse_dt(struct rockch + } + EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt); + ++#define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr) ++/* 100 ms max wait time for PHY PLLs to lock */ ++#define RK_PHY_PLL_LOCK_TIMEOUT_US 100000 ++/* Sleep should be less than 20ms */ ++#define RK_PHY_PLL_LOCK_SLEEP_US 1000 ++ + int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) + { + struct device *dev = rockchip->dev; +@@ -255,6 +262,16 @@ int rockchip_pcie_init_port(struct rockc + } + } + ++ err = readx_poll_timeout(rockchip_pcie_read_addr, ++ PCIE_CLIENT_SIDE_BAND_STATUS, ++ regs, !(regs & PCIE_CLIENT_PHY_ST), ++ RK_PHY_PLL_LOCK_SLEEP_US, ++ RK_PHY_PLL_LOCK_TIMEOUT_US); ++ if (err) { ++ dev_err(dev, "PHY PLLs could not lock, %d\n", err); ++ goto err_power_off_phy; ++ } ++ + /* + * Please don't reorder the deassert sequence of the following + * four reset pins. +--- a/drivers/pci/controller/pcie-rockchip.h ++++ b/drivers/pci/controller/pcie-rockchip.h +@@ -37,6 +37,8 @@ + #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0) + #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) + #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) ++#define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20) ++#define PCIE_CLIENT_PHY_ST BIT(12) + #define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c) + #define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0) + #define PCIE_CLIENT_DEBUG_LTSSM_L1 0x18 diff --git a/queue-4.19/pci-rockchip-assert-pci-configuration-enable-bit-after-probe.patch b/queue-4.19/pci-rockchip-assert-pci-configuration-enable-bit-after-probe.patch new file mode 100644 index 00000000000..40b24130c7a --- /dev/null +++ b/queue-4.19/pci-rockchip-assert-pci-configuration-enable-bit-after-probe.patch @@ -0,0 +1,40 @@ +From f397fd4ac1fa3afcabd8cee030f953ccaed2a364 Mon Sep 17 00:00:00 2001 +From: Rick Wertenbroek +Date: Tue, 18 Apr 2023 09:46:50 +0200 +Subject: PCI: rockchip: Assert PCI Configuration Enable bit after probe + +From: Rick Wertenbroek + +commit f397fd4ac1fa3afcabd8cee030f953ccaed2a364 upstream. + +Assert PCI Configuration Enable bit after probe. When this bit is left to +0 in the endpoint mode, the RK3399 PCIe endpoint core will generate +configuration request retry status (CRS) messages back to the root complex. +Assert this bit after probe to allow the RK3399 PCIe endpoint core to reply +to configuration requests from the root complex. +This is documented in section 17.5.8.1.2 of the RK3399 TRM. + +Link: https://lore.kernel.org/r/20230418074700.1083505-4-rick.wertenbroek@gmail.com +Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") +Tested-by: Damien Le Moal +Signed-off-by: Rick Wertenbroek +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Damien Le Moal +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pcie-rockchip-ep.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/pci/controller/pcie-rockchip-ep.c ++++ b/drivers/pci/controller/pcie-rockchip-ep.c +@@ -620,6 +620,9 @@ static int rockchip_pcie_ep_probe(struct + + ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR; + ++ rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE, ++ PCIE_CLIENT_CONFIG); ++ + return 0; + err_epc_mem_exit: + pci_epc_mem_exit(epc); diff --git a/queue-4.19/pci-rockchip-fix-legacy-irq-generation-for-rk3399-pcie-endpoint-core.patch b/queue-4.19/pci-rockchip-fix-legacy-irq-generation-for-rk3399-pcie-endpoint-core.patch new file mode 100644 index 00000000000..91128349f15 --- /dev/null +++ b/queue-4.19/pci-rockchip-fix-legacy-irq-generation-for-rk3399-pcie-endpoint-core.patch @@ -0,0 +1,113 @@ +From 166e89d99dd85a856343cca51eee781b793801f2 Mon Sep 17 00:00:00 2001 +From: Rick Wertenbroek +Date: Tue, 18 Apr 2023 09:46:54 +0200 +Subject: PCI: rockchip: Fix legacy IRQ generation for RK3399 PCIe endpoint core + +From: Rick Wertenbroek + +commit 166e89d99dd85a856343cca51eee781b793801f2 upstream. + +Fix legacy IRQ generation for RK3399 PCIe endpoint core according to +the technical reference manual (TRM). Assert and deassert legacy +interrupt (INTx) through the legacy interrupt control register +("PCIE_CLIENT_LEGACY_INT_CTRL") instead of manually generating a PCIe +message. The generation of the legacy interrupt was tested and validated +with the PCIe endpoint test driver. + +Link: https://lore.kernel.org/r/20230418074700.1083505-8-rick.wertenbroek@gmail.com +Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") +Tested-by: Damien Le Moal +Signed-off-by: Rick Wertenbroek +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Damien Le Moal +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pcie-rockchip-ep.c | 45 +++++++----------------------- + drivers/pci/controller/pcie-rockchip.h | 6 +++- + 2 files changed, 16 insertions(+), 35 deletions(-) + +--- a/drivers/pci/controller/pcie-rockchip-ep.c ++++ b/drivers/pci/controller/pcie-rockchip-ep.c +@@ -346,48 +346,25 @@ static int rockchip_pcie_ep_get_msi(stru + } + + static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn, +- u8 intx, bool is_asserted) ++ u8 intx, bool do_assert) + { + struct rockchip_pcie *rockchip = &ep->rockchip; +- u32 r = ep->max_regions - 1; +- u32 offset; +- u32 status; +- u8 msg_code; +- +- if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR || +- ep->irq_pci_fn != fn)) { +- rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r, +- AXI_WRAPPER_NOR_MSG, +- ep->irq_phys_addr, 0, 0); +- ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR; +- ep->irq_pci_fn = fn; +- } + + intx &= 3; +- if (is_asserted) { ++ ++ if (do_assert) { + ep->irq_pending |= BIT(intx); +- msg_code = ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA + intx; ++ rockchip_pcie_write(rockchip, ++ PCIE_CLIENT_INT_IN_ASSERT | ++ PCIE_CLIENT_INT_PEND_ST_PEND, ++ PCIE_CLIENT_LEGACY_INT_CTRL); + } else { + ep->irq_pending &= ~BIT(intx); +- msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx; ++ rockchip_pcie_write(rockchip, ++ PCIE_CLIENT_INT_IN_DEASSERT | ++ PCIE_CLIENT_INT_PEND_ST_NORMAL, ++ PCIE_CLIENT_LEGACY_INT_CTRL); + } +- +- status = rockchip_pcie_read(rockchip, +- ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + +- ROCKCHIP_PCIE_EP_CMD_STATUS); +- status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; +- +- if ((status != 0) ^ (ep->irq_pending != 0)) { +- status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; +- rockchip_pcie_write(rockchip, status, +- ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + +- ROCKCHIP_PCIE_EP_CMD_STATUS); +- } +- +- offset = +- ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) | +- ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA; +- writel(0, ep->irq_cpu_addr + offset); + } + + static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn, +--- a/drivers/pci/controller/pcie-rockchip.h ++++ b/drivers/pci/controller/pcie-rockchip.h +@@ -37,6 +37,11 @@ + #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0) + #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) + #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) ++#define PCIE_CLIENT_LEGACY_INT_CTRL (PCIE_CLIENT_BASE + 0x0c) ++#define PCIE_CLIENT_INT_IN_ASSERT HIWORD_UPDATE_BIT(0x0002) ++#define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0) ++#define PCIE_CLIENT_INT_PEND_ST_PEND HIWORD_UPDATE_BIT(0x0001) ++#define PCIE_CLIENT_INT_PEND_ST_NORMAL HIWORD_UPDATE(0x0001, 0) + #define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20) + #define PCIE_CLIENT_PHY_ST BIT(12) + #define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c) +@@ -234,7 +239,6 @@ + #define ROCKCHIP_PCIE_EP_MSI_CTRL_ME BIT(16) + #define ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP BIT(24) + #define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR 0x1 +-#define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR 0x3 + #define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) + #define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ + (PCIE_RC_RP_ATS_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) diff --git a/queue-4.19/pci-rockchip-use-u32-variable-to-access-32-bit-registers.patch b/queue-4.19/pci-rockchip-use-u32-variable-to-access-32-bit-registers.patch new file mode 100644 index 00000000000..8efd0dcdc05 --- /dev/null +++ b/queue-4.19/pci-rockchip-use-u32-variable-to-access-32-bit-registers.patch @@ -0,0 +1,76 @@ +From 8962b2cb39119cbda4fc69a1f83957824f102f81 Mon Sep 17 00:00:00 2001 +From: Rick Wertenbroek +Date: Tue, 18 Apr 2023 09:46:56 +0200 +Subject: PCI: rockchip: Use u32 variable to access 32-bit registers + +From: Rick Wertenbroek + +commit 8962b2cb39119cbda4fc69a1f83957824f102f81 upstream. + +Previously u16 variables were used to access 32-bit registers, this +resulted in not all of the data being read from the registers. Also +the left shift of more than 16-bits would result in moving data out +of the variable. Use u32 variables to access 32-bit registers + +Link: https://lore.kernel.org/r/20230418074700.1083505-10-rick.wertenbroek@gmail.com +Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") +Tested-by: Damien Le Moal +Signed-off-by: Rick Wertenbroek +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Damien Le Moal +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pcie-rockchip-ep.c | 10 +++++----- + drivers/pci/controller/pcie-rockchip.h | 1 + + 2 files changed, 6 insertions(+), 5 deletions(-) + +--- a/drivers/pci/controller/pcie-rockchip-ep.c ++++ b/drivers/pci/controller/pcie-rockchip-ep.c +@@ -313,15 +313,15 @@ static int rockchip_pcie_ep_set_msi(stru + { + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + struct rockchip_pcie *rockchip = &ep->rockchip; +- u16 flags; ++ u32 flags; + + flags = rockchip_pcie_read(rockchip, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); + flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK; + flags |= +- ((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | +- PCI_MSI_FLAGS_64BIT; ++ (multi_msg_cap << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | ++ (PCI_MSI_FLAGS_64BIT << ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET); + flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP; + rockchip_pcie_write(rockchip, flags, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + +@@ -333,7 +333,7 @@ static int rockchip_pcie_ep_get_msi(stru + { + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + struct rockchip_pcie *rockchip = &ep->rockchip; +- u16 flags; ++ u32 flags; + + flags = rockchip_pcie_read(rockchip, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + +@@ -394,7 +394,7 @@ static int rockchip_pcie_ep_send_msi_irq + u8 interrupt_num) + { + struct rockchip_pcie *rockchip = &ep->rockchip; +- u16 flags, mme, data, data_mask; ++ u32 flags, mme, data, data_mask; + u8 msi_count; + u64 pci_addr, pci_addr_mask = 0xff; + +--- a/drivers/pci/controller/pcie-rockchip.h ++++ b/drivers/pci/controller/pcie-rockchip.h +@@ -232,6 +232,7 @@ + #define ROCKCHIP_PCIE_EP_CMD_STATUS 0x4 + #define ROCKCHIP_PCIE_EP_CMD_STATUS_IS BIT(19) + #define ROCKCHIP_PCIE_EP_MSI_CTRL_REG 0x90 ++#define ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET 16 + #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET 17 + #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17) + #define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET 20 diff --git a/queue-4.19/pci-rockchip-write-pci-device-id-to-correct-register.patch b/queue-4.19/pci-rockchip-write-pci-device-id-to-correct-register.patch new file mode 100644 index 00000000000..e0393daa2ca --- /dev/null +++ b/queue-4.19/pci-rockchip-write-pci-device-id-to-correct-register.patch @@ -0,0 +1,60 @@ +From 1f1c42ece18de365c976a060f3c8eb481b038e3a Mon Sep 17 00:00:00 2001 +From: Rick Wertenbroek +Date: Tue, 18 Apr 2023 09:46:49 +0200 +Subject: PCI: rockchip: Write PCI Device ID to correct register + +From: Rick Wertenbroek + +commit 1f1c42ece18de365c976a060f3c8eb481b038e3a upstream. + +Write PCI Device ID (DID) to the correct register. The Device ID was not +updated through the correct register. Device ID was written to a read-only +register and therefore did not work. The Device ID is now set through the +correct register. This is documented in the RK3399 TRM section 17.6.6.1.1 + +Link: https://lore.kernel.org/r/20230418074700.1083505-3-rick.wertenbroek@gmail.com +Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") +Tested-by: Damien Le Moal +Signed-off-by: Rick Wertenbroek +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Damien Le Moal +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pcie-rockchip-ep.c | 6 ++++-- + drivers/pci/controller/pcie-rockchip.h | 2 ++ + 2 files changed, 6 insertions(+), 2 deletions(-) + +--- a/drivers/pci/controller/pcie-rockchip-ep.c ++++ b/drivers/pci/controller/pcie-rockchip-ep.c +@@ -124,6 +124,7 @@ static void rockchip_pcie_prog_ep_ob_atu + static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, + struct pci_epf_header *hdr) + { ++ u32 reg; + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + struct rockchip_pcie *rockchip = &ep->rockchip; + +@@ -136,8 +137,9 @@ static int rockchip_pcie_ep_write_header + PCIE_CORE_CONFIG_VENDOR); + } + +- rockchip_pcie_write(rockchip, hdr->deviceid << 16, +- ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID); ++ reg = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_DID_VID); ++ reg = (reg & 0xFFFF) | (hdr->deviceid << 16); ++ rockchip_pcie_write(rockchip, reg, PCIE_EP_CONFIG_DID_VID); + + rockchip_pcie_write(rockchip, + hdr->revid | +--- a/drivers/pci/controller/pcie-rockchip.h ++++ b/drivers/pci/controller/pcie-rockchip.h +@@ -132,6 +132,8 @@ + #define PCIE_RC_RP_ATS_BASE 0x400000 + #define PCIE_RC_CONFIG_NORMAL_BASE 0x800000 + #define PCIE_RC_CONFIG_BASE 0xa00000 ++#define PCIE_EP_CONFIG_BASE 0xa00000 ++#define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00) + #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) + #define PCIE_RC_CONFIG_SCC_SHIFT 16 + #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) diff --git a/queue-4.19/series b/queue-4.19/series index d71a0d025f6..844d4358d2c 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -155,3 +155,16 @@ tpm-tpm_vtpm_proxy-fix-a-race-condition-in-dev-vtpmx-creation.patch net-bcmgenet-ensure-mdio-unregistration-has-clocks-enabled.patch sunrpc-fix-uaf-in-svc_tcp_listen_data_ready.patch perf-intel-pt-fix-cyc-timestamps-after-standalone-cbr.patch +ext4-fix-wrong-unit-use-in-ext4_mb_clear_bb.patch +ext4-fix-to-check-return-value-of-freeze_bdev-in-ext4_shutdown.patch +ext4-only-update-i_reserved_data_blocks-on-successful-block-allocation.patch +jfs-jfs_dmap-validate-db_l2nbperpage-while-mounting.patch +pci-pm-avoid-putting-elopos-e2-s2-h2-pcie-ports-in-d3cold.patch +pci-add-function-1-dma-alias-quirk-for-marvell-88se9235.patch +pci-acpiphp-reassign-resources-on-bridge-if-necessary.patch +pci-qcom-disable-write-access-to-read-only-registers-for-ip-v2.3.3.patch +pci-rockchip-assert-pci-configuration-enable-bit-after-probe.patch +pci-rockchip-write-pci-device-id-to-correct-register.patch +pci-rockchip-add-poll-and-timeout-to-wait-for-phy-plls-to-be-locked.patch +pci-rockchip-fix-legacy-irq-generation-for-rk3399-pcie-endpoint-core.patch +pci-rockchip-use-u32-variable-to-access-32-bit-registers.patch