From: John Crispin Date: Wed, 18 Feb 2026 16:35:15 +0000 (+0100) Subject: qualcommax: replace NSS-DP DTSI with PPE DTSI X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=16d110aee39af6e359ff5068d159fed2fc01277b;p=thirdparty%2Fopenwrt.git qualcommax: replace NSS-DP DTSI with PPE DTSI Add DTSI files defining EDMA, PPE, and UNIPHY nodes for the new PPE driver bindings on IPQ5018, IPQ6018 and IPQ8074 platforms. IPQ5018 requires a patch for UNIPHY node as its cmn PLL node is upstream. These replace the existing NSS-DP ones. Signed-off-by: John Crispin [IPQ5018] Signed-off-by: George Moussalem [IPQ6018 and IPQ8074] Link: https://github.com/openwrt/openwrt/pull/22381 Signed-off-by: Robert Marko --- diff --git a/target/linux/qualcommax/config-6.12 b/target/linux/qualcommax/config-6.12 index 63d236f43bf..ed50f8fce40 100644 --- a/target/linux/qualcommax/config-6.12 +++ b/target/linux/qualcommax/config-6.12 @@ -153,6 +153,7 @@ CONFIG_FS_IOMAP=y CONFIG_FUNCTION_ALIGNMENT=4 CONFIG_FUNCTION_ALIGNMENT_4B=y CONFIG_FWNODE_MDIO=y +CONFIG_FWNODE_PCS=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y @@ -191,6 +192,7 @@ CONFIG_GPIOLIB_IRQCHIP=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_WATCHDOG=y # CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set +CONFIG_GRO_CELLS=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y @@ -281,6 +283,9 @@ CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_TAG_OOB=y CONFIG_NET_EGRESS=y CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_INGRESS=y @@ -327,10 +332,12 @@ CONFIG_PCIE_QCOM_COMMON=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_DOMAINS_GENERIC=y CONFIG_PCI_MSI=y +CONFIG_PCS_QCA_UNIPHY=y CONFIG_PER_VMA_LOCK=y CONFIG_PGTABLE_LEVELS=3 CONFIG_PHYLIB=y CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y CONFIG_PHYS_ADDR_T_64BIT=y # CONFIG_PHY_QCOM_APQ8064_SATA is not set # CONFIG_PHY_QCOM_EDP is not set @@ -535,6 +542,7 @@ CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_SGL_ALLOC=y CONFIG_SG_POOL=y +CONFIG_SKB_EXTENSIONS=y CONFIG_SMP=y # CONFIG_SM_CAMCC_4450 is not set # CONFIG_SM_CAMCC_6350 is not set diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-ess.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-ess.dtsi index a42b7bbeaa3..a2abf9f20c1 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-ess.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-ess.dtsi @@ -1,116 +1,78 @@ -#include - &soc { - ess_instance: ess-instance { - #address-cells = <1>; - #size-cells = <1>; - num_devices = <1>; - - switch: ess-switch@39c00000 { - compatible = "qcom,ess-switch-ipq50xx"; - device_id = <0>; - cmnblk_clk = "internal_96MHz"; - reg = <0x39c00000 0x200000>; - switch_access_mode = "local bus"; - clocks = <&gcc GCC_CMN_BLK_AHB_CLK>, - <&gcc GCC_CMN_BLK_SYS_CLK>, - <&gcc GCC_UNIPHY_AHB_CLK>, - <&gcc GCC_UNIPHY_SYS_CLK>, - <&gcc GCC_MDIO0_AHB_CLK>, - <&gcc GCC_MDIO1_AHB_CLK>, - <&gcc GCC_GMAC0_CFG_CLK>, - <&gcc GCC_GMAC0_SYS_CLK>, - <&gcc GCC_GMAC1_CFG_CLK>, - <&gcc GCC_GMAC1_SYS_CLK>, - <&gcc GCC_GEPHY_RX_CLK>, - <&gcc GCC_GEPHY_TX_CLK>, - <&gcc GCC_UNIPHY_RX_CLK>, - <&gcc GCC_UNIPHY_TX_CLK>, - <&gcc GCC_GMAC0_RX_CLK>, - <&gcc GCC_GMAC0_TX_CLK>, - <&gcc GCC_GMAC1_RX_CLK>, - <&gcc GCC_GMAC1_TX_CLK>, - <&gcc GCC_SNOC_GMAC0_AHB_CLK>, - <&gcc GCC_SNOC_GMAC1_AHB_CLK>, - <&gcc GCC_GMAC0_PTP_CLK>, - <&gcc GCC_GMAC1_PTP_CLK>; - clock-names = "cmn_ahb_clk", - "cmn_sys_clk", - "uniphy_ahb_clk", - "uniphy_sys_clk", - "gcc_mdio0_ahb_clk", - "gcc_mdio1_ahb_clk", - "gcc_gmac0_cfg_clk", - "gcc_gmac0_sys_clk", - "gcc_gmac1_cfg_clk", - "gcc_gmac1_sys_clk", - "uniphy0_port1_rx_clk", - "uniphy0_port1_tx_clk", - "uniphy1_port5_rx_clk", - "uniphy1_port5_tx_clk", - "nss_port1_rx_clk", - "nss_port1_tx_clk", - "nss_port2_rx_clk", - "nss_port2_tx_clk", - "gcc_snoc_gmac0_ahb_clk", - "gcc_snoc_gmac1_ahb_clk", - "gcc_gmac0_ptp_clk", - "gcc_gmac1_ptp_clk"; - resets = <&gcc GCC_GMAC0_BCR>, - <&gcc GCC_GMAC1_BCR>, - <&gcc GCC_UNIPHY_BCR>, - <&gcc GCC_UNIPHY_SOFT_RESET>; - reset-names = "gmac0_bcr_rst", - "gmac1_bcr_rst", - "uniphy_bcr_rst", - "uniphy1_soft_rst"; - - status = "disabled"; - }; - }; - - ess-uniphy@98000 { - compatible = "qcom,ess-uniphy"; - reg = <0x98000 0x800>; - uniphy_access_mode = "local bus"; - }; - - nss-dp-common { - compatible = "qcom,nss-dp-common"; - qcom,tcsr-base = <0x01937000>; - }; - - dp1: dp1 { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <1>; - - reg = <0x39C00000 0x10000>; + gmac0: ethernet@39c00000 { + compatible = "qcom,ipq5018-gmac", "snps,dwmac"; + reg = <0x39c00000 0x10000>; + reg-names = "stmmaceth"; + clocks = <&gcc GCC_GMAC0_SYS_CLK>, + <&gcc GCC_GMAC0_CFG_CLK>, + <&gcc GCC_GMAC0_PTP_CLK>, + <&gcc GCC_SNOC_GMAC0_AHB_CLK>, + <&gcc GCC_SNOC_GMAC0_AXI_CLK>, + <&gcc GCC_GMAC0_RX_CLK>, + <&gcc GCC_GMAC0_TX_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "ahb", + "axi", + "rx", + "tx"; + assigned-clocks = <&gcc GCC_GMAC0_SYS_CLK>, + <&gcc GCC_GMAC0_CFG_CLK>, + <&gcc GCC_GMAC0_PTP_CLK>, + <&gcc GCC_SNOC_GMAC0_AHB_CLK>, + <&gcc GCC_SNOC_GMAC0_AXI_CLK>; + assigned-clock-rates = <240000000>, + <240000000>, + <240000000>, + <240000000>, + <240000000>; + resets = <&gcc GCC_GMAC0_BCR>; + reset-names = "stmmaceth"; interrupts = ; - clocks = <&gcc GCC_SNOC_GMAC0_AXI_CLK>; - clock-names = "nss-snoc-gmac-axi-clk"; + interrupt-names = "macirq"; - qcom,mactype = <2>; /* GMAC_HAL_TYPE_SYN_GMAC */ - local-mac-address = [000000000000]; - phy-mode = "internal"; phy-handle = <&ge_phy>; + phy-mode = "sgmii"; status = "disabled"; }; - dp2: dp2 { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <2>; - - reg = <0x39D00000 0x10000>; + gmac1: ethernet@39d00000 { + compatible = "qcom,ipq5018-gmac", "snps,dwmac"; + reg = <0x39d00000 0x10000>; + reg-names = "stmmaceth"; + clocks = <&gcc GCC_GMAC1_SYS_CLK>, + <&gcc GCC_GMAC1_CFG_CLK>, + <&gcc GCC_GMAC1_PTP_CLK>, + <&gcc GCC_SNOC_GMAC1_AHB_CLK>, + <&gcc GCC_SNOC_GMAC1_AXI_CLK>, + <&gcc GCC_GMAC1_RX_CLK>, + <&gcc GCC_GMAC1_TX_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "ahb", + "axi", + "rx", + "tx"; + assigned-clocks = <&gcc GCC_GMAC1_SYS_CLK>, + <&gcc GCC_GMAC1_CFG_CLK>, + <&gcc GCC_GMAC1_PTP_CLK>, + <&gcc GCC_SNOC_GMAC1_AHB_CLK>, + <&gcc GCC_SNOC_GMAC1_AXI_CLK>; + assigned-clock-rates = <240000000>, + <240000000>, + <240000000>, + <240000000>, + <240000000>; + resets = <&gcc GCC_GMAC1_BCR>; + reset-names = "stmmaceth"; interrupts = ; - clocks = <&gcc GCC_SNOC_GMAC1_AXI_CLK>; - clock-names = "nss-snoc-gmac-axi-clk"; + interrupt-names = "macirq"; + + pcs-handle = <&uniphy0>; - qcom,mactype = <2>; /* GMAC_HAL_TYPE_SYN_GMAC */ - local-mac-address = [000000000000]; - phy-mode = "sgmii"; status = "disabled"; }; -}; +}; \ No newline at end of file diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-ess.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-ess.dtsi index b54f53f29ce..0de37caf7da 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-ess.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-ess.dtsi @@ -1,518 +1,166 @@ -#include +#include &soc { - bias_pll_cc_clk: bias-pll-cc-clk { + cmn_pll_ref_clk: cmn-pll-ref-clk { compatible = "fixed-clock"; - clock-frequency = <300000000>; - clock-output-names = "bias_pll_cc_clk"; + clock-frequency = <48000000>; #clock-cells = <0>; }; - bias_pll_nss_noc_clk: bias-pll-nss-noc-clk { - compatible = "fixed-clock"; - clock-frequency = <416500000>; - clock-output-names = "bias_pll_nss_noc_clk"; - #clock-cells = <0>; + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq6018-cmn-pll"; + reg = <0x0 0x0009b000 0x0 0x800>; + clocks = <&cmn_pll_ref_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", "ahb", "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll IPQ6018_CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <12000000000>; + }; + + uniphy0: ethernet-pcs@7a00000 { + compatible = "qualcomm,ipq6018-uniphy"; + reg = <0x0 0x07a00000 0x0 0x10000>; + #pcs-cells = <1>; + qcom,psgmii; + clocks = <&gcc GCC_UNIPHY0_AHB_CLK>, + <&gcc GCC_UNIPHY0_SYS_CLK>, + <&gcc GCC_UNIPHY0_PORT1_RX_CLK>, + <&gcc GCC_UNIPHY0_PORT1_TX_CLK>, + <&gcc GCC_UNIPHY0_PORT2_RX_CLK>, + <&gcc GCC_UNIPHY0_PORT2_TX_CLK>, + <&gcc GCC_UNIPHY0_PORT3_RX_CLK>, + <&gcc GCC_UNIPHY0_PORT3_TX_CLK>, + <&gcc GCC_UNIPHY0_PORT4_RX_CLK>, + <&gcc GCC_UNIPHY0_PORT4_TX_CLK>, + <&gcc GCC_UNIPHY0_PORT5_RX_CLK>, + <&gcc GCC_UNIPHY0_PORT5_TX_CLK>; + clock-names = "ahb", "sys", + "port1_rx", "port1_tx", + "port2_rx", "port2_tx", + "port3_rx", "port3_tx", + "port4_rx", "port4_tx", + "port5_rx", "port5_tx"; + clock-output-names = "uniphy0_gcc_tx_clk", + "uniphy0_gcc_rx_clk"; + resets = <&gcc GCC_UNIPHY0_SOFT_RESET>, + <&gcc GCC_UNIPHY0_XPCS_RESET>, + <&gcc GCC_UNIPHY0_PORT1_ARES>, + <&gcc GCC_UNIPHY0_PORT2_ARES>, + <&gcc GCC_UNIPHY0_PORT3_ARES>, + <&gcc GCC_UNIPHY0_PORT4_ARES>, + <&gcc GCC_UNIPHY0_PORT5_ARES>; + reset-names = "soft", "xpcs", + "port1", "port2", "port3", + "port4", "port5"; + status = "disabled"; + }; + + uniphy1: ethernet-pcs@7a10000 { + compatible = "qualcomm,ipq6018-uniphy"; + reg = <0x0 0x07a10000 0x0 0x10000>; + #pcs-cells = <1>; + clocks = <&gcc GCC_UNIPHY1_AHB_CLK>, + <&gcc GCC_UNIPHY1_SYS_CLK>, + <&gcc GCC_UNIPHY1_PORT5_RX_CLK>, + <&gcc GCC_UNIPHY1_PORT5_TX_CLK>; + clock-names = "ahb", "sys", + "port5_rx", "port5_tx"; + clock-output-names = "uniphy1_gcc_tx_clk", + "uniphy1_gcc_rx_clk"; + resets = <&gcc GCC_UNIPHY1_SOFT_RESET>, + <&gcc GCC_UNIPHY1_XPCS_RESET>; + reset-names = "soft", "xpcs"; + status = "disabled"; }; edma: edma@3ab00000 { - compatible = "qcom,edma"; - reg = <0x0 0x3ab00000 0x0 0xabe00>; - reg-names = "edma-reg-base"; - qcom,txdesc-ring-start = <23>; - qcom,txdesc-rings = <1>; - qcom,txcmpl-ring-start = <23>; - qcom,txcmpl-rings = <1>; - qcom,rxfill-ring-start = <7>; - qcom,rxfill-rings = <1>; - qcom,rxdesc-ring-start = <15>; - qcom,rxdesc-rings = <1>; + compatible = "qualcomm,ipq6018-edma"; + reg = <0x0 0x3ab00000 0x0 0xb0000>; interrupts = , , , ; resets = <&gcc GCC_EDMA_HW_RESET>; reset-names = "edma_rst"; + clocks = <&gcc GCC_NSS_EDMA_CLK>, + <&gcc GCC_NSS_EDMA_CFG_CLK>, + <&gcc GCC_NSS_PPE_CLK>, + <&gcc GCC_NSS_PPE_CFG_CLK>, + <&gcc GCC_NSSNOC_PPE_CLK>, + <&gcc GCC_NSSNOC_PPE_CFG_CLK>, + <&gcc GCC_NSS_NOC_CLK>, + <&gcc GCC_NSSNOC_SNOC_CLK>, + <&gcc GCC_SNOC_NSSNOC_CLK>; + clock-names = "nss_edma_clk", "nss_edma_cfg_clk", + "nss_ppe_clk", "nss_ppe_cfg_clk", + "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk", + "gcc_nss_noc_clk", "gcc_nssnoc_snoc_clk", + "gcc_snoc_nssnoc_clk"; status = "disabled"; }; - ess_instance: ess-instance { - #address-cells = <1>; - #size-cells = <1>; - num_devices = <1>; - - switch: ess-switch@3a000000 { - compatible = "qcom,ess-switch-ipq60xx"; - reg = <0x3a000000 0x1000000>; - switch_access_mode = "local bus"; - clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>, - <&gcc GCC_CMN_12GPLL_SYS_CLK>, - <&gcc GCC_UNIPHY0_AHB_CLK>, - <&gcc GCC_UNIPHY0_SYS_CLK>, - <&gcc GCC_UNIPHY1_AHB_CLK>, - <&gcc GCC_UNIPHY1_SYS_CLK>, - <&gcc GCC_PORT1_MAC_CLK>, - <&gcc GCC_PORT2_MAC_CLK>, - <&gcc GCC_PORT3_MAC_CLK>, - <&gcc GCC_PORT4_MAC_CLK>, - <&gcc GCC_PORT5_MAC_CLK>, - <&gcc GCC_NSS_PPE_CLK>, - <&gcc GCC_NSS_PPE_CFG_CLK>, - <&gcc GCC_NSSNOC_PPE_CLK>, - <&gcc GCC_NSSNOC_PPE_CFG_CLK>, - <&gcc GCC_NSS_EDMA_CLK>, - <&gcc GCC_NSS_EDMA_CFG_CLK>, - <&gcc GCC_NSS_PPE_IPE_CLK>, - <&gcc GCC_MDIO_AHB_CLK>, - <&gcc GCC_NSS_NOC_CLK>, - <&gcc GCC_NSSNOC_SNOC_CLK>, - <&gcc GCC_NSS_CRYPTO_CLK>, - <&gcc GCC_NSS_PTP_REF_CLK>, - <&gcc GCC_NSS_PORT1_RX_CLK>, - <&gcc GCC_NSS_PORT1_TX_CLK>, - <&gcc GCC_NSS_PORT2_RX_CLK>, - <&gcc GCC_NSS_PORT2_TX_CLK>, - <&gcc GCC_NSS_PORT3_RX_CLK>, - <&gcc GCC_NSS_PORT3_TX_CLK>, - <&gcc GCC_NSS_PORT4_RX_CLK>, - <&gcc GCC_NSS_PORT4_TX_CLK>, - <&gcc GCC_NSS_PORT5_RX_CLK>, - <&gcc GCC_NSS_PORT5_TX_CLK>, - <&gcc GCC_UNIPHY0_PORT1_RX_CLK>, - <&gcc GCC_UNIPHY0_PORT1_TX_CLK>, - <&gcc GCC_UNIPHY0_PORT2_RX_CLK>, - <&gcc GCC_UNIPHY0_PORT2_TX_CLK>, - <&gcc GCC_UNIPHY0_PORT3_RX_CLK>, - <&gcc GCC_UNIPHY0_PORT3_TX_CLK>, - <&gcc GCC_UNIPHY0_PORT4_RX_CLK>, - <&gcc GCC_UNIPHY0_PORT4_TX_CLK>, - <&gcc GCC_UNIPHY0_PORT5_RX_CLK>, - <&gcc GCC_UNIPHY0_PORT5_TX_CLK>, - <&gcc GCC_UNIPHY1_PORT5_RX_CLK>, - <&gcc GCC_UNIPHY1_PORT5_TX_CLK>, - <&gcc NSS_PORT5_RX_CLK_SRC>, - <&gcc NSS_PORT5_TX_CLK_SRC>, - <&gcc GCC_SNOC_NSSNOC_CLK>; - clock-names = "cmn_ahb_clk", "cmn_sys_clk", - "uniphy0_ahb_clk", "uniphy0_sys_clk", - "uniphy1_ahb_clk", "uniphy1_sys_clk", - "port1_mac_clk", "port2_mac_clk", - "port3_mac_clk", "port4_mac_clk", - "port5_mac_clk", - "nss_ppe_clk", "nss_ppe_cfg_clk", - "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk", - "nss_edma_clk", "nss_edma_cfg_clk", - "nss_ppe_ipe_clk", - "gcc_mdio_ahb_clk", "gcc_nss_noc_clk", - "gcc_nssnoc_snoc_clk", - "gcc_nss_crypto_clk", - "gcc_nss_ptp_ref_clk", - "nss_port1_rx_clk", "nss_port1_tx_clk", - "nss_port2_rx_clk", "nss_port2_tx_clk", - "nss_port3_rx_clk", "nss_port3_tx_clk", - "nss_port4_rx_clk", "nss_port4_tx_clk", - "nss_port5_rx_clk", "nss_port5_tx_clk", - "uniphy0_port1_rx_clk", - "uniphy0_port1_tx_clk", - "uniphy0_port2_rx_clk", - "uniphy0_port2_tx_clk", - "uniphy0_port3_rx_clk", - "uniphy0_port3_tx_clk", - "uniphy0_port4_rx_clk", - "uniphy0_port4_tx_clk", - "uniphy0_port5_rx_clk", - "uniphy0_port5_tx_clk", - "uniphy1_port5_rx_clk", - "uniphy1_port5_tx_clk", - "nss_port5_rx_clk_src", - "nss_port5_tx_clk_src", - "gcc_snoc_nssnoc_clk"; - resets = <&gcc GCC_PPE_FULL_RESET>, - <&gcc GCC_UNIPHY0_SOFT_RESET>, - <&gcc GCC_UNIPHY0_XPCS_RESET>, - <&gcc GCC_UNIPHY1_SOFT_RESET>, - <&gcc GCC_UNIPHY1_XPCS_RESET>, - <&gcc GCC_NSSPORT1_RESET>, - <&gcc GCC_NSSPORT2_RESET>, - <&gcc GCC_NSSPORT3_RESET>, - <&gcc GCC_NSSPORT4_RESET>, - <&gcc GCC_NSSPORT5_RESET>, - <&gcc GCC_UNIPHY0_PORT1_ARES>, - <&gcc GCC_UNIPHY0_PORT2_ARES>, - <&gcc GCC_UNIPHY0_PORT3_ARES>, - <&gcc GCC_UNIPHY0_PORT4_ARES>, - <&gcc GCC_UNIPHY0_PORT5_ARES>, - <&gcc GCC_UNIPHY0_PORT_4_5_RESET>, - <&gcc GCC_UNIPHY0_PORT_4_RESET>; - reset-names = "ppe_rst", "uniphy0_soft_rst", - "uniphy0_xpcs_rst", "uniphy1_soft_rst", - "uniphy1_xpcs_rst", "nss_port1_rst", - "nss_port2_rst", "nss_port3_rst", - "nss_port4_rst", "nss_port5_rst", - "uniphy0_port1_dis", - "uniphy0_port2_dis", - "uniphy0_port3_dis", - "uniphy0_port4_dis", - "uniphy0_port5_dis", - "uniphy0_port_4_5_rst", - "uniphy0_port_4_rst"; - mdio-bus = <&mdio>; - - switch_cpu_bmp = ; /* cpu port bitmap */ - switch_inner_bmp = <(ESS_PORT6 | ESS_PORT7)>; /*inner port bitmap*/ - switch_mac_mode = ; /* MAC mode for UNIPHY instance 0 */ - switch_mac_mode1 = ; /* MAC mode for UNIPHY instance 1 */ - switch_mac_mode2 = ; /* MAC mode for UNIPHY instance 2 */ - - status = "disabled"; - - bm_tick_mode = <0>; /* bm tick mode */ - tm_tick_mode = <0>; /* tm tick mode */ - - port_scheduler_resource { - port@0 { - port_id = <0>; - ucast_queue = <0 143>; - mcast_queue = <256 271>; - l0sp = <0 35>; - l0cdrr = <0 47>; - l0edrr = <0 47>; - l1cdrr = <0 7>; - l1edrr = <0 7>; - }; - port@1 { - port_id = <1>; - ucast_queue = <144 159>; - mcast_queue = <272 275>; - l0sp = <36 39>; - l0cdrr = <48 63>; - l0edrr = <48 63>; - l1cdrr = <8 11>; - l1edrr = <8 11>; - }; - port@2 { - port_id = <2>; - ucast_queue = <160 175>; - mcast_queue = <276 279>; - l0sp = <40 43>; - l0cdrr = <64 79>; - l0edrr = <64 79>; - l1cdrr = <12 15>; - l1edrr = <12 15>; - }; - port@3 { - port_id = <3>; - ucast_queue = <176 191>; - mcast_queue = <280 283>; - l0sp = <44 47>; - l0cdrr = <80 95>; - l0edrr = <80 95>; - l1cdrr = <16 19>; - l1edrr = <16 19>; - }; - port@4 { - port_id = <4>; - ucast_queue = <192 207>; - mcast_queue = <284 287>; - l0sp = <48 51>; - l0cdrr = <96 111>; - l0edrr = <96 111>; - l1cdrr = <20 23>; - l1edrr = <20 23>; - }; - port@5 { - port_id = <5>; - ucast_queue = <208 223>; - mcast_queue = <288 291>; - l0sp = <52 55>; - l0cdrr = <112 127>; - l0edrr = <112 127>; - l1cdrr = <24 27>; - l1edrr = <24 27>; - }; - port@6 { - port_id = <6>; - ucast_queue = <224 239>; - mcast_queue = <292 295>; - l0sp = <56 59>; - l0cdrr = <128 143>; - l0edrr = <128 143>; - l1cdrr = <28 31>; - l1edrr = <28 31>; - }; - port@7 { - port_id = <7>; - ucast_queue = <240 255>; - mcast_queue = <296 299>; - l0sp = <60 63>; - l0cdrr = <144 159>; - l0edrr = <144 159>; - l1cdrr = <32 35>; - l1edrr = <32 35>; - }; - }; - port_scheduler_config { - port@0 { - port_id = <0>; - l1scheduler { - group@0 { - sp = <0 1>; /*L0 SPs*/ - /*cpri cdrr epri edrr*/ - cfg = <0 0 0 0>; - }; - }; - l0scheduler { - group@0 { - /*unicast queues*/ - ucast_queue = <0 4 8>; - /*multicast queues*/ - mcast_queue = <256 260>; - /*sp cpricdrrepriedrr*/ - cfg = <0 0 0 0 0>; - }; - group@1 { - ucast_queue = <1 5 9>; - mcast_queue = <257 261>; - cfg = <0 1 1 1 1>; - }; - group@2 { - ucast_queue = <2 6 10>; - mcast_queue = <258 262>; - cfg = <0 2 2 2 2>; - }; - group@3 { - ucast_queue = <3 7 11>; - mcast_queue = <259 263>; - cfg = <0 3 3 3 3>; - }; - }; - }; - port@1 { - port_id = <1>; - l1scheduler { - group@0 { - sp = <36>; - cfg = <0 8 0 8>; - }; - group@1 { - sp = <37>; - cfg = <1 9 1 9>; - }; - }; - l0scheduler { - group@0 { - ucast_queue = <144>; - ucast_loop_pri = <16>; - mcast_queue = <272>; - mcast_loop_pri = <4>; - cfg = <36 0 48 0 48>; - }; - }; - }; - port@2 { - port_id = <2>; - l1scheduler { - group@0 { - sp = <40>; - cfg = <0 12 0 12>; - }; - group@1 { - sp = <41>; - cfg = <1 13 1 13>; - }; - }; - l0scheduler { - group@0 { - ucast_queue = <160>; - ucast_loop_pri = <16>; - mcast_queue = <276>; - mcast_loop_pri = <4>; - cfg = <40 0 64 0 64>; - }; - }; - }; - port@3 { - port_id = <3>; - l1scheduler { - group@0 { - sp = <44>; - cfg = <0 16 0 16>; - }; - group@1 { - sp = <45>; - cfg = <1 17 1 17>; - }; - }; - l0scheduler { - group@0 { - ucast_queue = <176>; - ucast_loop_pri = <16>; - mcast_queue = <280>; - mcast_loop_pri = <4>; - cfg = <44 0 80 0 80>; - }; - }; - }; - port@4 { - port_id = <4>; - l1scheduler { - group@0 { - sp = <48>; - cfg = <0 20 0 20>; - }; - group@1 { - sp = <49>; - cfg = <1 21 1 21>; - }; - }; - l0scheduler { - group@0 { - ucast_queue = <192>; - ucast_loop_pri = <16>; - mcast_queue = <284>; - mcast_loop_pri = <4>; - cfg = <48 0 96 0 96>; - }; - }; - }; - port@5 { - port_id = <5>; - l1scheduler { - group@0 { - sp = <52>; - cfg = <0 24 0 24>; - }; - group@1 { - sp = <53>; - cfg = <1 25 1 25>; - }; - }; - l0scheduler { - group@0 { - ucast_queue = <208>; - ucast_loop_pri = <16>; - mcast_queue = <288>; - mcast_loop_pri = <4>; - cfg = <52 0 112 0 112>; - }; - }; - }; - port@6 { - port_id = <6>; - l1scheduler { - group@0 { - sp = <56>; - cfg = <0 28 0 28>; - }; - group@1 { - sp = <57>; - cfg = <1 29 1 29>; - }; - }; - l0scheduler { - group@0 { - ucast_queue = <224>; - ucast_loop_pri = <16>; - mcast_queue = <292>; - mcast_loop_pri = <4>; - cfg = <56 0 128 0 128>; - }; - }; - }; - port@7 { - port_id = <7>; - l1scheduler { - group@0 { - sp = <60>; - cfg = <0 32 0 32>; - }; - group@1 { - sp = <61>; - cfg = <1 33 1 33>; - }; - }; - l0scheduler { - group@0 { - ucast_queue = <240>; - ucast_loop_pri = <16>; - mcast_queue = <296>; - cfg = <60 0 144 0 144>; - }; - }; - }; - }; - }; - - ess-uniphy@7a00000 { - compatible = "qcom,ess-uniphy"; - reg = <0x7a00000 0x30000>; - uniphy_access_mode = "local bus"; - }; - }; - - dp1: dp1 { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <1>; - reg = <0x0 0x3a001000 0x0 0x200>; - qcom,mactype = <0>; - local-mac-address = [000000000000]; - phy-mode = "psgmii"; - status = "disabled"; - }; - - dp2: dp2 { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <2>; - reg = <0x0 0x3a001200 0x0 0x200>; - qcom,mactype = <0>; - local-mac-address = [000000000000]; - phy-mode = "psgmii"; - status = "disabled"; - }; - - dp3: dp3 { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <3>; - reg = <0x0 0x3a001400 0x0 0x200>; - qcom,mactype = <0>; - local-mac-address = [000000000000]; - phy-mode = "psgmii"; - status = "disabled"; - }; - - dp4: dp4 { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <4>; - reg = <0x0 0x3a001600 0x0 0x200>; - qcom,mactype = <0>; - local-mac-address = [000000000000]; - phy-mode = "psgmii"; - status = "disabled"; - }; - - dp5: dp5 { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <5>; - reg = <0x0 0x3a001800 0x0 0x200>; - qcom,mactype = <0>; - local-mac-address = [000000000000]; - phy-mode = "psgmii"; - status = "disabled"; - }; - - dp5_syn: dp5-syn { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <5>; - reg = <0x0 0x3a003000 0x0 0x3fff>; - qcom,mactype = <1>; - local-mac-address = [000000000000]; - phy-mode = "usxgmii"; + switch: ppe@3a000000 { + compatible = "qualcomm,ipq6018-ppe"; + reg = <0x0 0x3a000000 0x0 0x900000>; + clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>, + <&gcc GCC_PORT1_MAC_CLK>, + <&gcc GCC_PORT2_MAC_CLK>, + <&gcc GCC_PORT3_MAC_CLK>, + <&gcc GCC_PORT4_MAC_CLK>, + <&gcc GCC_PORT5_MAC_CLK>, + <&gcc GCC_NSS_PPE_CLK>, + <&gcc GCC_NSS_PPE_CFG_CLK>, + <&gcc GCC_NSSNOC_PPE_CLK>, + <&gcc GCC_NSSNOC_PPE_CFG_CLK>, + <&gcc GCC_NSS_PPE_IPE_CLK>, + <&gcc GCC_MDIO_AHB_CLK>, + <&gcc GCC_NSS_NOC_CLK>, + <&gcc GCC_NSSNOC_SNOC_CLK>, + <&gcc GCC_NSS_CRYPTO_CLK>, + <&gcc GCC_NSS_PTP_REF_CLK>, + <&gcc GCC_NSS_PORT1_RX_CLK>, + <&gcc GCC_NSS_PORT1_TX_CLK>, + <&gcc GCC_NSS_PORT2_RX_CLK>, + <&gcc GCC_NSS_PORT2_TX_CLK>, + <&gcc GCC_NSS_PORT3_RX_CLK>, + <&gcc GCC_NSS_PORT3_TX_CLK>, + <&gcc GCC_NSS_PORT4_RX_CLK>, + <&gcc GCC_NSS_PORT4_TX_CLK>, + <&gcc GCC_NSS_PORT5_RX_CLK>, + <&gcc GCC_NSS_PORT5_TX_CLK>, + <&gcc GCC_SNOC_NSSNOC_CLK>; + clock-names = "cmn_ahb_clk", "cmn_sys_clk", + "port1_mac_clk", "port2_mac_clk", + "port3_mac_clk", "port4_mac_clk", + "port5_mac_clk", + "nss_ppe_clk", "nss_ppe_cfg_clk", + "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk", + "nss_ppe_ipe_clk", + "gcc_mdio_ahb_clk", "gcc_nss_noc_clk", + "gcc_nssnoc_snoc_clk", + "gcc_nss_crypto_clk", + "gcc_nss_ptp_ref_clk", + "port1_rx", "port1_tx", + "port2_rx", "port2_tx", + "port3_rx", "port3_tx", + "port4_rx", "port4_tx", + "port5_rx", "port5_tx", + "gcc_snoc_nssnoc_clk"; + assigned-clocks = <&gcc GCC_NSS_PPE_CLK>, + <&gcc GCC_NSS_CRYPTO_CLK>; + assigned-clock-rates = <300000000>, <600000000>; + resets = <&gcc GCC_PPE_FULL_RESET>, + <&gcc GCC_NSSPORT1_RESET>, + <&gcc GCC_NSSPORT2_RESET>, + <&gcc GCC_NSSPORT3_RESET>, + <&gcc GCC_NSSPORT4_RESET>, + <&gcc GCC_NSSPORT5_RESET>; + reset-names = "ppe_rst", "nss_port1_rst", + "nss_port2_rst", "nss_port3_rst", + "nss_port4_rst", "nss_port5_rst"; status = "disabled"; }; }; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi index 194540aac11..fe59cb81b3c 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi @@ -1,547 +1,186 @@ -// SPDX-License-Identifier: GPL-2.0-only +#include -#include - -&clocks { - bias_pll_cc_clk { +&soc { + cmn_pll_ref_clk: cmn-pll-ref-clk { compatible = "fixed-clock"; - clock-frequency = <300000000>; + clock-frequency = <48000000>; #clock-cells = <0>; }; - bias_pll_nss_noc_clk { - compatible = "fixed-clock"; - clock-frequency = <416500000>; - #clock-cells = <0>; + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq8074-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&cmn_pll_ref_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", "ahb", "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll IPQ8074_CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <12000000000>; }; -}; - -&soc { - ess_instance: ess-instance { - #address-cells = <1>; - #size-cells = <1>; - num_devices = <1>; - - switch: ess-switch@3a000000 { - compatible = "qcom,ess-switch-ipq807x"; - reg = <0x3a000000 0x1000000>; - switch_access_mode = "local bus"; - switch_cpu_bmp = ; /* cpu port bitmap */ - switch_inner_bmp = ; /*inner port bitmap*/ - clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>, - <&gcc GCC_CMN_12GPLL_SYS_CLK>, - <&gcc GCC_UNIPHY0_AHB_CLK>, - <&gcc GCC_UNIPHY0_SYS_CLK>, - <&gcc GCC_UNIPHY1_AHB_CLK>, - <&gcc GCC_UNIPHY1_SYS_CLK>, - <&gcc GCC_UNIPHY2_AHB_CLK>, - <&gcc GCC_UNIPHY2_SYS_CLK>, - <&gcc GCC_PORT1_MAC_CLK>, - <&gcc GCC_PORT2_MAC_CLK>, - <&gcc GCC_PORT3_MAC_CLK>, - <&gcc GCC_PORT4_MAC_CLK>, - <&gcc GCC_PORT5_MAC_CLK>, - <&gcc GCC_PORT6_MAC_CLK>, - <&gcc GCC_NSS_PPE_CLK>, - <&gcc GCC_NSS_PPE_CFG_CLK>, - <&gcc GCC_NSSNOC_PPE_CLK>, - <&gcc GCC_NSSNOC_PPE_CFG_CLK>, - <&gcc GCC_NSS_EDMA_CLK>, - <&gcc GCC_NSS_EDMA_CFG_CLK>, - <&gcc GCC_NSS_PPE_IPE_CLK>, - <&gcc GCC_NSS_PPE_BTQ_CLK>, - <&gcc GCC_MDIO_AHB_CLK>, - <&gcc GCC_NSS_NOC_CLK>, - <&gcc GCC_NSSNOC_SNOC_CLK>, - <&gcc GCC_MEM_NOC_NSS_AXI_CLK>, - <&gcc GCC_NSS_CRYPTO_CLK>, - <&gcc GCC_NSS_IMEM_CLK>, - <&gcc GCC_NSS_PTP_REF_CLK>, - <&gcc GCC_NSS_PORT1_RX_CLK>, - <&gcc GCC_NSS_PORT1_TX_CLK>, - <&gcc GCC_NSS_PORT2_RX_CLK>, - <&gcc GCC_NSS_PORT2_TX_CLK>, - <&gcc GCC_NSS_PORT3_RX_CLK>, - <&gcc GCC_NSS_PORT3_TX_CLK>, - <&gcc GCC_NSS_PORT4_RX_CLK>, - <&gcc GCC_NSS_PORT4_TX_CLK>, - <&gcc GCC_NSS_PORT5_RX_CLK>, - <&gcc GCC_NSS_PORT5_TX_CLK>, - <&gcc GCC_NSS_PORT6_RX_CLK>, - <&gcc GCC_NSS_PORT6_TX_CLK>, - <&gcc GCC_UNIPHY0_PORT1_RX_CLK>, - <&gcc GCC_UNIPHY0_PORT1_TX_CLK>, - <&gcc GCC_UNIPHY0_PORT2_RX_CLK>, - <&gcc GCC_UNIPHY0_PORT2_TX_CLK>, - <&gcc GCC_UNIPHY0_PORT3_RX_CLK>, - <&gcc GCC_UNIPHY0_PORT3_TX_CLK>, - <&gcc GCC_UNIPHY0_PORT4_RX_CLK>, - <&gcc GCC_UNIPHY0_PORT4_TX_CLK>, - <&gcc GCC_UNIPHY0_PORT5_RX_CLK>, - <&gcc GCC_UNIPHY0_PORT5_TX_CLK>, - <&gcc GCC_UNIPHY1_PORT5_RX_CLK>, - <&gcc GCC_UNIPHY1_PORT5_TX_CLK>, - <&gcc GCC_UNIPHY2_PORT6_RX_CLK>, - <&gcc GCC_UNIPHY2_PORT6_TX_CLK>, - <&gcc NSS_PORT5_RX_CLK_SRC>, - <&gcc NSS_PORT5_TX_CLK_SRC>; - clock-names = "cmn_ahb_clk", "cmn_sys_clk", - "uniphy0_ahb_clk", "uniphy0_sys_clk", - "uniphy1_ahb_clk", "uniphy1_sys_clk", - "uniphy2_ahb_clk", "uniphy2_sys_clk", - "port1_mac_clk", "port2_mac_clk", - "port3_mac_clk", "port4_mac_clk", - "port5_mac_clk", "port6_mac_clk", - "nss_ppe_clk", "nss_ppe_cfg_clk", - "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk", - "nss_edma_clk", "nss_edma_cfg_clk", - "nss_ppe_ipe_clk", "nss_ppe_btq_clk", - "gcc_mdio_ahb_clk", "gcc_nss_noc_clk", - "gcc_nssnoc_snoc_clk", - "gcc_mem_noc_nss_axi_clk", - "gcc_nss_crypto_clk", - "gcc_nss_imem_clk", - "gcc_nss_ptp_ref_clk", - "nss_port1_rx_clk", "nss_port1_tx_clk", - "nss_port2_rx_clk", "nss_port2_tx_clk", - "nss_port3_rx_clk", "nss_port3_tx_clk", - "nss_port4_rx_clk", "nss_port4_tx_clk", - "nss_port5_rx_clk", "nss_port5_tx_clk", - "nss_port6_rx_clk", "nss_port6_tx_clk", - "uniphy0_port1_rx_clk", - "uniphy0_port1_tx_clk", - "uniphy0_port2_rx_clk", - "uniphy0_port2_tx_clk", - "uniphy0_port3_rx_clk", - "uniphy0_port3_tx_clk", - "uniphy0_port4_rx_clk", - "uniphy0_port4_tx_clk", - "uniphy0_port5_rx_clk", - "uniphy0_port5_tx_clk", - "uniphy1_port5_rx_clk", - "uniphy1_port5_tx_clk", - "uniphy2_port6_rx_clk", - "uniphy2_port6_tx_clk", - "nss_port5_rx_clk_src", - "nss_port5_tx_clk_src"; - resets = <&gcc GCC_PPE_FULL_RESET>, - <&gcc GCC_UNIPHY0_SOFT_RESET>, - <&gcc GCC_UNIPHY0_XPCS_RESET>, - <&gcc GCC_UNIPHY1_SOFT_RESET>, - <&gcc GCC_UNIPHY1_XPCS_RESET>, - <&gcc GCC_UNIPHY2_SOFT_RESET>, - <&gcc GCC_UNIPHY2_XPCS_RESET>, - <&gcc GCC_NSSPORT1_RESET>, - <&gcc GCC_NSSPORT2_RESET>, - <&gcc GCC_NSSPORT3_RESET>, - <&gcc GCC_NSSPORT4_RESET>, - <&gcc GCC_NSSPORT5_RESET>, - <&gcc GCC_NSSPORT6_RESET>; - reset-names = "ppe_rst", "uniphy0_soft_rst", - "uniphy0_xpcs_rst", "uniphy1_soft_rst", - "uniphy1_xpcs_rst", "uniphy2_soft_rst", - "uniphy2_xpcs_rst", "nss_port1_rst", - "nss_port2_rst", "nss_port3_rst", - "nss_port4_rst", "nss_port5_rst", - "nss_port6_rst"; - mdio-bus = <&mdio>; - - switch_mac_mode = ; /* MAC mode for UNIPHY instance 0 */ - switch_mac_mode1 = ; /* MAC mode for UNIPHY instance 1 */ - switch_mac_mode2 = ; /* MAC mode for UNIPHY instance 2 */ - bm_tick_mode = <0>; /* bm tick mode */ - tm_tick_mode = <0>; /* tm tick mode */ - - status = "disabled"; + uniphy0: ethernet-pcs@7a00000 { + compatible = "qualcomm,ipq8074-uniphy"; + reg = <0x07a00000 0x10000>; + #pcs-cells = <1>; + clocks = <&gcc GCC_UNIPHY0_AHB_CLK>, + <&gcc GCC_UNIPHY0_SYS_CLK>, + <&gcc GCC_UNIPHY0_PORT1_RX_CLK>, + <&gcc GCC_UNIPHY0_PORT1_TX_CLK>, + <&gcc GCC_UNIPHY0_PORT2_RX_CLK>, + <&gcc GCC_UNIPHY0_PORT2_TX_CLK>, + <&gcc GCC_UNIPHY0_PORT3_RX_CLK>, + <&gcc GCC_UNIPHY0_PORT3_TX_CLK>, + <&gcc GCC_UNIPHY0_PORT4_RX_CLK>, + <&gcc GCC_UNIPHY0_PORT4_TX_CLK>, + <&gcc GCC_UNIPHY0_PORT5_RX_CLK>, + <&gcc GCC_UNIPHY0_PORT5_TX_CLK>; + clock-names = "ahb", "sys", + "port1_rx", "port1_tx", + "port2_rx", "port2_tx", + "port3_rx", "port3_tx", + "port4_rx", "port4_tx", + "port5_rx", "port5_tx"; + clock-output-names = "uniphy0_gcc_tx_clk", + "uniphy0_gcc_rx_clk"; + resets = <&gcc GCC_UNIPHY0_SOFT_RESET>, + <&gcc GCC_UNIPHY0_XPCS_RESET>; + reset-names = "soft", "xpcs"; + status = "disabled"; + }; - port_scheduler_resource { - port@0 { - port_id = <0>; - ucast_queue = <0 143>; - mcast_queue = <256 271>; - l0sp = <0 35>; - l0cdrr = <0 47>; - l0edrr = <0 47>; - l1cdrr = <0 7>; - l1edrr = <0 7>; - }; - port@1 { - port_id = <1>; - ucast_queue = <144 159>; - mcast_queue = <272 275>; - l0sp = <36 39>; - l0cdrr = <48 63>; - l0edrr = <48 63>; - l1cdrr = <8 11>; - l1edrr = <8 11>; - }; - port@2 { - port_id = <2>; - ucast_queue = <160 175>; - mcast_queue = <276 279>; - l0sp = <40 43>; - l0cdrr = <64 79>; - l0edrr = <64 79>; - l1cdrr = <12 15>; - l1edrr = <12 15>; - }; - port@3 { - port_id = <3>; - ucast_queue = <176 191>; - mcast_queue = <280 283>; - l0sp = <44 47>; - l0cdrr = <80 95>; - l0edrr = <80 95>; - l1cdrr = <16 19>; - l1edrr = <16 19>; - }; - port@4 { - port_id = <4>; - ucast_queue = <192 207>; - mcast_queue = <284 287>; - l0sp = <48 51>; - l0cdrr = <96 111>; - l0edrr = <96 111>; - l1cdrr = <20 23>; - l1edrr = <20 23>; - }; - port@5 { - port_id = <5>; - ucast_queue = <208 223>; - mcast_queue = <288 291>; - l0sp = <52 55>; - l0cdrr = <112 127>; - l0edrr = <112 127>; - l1cdrr = <24 27>; - l1edrr = <24 27>; - }; - port@6 { - port_id = <6>; - ucast_queue = <224 239>; - mcast_queue = <292 295>; - l0sp = <56 59>; - l0cdrr = <128 143>; - l0edrr = <128 143>; - l1cdrr = <28 31>; - l1edrr = <28 31>; - }; - port@7 { - port_id = <7>; - ucast_queue = <240 255>; - mcast_queue = <296 299>; - l0sp = <60 63>; - l0cdrr = <144 159>; - l0edrr = <144 159>; - l1cdrr = <32 35>; - l1edrr = <32 35>; - }; - }; - port_scheduler_config { - port@0 { - port_id = <0>; - l1scheduler { - group@0 { - sp = <0 1>; /*L0 SPs*/ - /*cpri cdrr epri edrr*/ - cfg = <0 0 0 0>; - }; - }; - l0scheduler { - group@0 { - /*unicast queues*/ - ucast_queue = <0 4 8>; - /*multicast queues*/ - mcast_queue = <256 260>; - /*sp cpri cdrr epri edrr*/ - cfg = <0 0 0 0 0>; - }; - group@1 { - ucast_queue = <1 5 9>; - mcast_queue = <257 261>; - cfg = <0 1 1 1 1>; - }; - group@2 { - ucast_queue = <2 6 10>; - mcast_queue = <258 262>; - cfg = <0 2 2 2 2>; - }; - group@3 { - ucast_queue = <3 7 11>; - mcast_queue = <259 263>; - cfg = <0 3 3 3 3>; - }; - }; - }; - port@1 { - port_id = <1>; - l1scheduler { - group@0 { - sp = <36>; - cfg = <0 8 0 8>; - }; - group@1 { - sp = <37>; - cfg = <1 9 1 9>; - }; - }; - l0scheduler { - group@0 { - ucast_queue = <144>; - ucast_loop_pri = <16>; - mcast_queue = <272>; - mcast_loop_pri = <4>; - cfg = <36 0 48 0 48>; - }; - }; - }; - port@2 { - port_id = <2>; - l1scheduler { - group@0 { - sp = <40>; - cfg = <0 12 0 12>; - }; - group@1 { - sp = <41>; - cfg = <1 13 1 13>; - }; - }; - l0scheduler { - group@0 { - ucast_queue = <160>; - ucast_loop_pri = <16>; - mcast_queue = <276>; - mcast_loop_pri = <4>; - cfg = <40 0 64 0 64>; - }; - }; - }; - port@3 { - port_id = <3>; - l1scheduler { - group@0 { - sp = <44>; - cfg = <0 16 0 16>; - }; - group@1 { - sp = <45>; - cfg = <1 17 1 17>; - }; - }; - l0scheduler { - group@0 { - ucast_queue = <176>; - ucast_loop_pri = <16>; - mcast_queue = <280>; - mcast_loop_pri = <4>; - cfg = <44 0 80 0 80>; - }; - }; - }; - port@4 { - port_id = <4>; - l1scheduler { - group@0 { - sp = <48>; - cfg = <0 20 0 20>; - }; - group@1 { - sp = <49>; - cfg = <1 21 1 21>; - }; - }; - l0scheduler { - group@0 { - ucast_queue = <192>; - ucast_loop_pri = <16>; - mcast_queue = <284>; - mcast_loop_pri = <4>; - cfg = <48 0 96 0 96>; - }; - }; - }; - port@5 { - port_id = <5>; - l1scheduler { - group@0 { - sp = <52>; - cfg = <0 24 0 24>; - }; - group@1 { - sp = <53>; - cfg = <1 25 1 25>; - }; - }; - l0scheduler { - group@0 { - ucast_queue = <208>; - ucast_loop_pri = <16>; - mcast_queue = <288>; - mcast_loop_pri = <4>; - cfg = <52 0 112 0 112>; - }; - }; - }; - port@6 { - port_id = <6>; - l1scheduler { - group@0 { - sp = <56>; - cfg = <0 28 0 28>; - }; - group@1 { - sp = <57>; - cfg = <1 29 1 29>; - }; - }; - l0scheduler { - group@0 { - ucast_queue = <224>; - ucast_loop_pri = <16>; - mcast_queue = <292>; - mcast_loop_pri = <4>; - cfg = <56 0 128 0 128>; - }; - }; - }; - port@7 { - port_id = <7>; - l1scheduler { - group@0 { - sp = <60>; - cfg = <0 32 0 32>; - }; - group@1 { - sp = <61>; - cfg = <1 33 1 33>; - }; - }; - l0scheduler { - group@0 { - ucast_queue = <240>; - ucast_loop_pri = <16>; - mcast_queue = <296>; - cfg = <60 0 144 0 144>; - }; - }; - }; - }; - }; + uniphy1: ethernet-pcs@7a10000 { + compatible = "qualcomm,ipq8074-uniphy"; + reg = <0x07a10000 0x10000>; + #pcs-cells = <1>; + clocks = <&gcc GCC_UNIPHY1_AHB_CLK>, + <&gcc GCC_UNIPHY1_SYS_CLK>, + <&gcc GCC_UNIPHY1_PORT5_RX_CLK>, + <&gcc GCC_UNIPHY1_PORT5_TX_CLK>; + clock-names = "ahb", "sys", + "port5_rx", "port5_tx"; + clock-output-names = "uniphy1_gcc_tx_clk", + "uniphy1_gcc_rx_clk"; + resets = <&gcc GCC_UNIPHY1_SOFT_RESET>, + <&gcc GCC_UNIPHY1_XPCS_RESET>; + reset-names = "soft", "xpcs"; + status = "disabled"; }; - ess-uniphy@7a00000 { - compatible = "qcom,ess-uniphy"; - reg = <0x7a00000 0x30000>; - uniphy_access_mode = "local bus"; + uniphy2: ethernet-pcs@7a20000 { + compatible = "qualcomm,ipq8074-uniphy"; + reg = <0x07a20000 0x10000>; + #pcs-cells = <1>; + clocks = <&gcc GCC_UNIPHY2_AHB_CLK>, + <&gcc GCC_UNIPHY2_SYS_CLK>, + <&gcc GCC_UNIPHY2_PORT6_RX_CLK>, + <&gcc GCC_UNIPHY2_PORT6_TX_CLK>; + clock-names = "ahb", "sys", + "port6_rx", "port6_tx"; + clock-output-names = "uniphy2_gcc_tx_clk", + "uniphy2_gcc_rx_clk"; + resets = <&gcc GCC_UNIPHY2_SOFT_RESET>, + <&gcc GCC_UNIPHY2_XPCS_RESET>; + reset-names = "soft", "xpcs"; + status = "disabled"; }; edma: edma@3ab00000 { - compatible = "qcom,edma"; - reg = <0x3ab00000 0x76900>; - reg-names = "edma-reg-base"; - qcom,txdesc-ring-start = <23>; - qcom,txdesc-rings = <1>; - qcom,txcmpl-ring-start = <7>; - qcom,txcmpl-rings = <1>; - qcom,rxfill-ring-start = <7>; - qcom,rxfill-rings = <1>; - qcom,rxdesc-ring-start = <15>; - qcom,rxdesc-rings = <1>; + compatible = "qualcomm,ipq8074-edma"; + reg = <0x3ab00000 0xb0000>; interrupts = , , , ; resets = <&gcc GCC_EDMA_HW_RESET>; reset-names = "edma_rst"; + clocks = <&gcc GCC_NSS_EDMA_CLK>, + <&gcc GCC_NSS_EDMA_CFG_CLK>, + <&gcc GCC_NSS_PPE_CLK>, + <&gcc GCC_NSS_PPE_CFG_CLK>, + <&gcc GCC_NSSNOC_PPE_CLK>, + <&gcc GCC_NSSNOC_PPE_CFG_CLK>, + <&gcc GCC_NSS_NOC_CLK>, + <&gcc GCC_NSSNOC_SNOC_CLK>, + <&gcc GCC_MEM_NOC_NSS_AXI_CLK>; + clock-names = "nss_edma_clk", "nss_edma_cfg_clk", + "nss_ppe_clk", "nss_ppe_cfg_clk", + "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk", + "gcc_nss_noc_clk", "gcc_nssnoc_snoc_clk", + "gcc_mem_noc_nss_axi_clk"; status = "disabled"; }; - dp1: dp1@3a001000 { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <1>; - reg = <0x3a001000 0x200>; - qcom,mactype = <0>; - local-mac-address = [000000000000]; - phy-mode = "psgmii"; - status = "disabled"; - }; - - dp2: dp2@3a001200 { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <2>; - reg = <0x3a001200 0x200>; - qcom,mactype = <0>; - local-mac-address = [000000000000]; - phy-mode = "psgmii"; - status = "disabled"; - }; - - dp3: dp3@3a001400 { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <3>; - reg = <0x3a001400 0x200>; - qcom,mactype = <0>; - local-mac-address = [000000000000]; - phy-mode = "psgmii"; - status = "disabled"; - }; - - dp4: dp4@3a001600 { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <4>; - reg = <0x3a001600 0x200>; - qcom,mactype = <0>; - local-mac-address = [000000000000]; - phy-mode = "psgmii"; - status = "disabled"; - }; - - dp5: dp5@3a001800 { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <5>; - reg = <0x3a001800 0x200>; - qcom,mactype = <0>; - local-mac-address = [000000000000]; - phy-mode = "psgmii"; - status = "disabled"; - }; - - dp6: dp6@3a001a00 { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <6>; - reg = <0x3a001a00 0x200>; - qcom,mactype = <0>; - local-mac-address = [000000000000]; - phy-mode = "sgmii"; - status = "disabled"; - }; - - dp5_syn: dp5-syn@3a003000 { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <5>; - reg = <0x3a003000 0x3fff>; - qcom,mactype = <1>; - local-mac-address = [000000000000]; - phy-mode = "sgmii"; - status = "disabled"; - }; - - dp6_syn: dp6-syn@3a007000 { - device_type = "network"; - compatible = "qcom,nss-dp"; - qcom,id = <6>; - reg = <0x3a007000 0x3fff>; - qcom,mactype = <1>; - local-mac-address = [000000000000]; - phy-mode = "sgmii"; + switch: ppe@3a000000 { + compatible = "qualcomm,ipq8074-ppe"; + reg = <0x3a000000 0x900000>; + clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>, + <&gcc GCC_PORT1_MAC_CLK>, + <&gcc GCC_PORT2_MAC_CLK>, + <&gcc GCC_PORT3_MAC_CLK>, + <&gcc GCC_PORT4_MAC_CLK>, + <&gcc GCC_PORT5_MAC_CLK>, + <&gcc GCC_PORT6_MAC_CLK>, + <&gcc GCC_NSS_PPE_CLK>, + <&gcc GCC_NSS_PPE_CFG_CLK>, + <&gcc GCC_NSSNOC_PPE_CLK>, + <&gcc GCC_NSSNOC_PPE_CFG_CLK>, + <&gcc GCC_NSS_PPE_IPE_CLK>, + <&gcc GCC_NSS_PPE_BTQ_CLK>, + <&gcc GCC_MDIO_AHB_CLK>, + <&gcc GCC_NSS_NOC_CLK>, + <&gcc GCC_NSSNOC_SNOC_CLK>, + <&gcc GCC_MEM_NOC_NSS_AXI_CLK>, + <&gcc GCC_NSS_CRYPTO_CLK>, + <&gcc GCC_NSS_IMEM_CLK>, + <&gcc GCC_NSS_PTP_REF_CLK>, + <&gcc GCC_NSS_PORT1_RX_CLK>, + <&gcc GCC_NSS_PORT1_TX_CLK>, + <&gcc GCC_NSS_PORT2_RX_CLK>, + <&gcc GCC_NSS_PORT2_TX_CLK>, + <&gcc GCC_NSS_PORT3_RX_CLK>, + <&gcc GCC_NSS_PORT3_TX_CLK>, + <&gcc GCC_NSS_PORT4_RX_CLK>, + <&gcc GCC_NSS_PORT4_TX_CLK>, + <&gcc GCC_NSS_PORT5_RX_CLK>, + <&gcc GCC_NSS_PORT5_TX_CLK>, + <&gcc GCC_NSS_PORT6_RX_CLK>, + <&gcc GCC_NSS_PORT6_TX_CLK>; + clock-names = "cmn_ahb_clk", "cmn_sys_clk", + "port1_mac_clk", "port2_mac_clk", + "port3_mac_clk", "port4_mac_clk", + "port5_mac_clk", "port6_mac_clk", + "nss_ppe_clk", "nss_ppe_cfg_clk", + "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk", + "nss_ppe_ipe_clk", "nss_ppe_btq_clk", + "gcc_mdio_ahb_clk", "gcc_nss_noc_clk", + "gcc_nssnoc_snoc_clk", + "gcc_mem_noc_nss_axi_clk", + "gcc_nss_crypto_clk", + "gcc_nss_imem_clk", + "gcc_nss_ptp_ref_clk", + "port1_rx", "port1_tx", + "port2_rx", "port2_tx", + "port3_rx", "port3_tx", + "port4_rx", "port4_tx", + "port5_rx", "port5_tx", + "port6_rx", "port6_tx"; + assigned-clocks = <&gcc GCC_NSS_PPE_CLK>, + <&gcc GCC_NSS_CRYPTO_CLK>, + <&gcc GCC_NSS_IMEM_CLK>; + assigned-clock-rates = <300000000>, <600000000>, <400000000>; + resets = <&gcc GCC_PPE_FULL_RESET>, + <&gcc GCC_NSSPORT1_RESET>, + <&gcc GCC_NSSPORT2_RESET>, + <&gcc GCC_NSSPORT3_RESET>, + <&gcc GCC_NSSPORT4_RESET>, + <&gcc GCC_NSSPORT5_RESET>, + <&gcc GCC_NSSPORT6_RESET>; + reset-names = "ppe_rst", "nss_port1_rst", + "nss_port2_rst", "nss_port3_rst", + "nss_port4_rst", "nss_port5_rst", + "nss_port6_rst"; status = "disabled"; }; }; diff --git a/target/linux/qualcommax/ipq50xx/config-default b/target/linux/qualcommax/ipq50xx/config-default index 5864b7a801a..8cbec438c0a 100644 --- a/target/linux/qualcommax/ipq50xx/config-default +++ b/target/linux/qualcommax/ipq50xx/config-default @@ -1,15 +1,11 @@ -CONFIG_GRO_CELLS=y CONFIG_IPQ_CMN_PLL=y CONFIG_IPQ_GCC_5018=y CONFIG_LEDS_PWM=y CONFIG_MAXLINEAR_GPHY=y CONFIG_MTD_SPI_NAND=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y CONFIG_NET_DSA_QCA8K=y CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y CONFIG_NET_DSA_TAG_QCA=y -CONFIG_PHYLINK=y CONFIG_PHY_QCOM_M31_USB=y CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP=y CONFIG_PINCTRL_IPQ5018=y diff --git a/target/linux/qualcommax/ipq807x/config-default b/target/linux/qualcommax/ipq807x/config-default index ba4c4631cb7..7c4f73d5435 100644 --- a/target/linux/qualcommax/ipq807x/config-default +++ b/target/linux/qualcommax/ipq807x/config-default @@ -1,18 +1,14 @@ CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y CONFIG_DT_IDLE_GENPD=y -CONFIG_GRO_CELLS=y CONFIG_IPQ_CMN_PLL=y CONFIG_IPQ_GCC_8074=y CONFIG_MDIO_BITBANG=y CONFIG_MDIO_GPIO=y # CONFIG_MFD_HI6421_SPMI is not set CONFIG_MFD_SPMI_PMIC=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y CONFIG_NET_DSA_QCA8K=y CONFIG_NET_DSA_TAG_QCA=y # CONFIG_NVMEM_SPMI_SDAM is not set -CONFIG_PHYLINK=y CONFIG_PINCTRL_IPQ8074=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y # CONFIG_PM8916_WATCHDOG is not set diff --git a/target/linux/qualcommax/patches-6.12/0842-arm64-dts-qcom-ipq5018-add-uniphy-node.patch b/target/linux/qualcommax/patches-6.12/0842-arm64-dts-qcom-ipq5018-add-uniphy-node.patch new file mode 100644 index 00000000000..a4432179777 --- /dev/null +++ b/target/linux/qualcommax/patches-6.12/0842-arm64-dts-qcom-ipq5018-add-uniphy-node.patch @@ -0,0 +1,51 @@ +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -258,6 +259,29 @@ + status = "disabled"; + }; + ++ uniphy0: ethernet-pcs@98000 { ++ compatible = "qualcomm,ipq5018-uniphy"; ++ reg = <0x00098000 0x800>; ++ #clock-cells = <1>; ++ clocks = <&gcc GCC_UNIPHY_AHB_CLK>, ++ <&gcc GCC_UNIPHY_SYS_CLK>, ++ <&gcc GCC_UNIPHY_RX_CLK>, ++ <&gcc GCC_UNIPHY_TX_CLK>, ++ <&cmn_pll IPQ5018_ETH_50MHZ_CLK>; ++ clock-names = "ahb", ++ "sys", ++ "port5_rx", ++ "port5_tx", ++ "ref"; ++ clock-output-names = "uniphy0_gcc_rx_clk", ++ "uniphy0_gcc_tx_clk", ++ "uniphy0_ref_clk"; ++ resets = <&gcc GCC_UNIPHY_SOFT_RESET>; ++ reset-names = "soft"; ++ #pcs-cells = <0>; ++ status = "disabled"; ++ }; ++ + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq5018-cmn-pll"; + reg = <0x0009b000 0x800>; +@@ -449,8 +473,8 @@ + <0>, + <&gephy_rx_clk>, + <&gephy_tx_clk>, +- <0>, +- <0>; ++ <&uniphy0 UNIPHY_CLK_RX>, ++ <&uniphy0 UNIPHY_CLK_TX>; + #clock-cells = <1>; + #reset-cells = <1>; + };