From: Sasha Levin Date: Wed, 10 Mar 2021 12:06:58 +0000 (-0500) Subject: Fixes for 5.11 X-Git-Tag: v4.4.261~3^2~6 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=170f9ed83bd8d3032b045fb1496a46c55739243d;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.11 Signed-off-by: Sasha Levin --- diff --git a/queue-5.11/alsa-usb-audio-add-djm750-to-pioneer-mixer-quirk.patch b/queue-5.11/alsa-usb-audio-add-djm750-to-pioneer-mixer-quirk.patch new file mode 100644 index 00000000000..5895a110db9 --- /dev/null +++ b/queue-5.11/alsa-usb-audio-add-djm750-to-pioneer-mixer-quirk.patch @@ -0,0 +1,471 @@ +From 541da7652812d06a21c600d36688f40fdd660651 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 5 Feb 2021 18:42:56 +0000 +Subject: ALSA: usb-audio: Add DJM750 to Pioneer mixer quirk + +From: Olivia Mackintosh + +[ Upstream commit a07df82c799013236aa90a140785775eda9f9523 ] + +This allows for N different devices to use the pioneer mixer quirk for +setting capture/record type and recording level. The impementation has +not changed much with the exception of an additional mask on +private_value to allow storing of a device index: + DEVICE MASK 0xff000000 + GROUP_MASK 0x00ff0000 + VALUE_MASK 0x0000ffff + +This could be improved by changing the arrays of wValues for each +channel to contain named definitions (e.g. SND_DJM_CAP_LINE). It would +improve readability and perhaps would allow using the same array for +multiple channels. The channel number can be specified on the control +next to the wIndex. + +Feedback is very much appreciated as I'm not the most proficient C +programmer but am learning as I go. + +Signed-off-by: Olivia Mackintosh +Link: https://lore.kernel.org/r/20210205184256.10201-2-livvy@base.nu +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/mixer_quirks.c | 336 +++++++++++++++++++++++++-------------- + 1 file changed, 216 insertions(+), 120 deletions(-) + +diff --git a/sound/usb/mixer_quirks.c b/sound/usb/mixer_quirks.c +index df036a359f2f..788b75cb9447 100644 +--- a/sound/usb/mixer_quirks.c ++++ b/sound/usb/mixer_quirks.c +@@ -2603,141 +2603,221 @@ static int snd_bbfpro_controls_create(struct usb_mixer_interface *mixer) + } + + /* +- * Pioneer DJ DJM-250MK2 and maybe other DJM models ++ * Pioneer DJ DJM Mixers + * +- * For playback, no duplicate mapping should be set. +- * There are three mixer stereo channels (CH1, CH2, AUX) +- * and three stereo sources (Playback 1-2, Playback 3-4, Playback 5-6). +- * Each channel should be mapped just once to one source. +- * If mapped multiple times, only one source will play on given channel +- * (sources are not mixed together). ++ * These devices generally have options for soft-switching the playback and ++ * capture sources in addition to the recording level. Although different ++ * devices have different configurations, there seems to be canonical values ++ * for specific capture/playback types: See the definitions of these below. + * +- * For recording, duplicate mapping is OK. We will get the same signal multiple times. +- * +- * Channels 7-8 are in both directions fixed to FX SEND / FX RETURN. +- * +- * See also notes in the quirks-table.h file. ++ * The wValue is masked with the stereo channel number. e.g. Setting Ch2 to ++ * capture phono would be 0x0203. Capture, playback and capture level have ++ * different wIndexes. + */ + +-struct snd_pioneer_djm_option { +- const u16 wIndex; +- const u16 wValue; ++// Capture types ++#define SND_DJM_CAP_LINE 0x00 ++#define SND_DJM_CAP_CDLINE 0x01 ++#define SND_DJM_CAP_PHONO 0x03 ++#define SND_DJM_CAP_PFADER 0x06 ++#define SND_DJM_CAP_XFADERA 0x07 ++#define SND_DJM_CAP_XFADERB 0x08 ++#define SND_DJM_CAP_MIC 0x09 ++#define SND_DJM_CAP_AUX 0x0d ++#define SND_DJM_CAP_RECOUT 0x0a ++#define SND_DJM_CAP_NONE 0x0f ++#define SND_DJM_CAP_CH1PFADER 0x11 ++#define SND_DJM_CAP_CH2PFADER 0x12 ++ ++// Playback types ++#define SND_DJM_PB_CH1 0x00 ++#define SND_DJM_PB_CH2 0x01 ++#define SND_DJM_PB_AUX 0x04 ++ ++#define SND_DJM_WINDEX_CAP 0x8002 ++#define SND_DJM_WINDEX_CAPLVL 0x8003 ++#define SND_DJM_WINDEX_PB 0x8016 ++ ++// kcontrol->private_value layout ++#define SND_DJM_VALUE_MASK 0x0000ffff ++#define SND_DJM_GROUP_MASK 0x00ff0000 ++#define SND_DJM_DEVICE_MASK 0xff000000 ++#define SND_DJM_GROUP_SHIFT 16 ++#define SND_DJM_DEVICE_SHIFT 24 ++ ++// device table index ++#define SND_DJM_250MK2_IDX 0x0 ++#define SND_DJM_750_IDX 0x1 ++ ++ ++#define SND_DJM_CTL(_name, suffix, _default_value, _windex) { \ ++ .name = _name, \ ++ .options = snd_djm_opts_##suffix, \ ++ .noptions = ARRAY_SIZE(snd_djm_opts_##suffix), \ ++ .default_value = _default_value, \ ++ .wIndex = _windex } ++ ++#define SND_DJM_DEVICE(suffix) { \ ++ .controls = snd_djm_ctls_##suffix, \ ++ .ncontrols = ARRAY_SIZE(snd_djm_ctls_##suffix) } ++ ++ ++struct snd_djm_device { + const char *name; ++ const struct snd_djm_ctl *controls; ++ size_t ncontrols; + }; + +-static const struct snd_pioneer_djm_option snd_pioneer_djm_options_capture_level[] = { +- { .name = "-5 dB", .wValue = 0x0300, .wIndex = 0x8003 }, +- { .name = "-10 dB", .wValue = 0x0200, .wIndex = 0x8003 }, +- { .name = "-15 dB", .wValue = 0x0100, .wIndex = 0x8003 }, +- { .name = "-19 dB", .wValue = 0x0000, .wIndex = 0x8003 } ++struct snd_djm_ctl { ++ const char *name; ++ const u16 *options; ++ size_t noptions; ++ u16 default_value; ++ u16 wIndex; + }; + +-static const struct snd_pioneer_djm_option snd_pioneer_djm_options_capture_ch12[] = { +- { .name = "CH1 Control Tone PHONO", .wValue = 0x0103, .wIndex = 0x8002 }, +- { .name = "CH1 Control Tone LINE", .wValue = 0x0100, .wIndex = 0x8002 }, +- { .name = "Post CH1 Fader", .wValue = 0x0106, .wIndex = 0x8002 }, +- { .name = "Cross Fader A", .wValue = 0x0107, .wIndex = 0x8002 }, +- { .name = "Cross Fader B", .wValue = 0x0108, .wIndex = 0x8002 }, +- { .name = "MIC", .wValue = 0x0109, .wIndex = 0x8002 }, +- { .name = "AUX", .wValue = 0x010d, .wIndex = 0x8002 }, +- { .name = "REC OUT", .wValue = 0x010a, .wIndex = 0x8002 } ++static const char *snd_djm_get_label_caplevel(u16 wvalue) ++{ ++ switch (wvalue) { ++ case 0x0000: return "-19dB"; ++ case 0x0100: return "-15dB"; ++ case 0x0200: return "-10dB"; ++ case 0x0300: return "-5dB"; ++ default: return NULL; ++ } + }; + +-static const struct snd_pioneer_djm_option snd_pioneer_djm_options_capture_ch34[] = { +- { .name = "CH2 Control Tone PHONO", .wValue = 0x0203, .wIndex = 0x8002 }, +- { .name = "CH2 Control Tone LINE", .wValue = 0x0200, .wIndex = 0x8002 }, +- { .name = "Post CH2 Fader", .wValue = 0x0206, .wIndex = 0x8002 }, +- { .name = "Cross Fader A", .wValue = 0x0207, .wIndex = 0x8002 }, +- { .name = "Cross Fader B", .wValue = 0x0208, .wIndex = 0x8002 }, +- { .name = "MIC", .wValue = 0x0209, .wIndex = 0x8002 }, +- { .name = "AUX", .wValue = 0x020d, .wIndex = 0x8002 }, +- { .name = "REC OUT", .wValue = 0x020a, .wIndex = 0x8002 } ++static const char *snd_djm_get_label_cap(u16 wvalue) ++{ ++ switch (wvalue & 0x00ff) { ++ case SND_DJM_CAP_LINE: return "Control Tone LINE"; ++ case SND_DJM_CAP_CDLINE: return "Control Tone CD/LINE"; ++ case SND_DJM_CAP_PHONO: return "Control Tone PHONO"; ++ case SND_DJM_CAP_PFADER: return "Post Fader"; ++ case SND_DJM_CAP_XFADERA: return "Cross Fader A"; ++ case SND_DJM_CAP_XFADERB: return "Cross Fader B"; ++ case SND_DJM_CAP_MIC: return "Mic"; ++ case SND_DJM_CAP_RECOUT: return "Rec Out"; ++ case SND_DJM_CAP_AUX: return "Aux"; ++ case SND_DJM_CAP_NONE: return "None"; ++ case SND_DJM_CAP_CH1PFADER: return "Post Fader Ch1"; ++ case SND_DJM_CAP_CH2PFADER: return "Post Fader Ch2"; ++ default: return NULL; ++ } + }; + +-static const struct snd_pioneer_djm_option snd_pioneer_djm_options_capture_ch56[] = { +- { .name = "REC OUT", .wValue = 0x030a, .wIndex = 0x8002 }, +- { .name = "Post CH1 Fader", .wValue = 0x0311, .wIndex = 0x8002 }, +- { .name = "Post CH2 Fader", .wValue = 0x0312, .wIndex = 0x8002 }, +- { .name = "Cross Fader A", .wValue = 0x0307, .wIndex = 0x8002 }, +- { .name = "Cross Fader B", .wValue = 0x0308, .wIndex = 0x8002 }, +- { .name = "MIC", .wValue = 0x0309, .wIndex = 0x8002 }, +- { .name = "AUX", .wValue = 0x030d, .wIndex = 0x8002 } ++static const char *snd_djm_get_label_pb(u16 wvalue) ++{ ++ switch (wvalue & 0x00ff) { ++ case SND_DJM_PB_CH1: return "Ch1"; ++ case SND_DJM_PB_CH2: return "Ch2"; ++ case SND_DJM_PB_AUX: return "Aux"; ++ default: return NULL; ++ } + }; + +-static const struct snd_pioneer_djm_option snd_pioneer_djm_options_playback_12[] = { +- { .name = "CH1", .wValue = 0x0100, .wIndex = 0x8016 }, +- { .name = "CH2", .wValue = 0x0101, .wIndex = 0x8016 }, +- { .name = "AUX", .wValue = 0x0104, .wIndex = 0x8016 } ++static const char *snd_djm_get_label(u16 wvalue, u16 windex) ++{ ++ switch (windex) { ++ case SND_DJM_WINDEX_CAPLVL: return snd_djm_get_label_caplevel(wvalue); ++ case SND_DJM_WINDEX_CAP: return snd_djm_get_label_cap(wvalue); ++ case SND_DJM_WINDEX_PB: return snd_djm_get_label_pb(wvalue); ++ default: return NULL; ++ } + }; + +-static const struct snd_pioneer_djm_option snd_pioneer_djm_options_playback_34[] = { +- { .name = "CH1", .wValue = 0x0200, .wIndex = 0x8016 }, +- { .name = "CH2", .wValue = 0x0201, .wIndex = 0x8016 }, +- { .name = "AUX", .wValue = 0x0204, .wIndex = 0x8016 } +-}; + +-static const struct snd_pioneer_djm_option snd_pioneer_djm_options_playback_56[] = { +- { .name = "CH1", .wValue = 0x0300, .wIndex = 0x8016 }, +- { .name = "CH2", .wValue = 0x0301, .wIndex = 0x8016 }, +- { .name = "AUX", .wValue = 0x0304, .wIndex = 0x8016 } ++// DJM-250MK2 ++static const u16 snd_djm_opts_cap_level[] = { ++ 0x0000, 0x0100, 0x0200, 0x0300 }; ++ ++static const u16 snd_djm_opts_250mk2_cap1[] = { ++ 0x0103, 0x0100, 0x0106, 0x0107, 0x0108, 0x0109, 0x010d, 0x010a }; ++ ++static const u16 snd_djm_opts_250mk2_cap2[] = { ++ 0x0203, 0x0200, 0x0206, 0x0207, 0x0208, 0x0209, 0x020d, 0x020a }; ++ ++static const u16 snd_djm_opts_250mk2_cap3[] = { ++ 0x030a, 0x0311, 0x0312, 0x0307, 0x0308, 0x0309, 0x030d }; ++ ++static const u16 snd_djm_opts_250mk2_pb1[] = { 0x0100, 0x0101, 0x0104 }; ++static const u16 snd_djm_opts_250mk2_pb2[] = { 0x0200, 0x0201, 0x0204 }; ++static const u16 snd_djm_opts_250mk2_pb3[] = { 0x0300, 0x0301, 0x0304 }; ++ ++static const struct snd_djm_ctl snd_djm_ctls_250mk2[] = { ++ SND_DJM_CTL("Capture Level", cap_level, 0, SND_DJM_WINDEX_CAPLVL), ++ SND_DJM_CTL("Ch1 Input", 250mk2_cap1, 2, SND_DJM_WINDEX_CAP), ++ SND_DJM_CTL("Ch2 Input", 250mk2_cap2, 2, SND_DJM_WINDEX_CAP), ++ SND_DJM_CTL("Ch3 Input", 250mk2_cap3, 0, SND_DJM_WINDEX_CAP), ++ SND_DJM_CTL("Ch1 Output", 250mk2_pb1, 0, SND_DJM_WINDEX_PB), ++ SND_DJM_CTL("Ch2 Output", 250mk2_pb2, 1, SND_DJM_WINDEX_PB), ++ SND_DJM_CTL("Ch3 Output", 250mk2_pb3, 2, SND_DJM_WINDEX_PB) + }; + +-struct snd_pioneer_djm_option_group { +- const char *name; +- const struct snd_pioneer_djm_option *options; +- const size_t count; +- const u16 default_value; ++ ++// DJM-750 ++static const u16 snd_djm_opts_750_cap1[] = { ++ 0x0101, 0x0103, 0x0106, 0x0107, 0x0108, 0x0109, 0x010a, 0x010f }; ++static const u16 snd_djm_opts_750_cap2[] = { ++ 0x0200, 0x0201, 0x0206, 0x0207, 0x0208, 0x0209, 0x020a, 0x020f }; ++static const u16 snd_djm_opts_750_cap3[] = { ++ 0x0300, 0x0301, 0x0306, 0x0307, 0x0308, 0x0309, 0x030a, 0x030f }; ++static const u16 snd_djm_opts_750_cap4[] = { ++ 0x0401, 0x0403, 0x0406, 0x0407, 0x0408, 0x0409, 0x040a, 0x040f }; ++ ++static const struct snd_djm_ctl snd_djm_ctls_750[] = { ++ SND_DJM_CTL("Capture Level", cap_level, 0, SND_DJM_WINDEX_CAPLVL), ++ SND_DJM_CTL("Ch1 Input", 750_cap1, 2, SND_DJM_WINDEX_CAP), ++ SND_DJM_CTL("Ch2 Input", 750_cap2, 2, SND_DJM_WINDEX_CAP), ++ SND_DJM_CTL("Ch3 Input", 750_cap3, 0, SND_DJM_WINDEX_CAP), ++ SND_DJM_CTL("Ch4 Input", 750_cap4, 0, SND_DJM_WINDEX_CAP) + }; + +-#define snd_pioneer_djm_option_group_item(_name, suffix, _default_value) { \ +- .name = _name, \ +- .options = snd_pioneer_djm_options_##suffix, \ +- .count = ARRAY_SIZE(snd_pioneer_djm_options_##suffix), \ +- .default_value = _default_value } +- +-static const struct snd_pioneer_djm_option_group snd_pioneer_djm_option_groups[] = { +- snd_pioneer_djm_option_group_item("Master Capture Level Capture Switch", capture_level, 0), +- snd_pioneer_djm_option_group_item("Capture 1-2 Capture Switch", capture_ch12, 2), +- snd_pioneer_djm_option_group_item("Capture 3-4 Capture Switch", capture_ch34, 2), +- snd_pioneer_djm_option_group_item("Capture 5-6 Capture Switch", capture_ch56, 0), +- snd_pioneer_djm_option_group_item("Playback 1-2 Playback Switch", playback_12, 0), +- snd_pioneer_djm_option_group_item("Playback 3-4 Playback Switch", playback_34, 1), +- snd_pioneer_djm_option_group_item("Playback 5-6 Playback Switch", playback_56, 2) ++ ++static const struct snd_djm_device snd_djm_devices[] = { ++ SND_DJM_DEVICE(250mk2), ++ SND_DJM_DEVICE(750) + }; + +-// layout of the kcontrol->private_value: +-#define SND_PIONEER_DJM_VALUE_MASK 0x0000ffff +-#define SND_PIONEER_DJM_GROUP_MASK 0xffff0000 +-#define SND_PIONEER_DJM_GROUP_SHIFT 16 + +-static int snd_pioneer_djm_controls_info(struct snd_kcontrol *kctl, struct snd_ctl_elem_info *info) ++static int snd_djm_controls_info(struct snd_kcontrol *kctl, ++ struct snd_ctl_elem_info *info) + { +- u16 group_index = kctl->private_value >> SND_PIONEER_DJM_GROUP_SHIFT; +- size_t count; ++ unsigned long private_value = kctl->private_value; ++ u8 device_idx = (private_value & SND_DJM_DEVICE_MASK) >> SND_DJM_DEVICE_SHIFT; ++ u8 ctl_idx = (private_value & SND_DJM_GROUP_MASK) >> SND_DJM_GROUP_SHIFT; ++ const struct snd_djm_device *device = &snd_djm_devices[device_idx]; + const char *name; +- const struct snd_pioneer_djm_option_group *group; ++ const struct snd_djm_ctl *ctl; ++ size_t noptions; ++ ++ if (ctl_idx >= device->ncontrols) ++ return -EINVAL; ++ ++ ctl = &device->controls[ctl_idx]; ++ noptions = ctl->noptions; ++ if (info->value.enumerated.item >= noptions) ++ info->value.enumerated.item = noptions - 1; + +- if (group_index >= ARRAY_SIZE(snd_pioneer_djm_option_groups)) ++ name = snd_djm_get_label(ctl->options[info->value.enumerated.item], ++ ctl->wIndex); ++ if (!name) + return -EINVAL; + +- group = &snd_pioneer_djm_option_groups[group_index]; +- count = group->count; +- if (info->value.enumerated.item >= count) +- info->value.enumerated.item = count - 1; +- name = group->options[info->value.enumerated.item].name; + strlcpy(info->value.enumerated.name, name, sizeof(info->value.enumerated.name)); + info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; + info->count = 1; +- info->value.enumerated.items = count; ++ info->value.enumerated.items = noptions; + return 0; + } + +-static int snd_pioneer_djm_controls_update(struct usb_mixer_interface *mixer, u16 group, u16 value) ++static int snd_djm_controls_update(struct usb_mixer_interface *mixer, ++ u8 device_idx, u8 group, u16 value) + { + int err; ++ const struct snd_djm_device *device = &snd_djm_devices[device_idx]; + +- if (group >= ARRAY_SIZE(snd_pioneer_djm_option_groups) +- || value >= snd_pioneer_djm_option_groups[group].count) ++ if ((group >= device->ncontrols) || value >= device->controls[group].noptions) + return -EINVAL; + + err = snd_usb_lock_shutdown(mixer->chip); +@@ -2748,63 +2828,76 @@ static int snd_pioneer_djm_controls_update(struct usb_mixer_interface *mixer, u1 + mixer->chip->dev, usb_sndctrlpipe(mixer->chip->dev, 0), + USB_REQ_SET_FEATURE, + USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, +- snd_pioneer_djm_option_groups[group].options[value].wValue, +- snd_pioneer_djm_option_groups[group].options[value].wIndex, ++ device->controls[group].options[value], ++ device->controls[group].wIndex, + NULL, 0); + + snd_usb_unlock_shutdown(mixer->chip); + return err; + } + +-static int snd_pioneer_djm_controls_get(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *elem) ++static int snd_djm_controls_get(struct snd_kcontrol *kctl, ++ struct snd_ctl_elem_value *elem) + { +- elem->value.enumerated.item[0] = kctl->private_value & SND_PIONEER_DJM_VALUE_MASK; ++ elem->value.enumerated.item[0] = kctl->private_value & SND_DJM_VALUE_MASK; + return 0; + } + +-static int snd_pioneer_djm_controls_put(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *elem) ++static int snd_djm_controls_put(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *elem) + { + struct usb_mixer_elem_list *list = snd_kcontrol_chip(kctl); + struct usb_mixer_interface *mixer = list->mixer; + unsigned long private_value = kctl->private_value; +- u16 group = (private_value & SND_PIONEER_DJM_GROUP_MASK) >> SND_PIONEER_DJM_GROUP_SHIFT; ++ ++ u8 device = (private_value & SND_DJM_DEVICE_MASK) >> SND_DJM_DEVICE_SHIFT; ++ u8 group = (private_value & SND_DJM_GROUP_MASK) >> SND_DJM_GROUP_SHIFT; + u16 value = elem->value.enumerated.item[0]; + +- kctl->private_value = (group << SND_PIONEER_DJM_GROUP_SHIFT) | value; ++ kctl->private_value = ((device << SND_DJM_DEVICE_SHIFT) | ++ (group << SND_DJM_GROUP_SHIFT) | ++ value); + +- return snd_pioneer_djm_controls_update(mixer, group, value); ++ return snd_djm_controls_update(mixer, device, group, value); + } + +-static int snd_pioneer_djm_controls_resume(struct usb_mixer_elem_list *list) ++static int snd_djm_controls_resume(struct usb_mixer_elem_list *list) + { + unsigned long private_value = list->kctl->private_value; +- u16 group = (private_value & SND_PIONEER_DJM_GROUP_MASK) >> SND_PIONEER_DJM_GROUP_SHIFT; +- u16 value = (private_value & SND_PIONEER_DJM_VALUE_MASK); ++ u8 device = (private_value & SND_DJM_DEVICE_MASK) >> SND_DJM_DEVICE_SHIFT; ++ u8 group = (private_value & SND_DJM_GROUP_MASK) >> SND_DJM_GROUP_SHIFT; ++ u16 value = (private_value & SND_DJM_VALUE_MASK); + +- return snd_pioneer_djm_controls_update(list->mixer, group, value); ++ return snd_djm_controls_update(list->mixer, device, group, value); + } + +-static int snd_pioneer_djm_controls_create(struct usb_mixer_interface *mixer) ++static int snd_djm_controls_create(struct usb_mixer_interface *mixer, ++ const u8 device_idx) + { + int err, i; +- const struct snd_pioneer_djm_option_group *group; ++ u16 value; ++ ++ const struct snd_djm_device *device = &snd_djm_devices[device_idx]; ++ + struct snd_kcontrol_new knew = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .index = 0, +- .info = snd_pioneer_djm_controls_info, +- .get = snd_pioneer_djm_controls_get, +- .put = snd_pioneer_djm_controls_put ++ .info = snd_djm_controls_info, ++ .get = snd_djm_controls_get, ++ .put = snd_djm_controls_put + }; + +- for (i = 0; i < ARRAY_SIZE(snd_pioneer_djm_option_groups); i++) { +- group = &snd_pioneer_djm_option_groups[i]; +- knew.name = group->name; +- knew.private_value = (i << SND_PIONEER_DJM_GROUP_SHIFT) | group->default_value; +- err = snd_pioneer_djm_controls_update(mixer, i, group->default_value); ++ for (i = 0; i < device->ncontrols; i++) { ++ value = device->controls[i].default_value; ++ knew.name = device->controls[i].name; ++ knew.private_value = ( ++ (device_idx << SND_DJM_DEVICE_SHIFT) | ++ (i << SND_DJM_GROUP_SHIFT) | ++ value); ++ err = snd_djm_controls_update(mixer, device_idx, i, value); + if (err) + return err; +- err = add_single_ctl_with_resume(mixer, 0, snd_pioneer_djm_controls_resume, ++ err = add_single_ctl_with_resume(mixer, 0, snd_djm_controls_resume, + &knew, NULL); + if (err) + return err; +@@ -2917,7 +3010,10 @@ int snd_usb_mixer_apply_create_quirk(struct usb_mixer_interface *mixer) + err = snd_bbfpro_controls_create(mixer); + break; + case USB_ID(0x2b73, 0x0017): /* Pioneer DJ DJM-250MK2 */ +- err = snd_pioneer_djm_controls_create(mixer); ++ err = snd_djm_controls_create(mixer, SND_DJM_250MK2_IDX); ++ break; ++ case USB_ID(0x08e4, 0x017f): /* Pioneer DJ DJM-750 */ ++ err = snd_djm_controls_create(mixer, SND_DJM_750_IDX); + break; + } + +-- +2.30.1 + diff --git a/queue-5.11/alsa-usb-audio-add-mixer-quirks-for-pioneer-djm-900n.patch b/queue-5.11/alsa-usb-audio-add-mixer-quirks-for-pioneer-djm-900n.patch new file mode 100644 index 00000000000..72407e6ae1b --- /dev/null +++ b/queue-5.11/alsa-usb-audio-add-mixer-quirks-for-pioneer-djm-900n.patch @@ -0,0 +1,118 @@ +From 8c7a3c76f4c543fdfd1216d620d93a3eda66b6e9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 5 Feb 2021 22:51:16 +0100 +Subject: ALSA: usb-audio: add mixer quirks for Pioneer DJM-900NXS2 + +From: Fabian Lesniak + +[ Upstream commit fee03efc69345344c8851596d74d93199b175bfe ] + +This commit adds mixer quirks for the Pioneer DJM-900NXS2 mixer. This +device has 6 capture channels, 5 of them allow setting the signal +source. This adds controls for these, similar to the DJM-250Mk2. +However, playpack channels are not controllable via software like on the +250Mk2, as they can only be set manually on the mixing console. +Read-only controls showing the currently selected playback channels are +omitted. + +Signed-off-by: Fabian Lesniak +Link: https://lore.kernel.org/r/20210205215116.258724-2-fabian@lesniak-it.de +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/mixer_quirks.c | 35 ++++++++++++++++++++++++++++++++++- + 1 file changed, 34 insertions(+), 1 deletion(-) + +diff --git a/sound/usb/mixer_quirks.c b/sound/usb/mixer_quirks.c +index 788b75cb9447..448de77f43fd 100644 +--- a/sound/usb/mixer_quirks.c ++++ b/sound/usb/mixer_quirks.c +@@ -2618,6 +2618,7 @@ static int snd_bbfpro_controls_create(struct usb_mixer_interface *mixer) + // Capture types + #define SND_DJM_CAP_LINE 0x00 + #define SND_DJM_CAP_CDLINE 0x01 ++#define SND_DJM_CAP_DIGITAL 0x02 + #define SND_DJM_CAP_PHONO 0x03 + #define SND_DJM_CAP_PFADER 0x06 + #define SND_DJM_CAP_XFADERA 0x07 +@@ -2628,6 +2629,8 @@ static int snd_bbfpro_controls_create(struct usb_mixer_interface *mixer) + #define SND_DJM_CAP_NONE 0x0f + #define SND_DJM_CAP_CH1PFADER 0x11 + #define SND_DJM_CAP_CH2PFADER 0x12 ++#define SND_DJM_CAP_CH3PFADER 0x13 ++#define SND_DJM_CAP_CH4PFADER 0x14 + + // Playback types + #define SND_DJM_PB_CH1 0x00 +@@ -2648,6 +2651,7 @@ static int snd_bbfpro_controls_create(struct usb_mixer_interface *mixer) + // device table index + #define SND_DJM_250MK2_IDX 0x0 + #define SND_DJM_750_IDX 0x1 ++#define SND_DJM_900NXS2_IDX 0x2 + + + #define SND_DJM_CTL(_name, suffix, _default_value, _windex) { \ +@@ -2692,6 +2696,7 @@ static const char *snd_djm_get_label_cap(u16 wvalue) + switch (wvalue & 0x00ff) { + case SND_DJM_CAP_LINE: return "Control Tone LINE"; + case SND_DJM_CAP_CDLINE: return "Control Tone CD/LINE"; ++ case SND_DJM_CAP_DIGITAL: return "Control Tone DIGITAL"; + case SND_DJM_CAP_PHONO: return "Control Tone PHONO"; + case SND_DJM_CAP_PFADER: return "Post Fader"; + case SND_DJM_CAP_XFADERA: return "Cross Fader A"; +@@ -2702,6 +2707,8 @@ static const char *snd_djm_get_label_cap(u16 wvalue) + case SND_DJM_CAP_NONE: return "None"; + case SND_DJM_CAP_CH1PFADER: return "Post Fader Ch1"; + case SND_DJM_CAP_CH2PFADER: return "Post Fader Ch2"; ++ case SND_DJM_CAP_CH3PFADER: return "Post Fader Ch3"; ++ case SND_DJM_CAP_CH4PFADER: return "Post Fader Ch4"; + default: return NULL; + } + }; +@@ -2774,9 +2781,32 @@ static const struct snd_djm_ctl snd_djm_ctls_750[] = { + }; + + ++// DJM-900NXS2 ++static const u16 snd_djm_opts_900nxs2_cap1[] = { ++ 0x0100, 0x0102, 0x0103, 0x0106, 0x0107, 0x0108, 0x0109, 0x010a }; ++static const u16 snd_djm_opts_900nxs2_cap2[] = { ++ 0x0200, 0x0202, 0x0203, 0x0206, 0x0207, 0x0208, 0x0209, 0x020a }; ++static const u16 snd_djm_opts_900nxs2_cap3[] = { ++ 0x0300, 0x0302, 0x0303, 0x0306, 0x0307, 0x0308, 0x0309, 0x030a }; ++static const u16 snd_djm_opts_900nxs2_cap4[] = { ++ 0x0400, 0x0402, 0x0403, 0x0406, 0x0407, 0x0408, 0x0409, 0x040a }; ++static const u16 snd_djm_opts_900nxs2_cap5[] = { ++ 0x0507, 0x0508, 0x0509, 0x050a, 0x0511, 0x0512, 0x0513, 0x0514 }; ++ ++static const struct snd_djm_ctl snd_djm_ctls_900nxs2[] = { ++ SND_DJM_CTL("Capture Level", cap_level, 0, SND_DJM_WINDEX_CAPLVL), ++ SND_DJM_CTL("Ch1 Input", 900nxs2_cap1, 2, SND_DJM_WINDEX_CAP), ++ SND_DJM_CTL("Ch2 Input", 900nxs2_cap2, 2, SND_DJM_WINDEX_CAP), ++ SND_DJM_CTL("Ch3 Input", 900nxs2_cap3, 2, SND_DJM_WINDEX_CAP), ++ SND_DJM_CTL("Ch4 Input", 900nxs2_cap4, 2, SND_DJM_WINDEX_CAP), ++ SND_DJM_CTL("Ch5 Input", 900nxs2_cap5, 3, SND_DJM_WINDEX_CAP) ++}; ++ ++ + static const struct snd_djm_device snd_djm_devices[] = { + SND_DJM_DEVICE(250mk2), +- SND_DJM_DEVICE(750) ++ SND_DJM_DEVICE(750), ++ SND_DJM_DEVICE(900nxs2) + }; + + +@@ -3015,6 +3045,9 @@ int snd_usb_mixer_apply_create_quirk(struct usb_mixer_interface *mixer) + case USB_ID(0x08e4, 0x017f): /* Pioneer DJ DJM-750 */ + err = snd_djm_controls_create(mixer, SND_DJM_750_IDX); + break; ++ case USB_ID(0x2b73, 0x000a): /* Pioneer DJ DJM-900NXS2 */ ++ err = snd_djm_controls_create(mixer, SND_DJM_900NXS2_IDX); ++ break; + } + + return err; +-- +2.30.1 + diff --git a/queue-5.11/asoc-intel-sof_sdw-add-quirk-for-hp-spectre-x360-con.patch b/queue-5.11/asoc-intel-sof_sdw-add-quirk-for-hp-spectre-x360-con.patch new file mode 100644 index 00000000000..fcfeae9485b --- /dev/null +++ b/queue-5.11/asoc-intel-sof_sdw-add-quirk-for-hp-spectre-x360-con.patch @@ -0,0 +1,53 @@ +From 9374d2c93d14a800a6a75947ccbb7a4d890eb300 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 8 Feb 2021 17:33:28 -0600 +Subject: ASoC: Intel: sof_sdw: add quirk for HP Spectre x360 convertible + +From: Pierre-Louis Bossart + +[ Upstream commit d92e279dee56b4b65c1af21f972413f172a9734a ] + +This set of devices has SoundWire support along with DMICs. +The DMI information was provided by users for 3 separate skus. + +BugLink: https://github.com/thesofproject/linux/issues/2700 +Signed-off-by: Pierre-Louis Bossart +Reviewed-by: Guennadi Liakhovetski +Reviewed-by: Kai Vehmanen +Link: https://lore.kernel.org/r/20210208233336.59449-4-pierre-louis.bossart@linux.intel.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/intel/boards/sof_sdw.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/sound/soc/intel/boards/sof_sdw.c b/sound/soc/intel/boards/sof_sdw.c +index 9e2e8f508ed4..1d7677376e74 100644 +--- a/sound/soc/intel/boards/sof_sdw.c ++++ b/sound/soc/intel/boards/sof_sdw.c +@@ -159,6 +159,22 @@ static const struct dmi_system_id sof_sdw_quirk_table[] = { + SOF_SDW_PCH_DMIC | + SOF_SDW_FOUR_SPK), + }, ++ { ++ /* ++ * this entry covers multiple HP SKUs. The family name ++ * does not seem robust enough, so we use a partial ++ * match that ignores the product name suffix ++ * (e.g. 15-eb1xxx, 14t-ea000 or 13-aw2xxx) ++ */ ++ .callback = sof_sdw_quirk_cb, ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "HP"), ++ DMI_MATCH(DMI_PRODUCT_NAME, "HP Spectre x360 Convertible"), ++ }, ++ .driver_data = (void *)(SOF_SDW_TGL_HDMI | ++ SOF_SDW_PCH_DMIC | ++ SOF_RT711_JD_SRC_JD2), ++ }, + /* TigerLake-SDCA devices */ + { + .callback = sof_sdw_quirk_cb, +-- +2.30.1 + diff --git a/queue-5.11/asoc-intel-sof_sdw-reorganize-quirks-by-generation.patch b/queue-5.11/asoc-intel-sof_sdw-reorganize-quirks-by-generation.patch new file mode 100644 index 00000000000..2325e218df3 --- /dev/null +++ b/queue-5.11/asoc-intel-sof_sdw-reorganize-quirks-by-generation.patch @@ -0,0 +1,147 @@ +From bb2917240aeb75ee834d260e3559ed60ad9aebc4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 8 Feb 2021 17:33:26 -0600 +Subject: ASoC: Intel: sof_sdw: reorganize quirks by generation + +From: Pierre-Louis Bossart + +[ Upstream commit 3d09cf8d0d791a41a75123e135f604d59f4aa870 ] + +The quirk table is a mess, let's reorganize it by generation before +making sure that the quirks are consistent for each generation. + +Signed-off-by: Pierre-Louis Bossart +Reviewed-by: Guennadi Liakhovetski +Reviewed-by: Kai Vehmanen +Link: https://lore.kernel.org/r/20210208233336.59449-2-pierre-louis.bossart@linux.intel.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/intel/boards/sof_sdw.c | 73 +++++++++++++++++--------------- + 1 file changed, 38 insertions(+), 35 deletions(-) + +diff --git a/sound/soc/intel/boards/sof_sdw.c b/sound/soc/intel/boards/sof_sdw.c +index daca06dde99b..9e2e8f508ed4 100644 +--- a/sound/soc/intel/boards/sof_sdw.c ++++ b/sound/soc/intel/boards/sof_sdw.c +@@ -48,37 +48,14 @@ static int sof_sdw_quirk_cb(const struct dmi_system_id *id) + } + + static const struct dmi_system_id sof_sdw_quirk_table[] = { ++ /* CometLake devices */ + { + .callback = sof_sdw_quirk_cb, + .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"), +- DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0A32") +- }, +- .driver_data = (void *)(SOF_SDW_TGL_HDMI | +- SOF_RT711_JD_SRC_JD2 | +- SOF_RT715_DAI_ID_FIX | +- SOF_SDW_FOUR_SPK), +- }, +- { +- .callback = sof_sdw_quirk_cb, +- .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"), +- DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0A3E") +- }, +- .driver_data = (void *)(SOF_SDW_TGL_HDMI | +- SOF_RT711_JD_SRC_JD2 | +- SOF_RT715_DAI_ID_FIX), +- }, +- { +- .callback = sof_sdw_quirk_cb, +- .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"), +- DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0A5E") ++ DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"), ++ DMI_MATCH(DMI_PRODUCT_NAME, "CometLake Client"), + }, +- .driver_data = (void *)(SOF_SDW_TGL_HDMI | +- SOF_RT711_JD_SRC_JD2 | +- SOF_RT715_DAI_ID_FIX | +- SOF_SDW_FOUR_SPK), ++ .driver_data = (void *)SOF_SDW_PCH_DMIC, + }, + { + .callback = sof_sdw_quirk_cb, +@@ -109,7 +86,7 @@ static const struct dmi_system_id sof_sdw_quirk_table[] = { + SOF_RT715_DAI_ID_FIX | + SOF_SDW_FOUR_SPK), + }, +- { ++ { + .callback = sof_sdw_quirk_cb, + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"), +@@ -119,6 +96,16 @@ static const struct dmi_system_id sof_sdw_quirk_table[] = { + SOF_RT715_DAI_ID_FIX | + SOF_SDW_FOUR_SPK), + }, ++ /* IceLake devices */ ++ { ++ .callback = sof_sdw_quirk_cb, ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"), ++ DMI_MATCH(DMI_PRODUCT_NAME, "Ice Lake Client"), ++ }, ++ .driver_data = (void *)SOF_SDW_PCH_DMIC, ++ }, ++ /* TigerLake devices */ + { + .callback = sof_sdw_quirk_cb, + .matches = { +@@ -134,18 +121,23 @@ static const struct dmi_system_id sof_sdw_quirk_table[] = { + { + .callback = sof_sdw_quirk_cb, + .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"), +- DMI_MATCH(DMI_PRODUCT_NAME, "Ice Lake Client"), ++ DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0A3E") + }, +- .driver_data = (void *)SOF_SDW_PCH_DMIC, ++ .driver_data = (void *)(SOF_SDW_TGL_HDMI | ++ SOF_RT711_JD_SRC_JD2 | ++ SOF_RT715_DAI_ID_FIX), + }, + { + .callback = sof_sdw_quirk_cb, + .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"), +- DMI_MATCH(DMI_PRODUCT_NAME, "CometLake Client"), ++ DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0A5E") + }, +- .driver_data = (void *)SOF_SDW_PCH_DMIC, ++ .driver_data = (void *)(SOF_SDW_TGL_HDMI | ++ SOF_RT711_JD_SRC_JD2 | ++ SOF_RT715_DAI_ID_FIX | ++ SOF_SDW_FOUR_SPK), + }, + { + .callback = sof_sdw_quirk_cb, +@@ -167,7 +159,18 @@ static const struct dmi_system_id sof_sdw_quirk_table[] = { + SOF_SDW_PCH_DMIC | + SOF_SDW_FOUR_SPK), + }, +- ++ /* TigerLake-SDCA devices */ ++ { ++ .callback = sof_sdw_quirk_cb, ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0A32") ++ }, ++ .driver_data = (void *)(SOF_SDW_TGL_HDMI | ++ SOF_RT711_JD_SRC_JD2 | ++ SOF_RT715_DAI_ID_FIX | ++ SOF_SDW_FOUR_SPK), ++ }, + {} + }; + +-- +2.30.1 + diff --git a/queue-5.11/drm-msm-a5xx-remove-overwriting-a5xx_pc_dbg_eco_cntl.patch b/queue-5.11/drm-msm-a5xx-remove-overwriting-a5xx_pc_dbg_eco_cntl.patch new file mode 100644 index 00000000000..b9c76c35147 --- /dev/null +++ b/queue-5.11/drm-msm-a5xx-remove-overwriting-a5xx_pc_dbg_eco_cntl.patch @@ -0,0 +1,46 @@ +From f1387396a992d898d0ec139e9299ff44c75a7680 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 13 Jan 2021 19:33:33 +0100 +Subject: drm/msm/a5xx: Remove overwriting A5XX_PC_DBG_ECO_CNTL register + +From: AngeloGioacchino Del Regno + +[ Upstream commit 8f03c30cb814213e36032084a01f49a9e604a3e3 ] + +The PC_DBG_ECO_CNTL register on the Adreno A5xx family gets +programmed to some different values on a per-model basis. +At least, this is what we intend to do here; + +Unfortunately, though, this register is being overwritten with a +static magic number, right after applying the GPU-specific +configuration (including the GPU-specific quirks) and that is +effectively nullifying the efforts. + +Let's remove the redundant and wrong write to the PC_DBG_ECO_CNTL +register in order to retain the wanted configuration for the +target GPU. + +Signed-off-by: AngeloGioacchino Del Regno +Reviewed-by: Jordan Crouse +Signed-off-by: Rob Clark +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +index a5af223eaf50..81506d2539b0 100644 +--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c ++++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +@@ -626,8 +626,6 @@ static int a5xx_hw_init(struct msm_gpu *gpu) + if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI) + gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); + +- gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0xc0200100); +- + /* Enable USE_RETENTION_FLOPS */ + gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000); + +-- +2.30.1 + diff --git a/queue-5.11/hid-i2c-hid-add-i2c_hid_quirk_no_irq_after_reset-for.patch b/queue-5.11/hid-i2c-hid-add-i2c_hid_quirk_no_irq_after_reset-for.patch new file mode 100644 index 00000000000..d4e9aee459d --- /dev/null +++ b/queue-5.11/hid-i2c-hid-add-i2c_hid_quirk_no_irq_after_reset-for.patch @@ -0,0 +1,62 @@ +From cc08c519d1b81dc0c6ed48e9cf75d4f8c0eba138 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 30 Jan 2021 21:33:23 +0100 +Subject: HID: i2c-hid: Add I2C_HID_QUIRK_NO_IRQ_AFTER_RESET for ITE8568 EC on + Voyo Winpad A15 + +From: Hans de Goede + +[ Upstream commit fc6a31b00739356809dd566e16f2c4325a63285d ] + +The ITE8568 EC on the Voyo Winpad A15 presents itself as an I2C-HID +attached keyboard and mouse (which seems to never send any events). + +This needs the I2C_HID_QUIRK_NO_IRQ_AFTER_RESET quirk, otherwise we get +the following errors: + +[ 3688.770850] i2c_hid i2c-ITE8568:00: failed to reset device. +[ 3694.915865] i2c_hid i2c-ITE8568:00: failed to reset device. +[ 3701.059717] i2c_hid i2c-ITE8568:00: failed to reset device. +[ 3707.205944] i2c_hid i2c-ITE8568:00: failed to reset device. +[ 3708.227940] i2c_hid i2c-ITE8568:00: can't add hid device: -61 +[ 3708.236518] i2c_hid: probe of i2c-ITE8568:00 failed with error -61 + +Which leads to a significant boot delay. + +Signed-off-by: Hans de Goede +Signed-off-by: Jiri Kosina +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-ids.h | 2 ++ + drivers/hid/i2c-hid/i2c-hid-core.c | 2 ++ + 2 files changed, 4 insertions(+) + +diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h +index 5ba0aa1d2335..b60279aaed43 100644 +--- a/drivers/hid/hid-ids.h ++++ b/drivers/hid/hid-ids.h +@@ -641,6 +641,8 @@ + #define USB_DEVICE_ID_INNEX_GENESIS_ATARI 0x4745 + + #define USB_VENDOR_ID_ITE 0x048d ++#define I2C_VENDOR_ID_ITE 0x103c ++#define I2C_DEVICE_ID_ITE_VOYO_WINPAD_A15 0x184f + #define USB_DEVICE_ID_ITE_LENOVO_YOGA 0x8386 + #define USB_DEVICE_ID_ITE_LENOVO_YOGA2 0x8350 + #define I2C_DEVICE_ID_ITE_LENOVO_LEGION_Y720 0x837a +diff --git a/drivers/hid/i2c-hid/i2c-hid-core.c b/drivers/hid/i2c-hid/i2c-hid-core.c +index bfe716d7ea44..c586acf2fc0b 100644 +--- a/drivers/hid/i2c-hid/i2c-hid-core.c ++++ b/drivers/hid/i2c-hid/i2c-hid-core.c +@@ -171,6 +171,8 @@ static const struct i2c_hid_quirks { + I2C_HID_QUIRK_SET_PWR_WAKEUP_DEV }, + { I2C_VENDOR_ID_HANTICK, I2C_PRODUCT_ID_HANTICK_5288, + I2C_HID_QUIRK_NO_IRQ_AFTER_RESET }, ++ { I2C_VENDOR_ID_ITE, I2C_DEVICE_ID_ITE_VOYO_WINPAD_A15, ++ I2C_HID_QUIRK_NO_IRQ_AFTER_RESET }, + { I2C_VENDOR_ID_RAYDIUM, I2C_PRODUCT_ID_RAYDIUM_3118, + I2C_HID_QUIRK_NO_IRQ_AFTER_RESET }, + { USB_VENDOR_ID_ELAN, HID_ANY_ID, +-- +2.30.1 + diff --git a/queue-5.11/hid-ite-enable-quirk_touchpad_on_off_report-on-acer-.patch b/queue-5.11/hid-ite-enable-quirk_touchpad_on_off_report-on-acer-.patch new file mode 100644 index 00000000000..3e23cfa765c --- /dev/null +++ b/queue-5.11/hid-ite-enable-quirk_touchpad_on_off_report-on-acer-.patch @@ -0,0 +1,85 @@ +From 81676cbeb79f943dcd2a778ccd54f26228e3d163 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 6 Feb 2021 21:53:27 +0100 +Subject: HID: ite: Enable QUIRK_TOUCHPAD_ON_OFF_REPORT on Acer Aspire Switch + 10E + +From: Hans de Goede + +[ Upstream commit b7c20f3815985570ac71c39b1a3e68c201109578 ] + +The Acer Aspire Switch 10E (SW3-016)'s keyboard-dock uses the same USB-ids +as the Acer One S1003 keyboard-dock. Yet they are not entirely the same: + +1. The S1003 keyboard-dock has the same report descriptors as the +S1002 keyboard-dock (which has different USB-ids) + +2. The Acer Aspire Switch 10E's keyboard-dock has different +report descriptors from the S1002/S1003 keyboard docks and it +sends 0x00880078 / 0x00880079 usage events when the touchpad is +toggled on/off (which is handled internally). + +This means that all Acer kbd-docks handled by the hid-ite.c drivers +report their touchpad being toggled on/off through these custom +usage-codes with the exception of the S1003 dock, which likely is +a bug of that dock. + +Add a QUIRK_TOUCHPAD_ON_OFF_REPORT quirk for the Aspire Switch 10E / S1003 +usb-id so that the touchpad toggling will get reported to userspace on +the Aspire Switch 10E. + +Since the Aspire Switch 10E's kbd-dock has different report-descriptors, +this also requires adding support for fixing those to ite_report_fixup(). + +Setting the quirk will also cause ite_report_fixup() to hit the +S1002/S1003 descriptors path on the S1003. Since the S1003 kbd-dock +never generates any input-reports for the fixed up part of the +descriptors this does not matter; and if there are versions out there +which do actually send input-reports for the touchpad-toggle then the +fixup should actually help to make things work. + +This was tested on both an Acer Aspire Switch 10E and on an Acer One S1003. + +Signed-off-by: Hans de Goede +Signed-off-by: Jiri Kosina +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-ite.c | 12 +++++++++--- + 1 file changed, 9 insertions(+), 3 deletions(-) + +diff --git a/drivers/hid/hid-ite.c b/drivers/hid/hid-ite.c +index 22bfbebceaf4..14fc068affad 100644 +--- a/drivers/hid/hid-ite.c ++++ b/drivers/hid/hid-ite.c +@@ -23,11 +23,16 @@ static __u8 *ite_report_fixup(struct hid_device *hdev, __u8 *rdesc, unsigned int + hid_info(hdev, "Fixing up Acer Sw5-012 ITE keyboard report descriptor\n"); + rdesc[163] = HID_MAIN_ITEM_RELATIVE; + } +- /* For Acer One S1002 keyboard-dock */ ++ /* For Acer One S1002/S1003 keyboard-dock */ + if (*rsize == 188 && rdesc[185] == 0x81 && rdesc[186] == 0x02) { +- hid_info(hdev, "Fixing up Acer S1002 ITE keyboard report descriptor\n"); ++ hid_info(hdev, "Fixing up Acer S1002/S1003 ITE keyboard report descriptor\n"); + rdesc[186] = HID_MAIN_ITEM_RELATIVE; + } ++ /* For Acer Aspire Switch 10E (SW3-016) keyboard-dock */ ++ if (*rsize == 210 && rdesc[184] == 0x81 && rdesc[185] == 0x02) { ++ hid_info(hdev, "Fixing up Acer Aspire Switch 10E (SW3-016) ITE keyboard report descriptor\n"); ++ rdesc[185] = HID_MAIN_ITEM_RELATIVE; ++ } + } + + return rdesc; +@@ -114,7 +119,8 @@ static const struct hid_device_id ite_devices[] = { + /* ITE8910 USB kbd ctlr, with Synaptics touchpad connected to it. */ + { HID_DEVICE(BUS_USB, HID_GROUP_GENERIC, + USB_VENDOR_ID_SYNAPTICS, +- USB_DEVICE_ID_SYNAPTICS_ACER_ONE_S1003) }, ++ USB_DEVICE_ID_SYNAPTICS_ACER_ONE_S1003), ++ .driver_data = QUIRK_TOUCHPAD_ON_OFF_REPORT }, + { } + }; + MODULE_DEVICE_TABLE(hid, ite_devices); +-- +2.30.1 + diff --git a/queue-5.11/kvm-svm-clear-the-cr4-register-on-reset.patch b/queue-5.11/kvm-svm-clear-the-cr4-register-on-reset.patch new file mode 100644 index 00000000000..639308fa191 --- /dev/null +++ b/queue-5.11/kvm-svm-clear-the-cr4-register-on-reset.patch @@ -0,0 +1,47 @@ +From 4303d0f9bdb60491e8588bfd2559b708313a8c6b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 2 Mar 2021 12:51:31 -0600 +Subject: KVM: SVM: Clear the CR4 register on reset + +From: Babu Moger + +[ Upstream commit 9e46f6c6c959d9bb45445c2e8f04a75324a0dfd0 ] + +This problem was reported on a SVM guest while executing kexec. +Kexec fails to load the new kernel when the PCID feature is enabled. + +When kexec starts loading the new kernel, it starts the process by +resetting the vCPU's and then bringing each vCPU online one by one. +The vCPU reset is supposed to reset all the register states before the +vCPUs are brought online. However, the CR4 register is not reset during +this process. If this register is already setup during the last boot, +all the flags can remain intact. The X86_CR4_PCIDE bit can only be +enabled in long mode. So, it must be enabled much later in SMP +initialization. Having the X86_CR4_PCIDE bit set during SMP boot can +cause a boot failures. + +Fix the issue by resetting the CR4 register in init_vmcb(). + +Signed-off-by: Babu Moger +Message-Id: <161471109108.30811.6392805173629704166.stgit@bmoger-ubuntu> +Signed-off-by: Paolo Bonzini +Signed-off-by: Sasha Levin +--- + arch/x86/kvm/svm/svm.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c +index 825ef6d281c9..6a0670548125 100644 +--- a/arch/x86/kvm/svm/svm.c ++++ b/arch/x86/kvm/svm/svm.c +@@ -1205,6 +1205,7 @@ static void init_vmcb(struct vcpu_svm *svm) + init_sys_seg(&save->ldtr, SEG_TYPE_LDT); + init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); + ++ svm_set_cr4(&svm->vcpu, 0); + svm_set_efer(&svm->vcpu, 0); + save->dr6 = 0xffff0ff0; + kvm_set_rflags(&svm->vcpu, 2); +-- +2.30.1 + diff --git a/queue-5.11/misc-eeprom_93xx46-add-quirk-to-support-microchip-93.patch b/queue-5.11/misc-eeprom_93xx46-add-quirk-to-support-microchip-93.patch new file mode 100644 index 00000000000..90f654b08cf --- /dev/null +++ b/queue-5.11/misc-eeprom_93xx46-add-quirk-to-support-microchip-93.patch @@ -0,0 +1,91 @@ +From 14965dbd6d0bca454cb0aeb27c2c68823a0edb53 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 5 Jan 2021 16:28:12 +0530 +Subject: misc: eeprom_93xx46: Add quirk to support Microchip 93LC46B eeprom + +From: Aswath Govindraju + +[ Upstream commit f6f1f8e6e3eea25f539105d48166e91f0ab46dd1 ] + +A dummy zero bit is sent preceding the data during a read transfer by the +Microchip 93LC46B eeprom (section 2.7 of[1]). This results in right shift +of data during a read. In order to ignore this bit a quirk can be added to +send an extra zero bit after the read address. + +Add a quirk to ignore the zero bit sent before data by adding a zero bit +after the read address. + +[1] - https://www.mouser.com/datasheet/2/268/20001749K-277859.pdf + +Signed-off-by: Aswath Govindraju +Link: https://lore.kernel.org/r/20210105105817.17644-3-a-govindraju@ti.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/misc/eeprom/eeprom_93xx46.c | 15 +++++++++++++++ + include/linux/eeprom_93xx46.h | 2 ++ + 2 files changed, 17 insertions(+) + +diff --git a/drivers/misc/eeprom/eeprom_93xx46.c b/drivers/misc/eeprom/eeprom_93xx46.c +index d92c4d2c521a..6e5f544c9c73 100644 +--- a/drivers/misc/eeprom/eeprom_93xx46.c ++++ b/drivers/misc/eeprom/eeprom_93xx46.c +@@ -35,6 +35,10 @@ static const struct eeprom_93xx46_devtype_data atmel_at93c46d_data = { + EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH, + }; + ++static const struct eeprom_93xx46_devtype_data microchip_93lc46b_data = { ++ .quirks = EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE, ++}; ++ + struct eeprom_93xx46_dev { + struct spi_device *spi; + struct eeprom_93xx46_platform_data *pdata; +@@ -55,6 +59,11 @@ static inline bool has_quirk_instruction_length(struct eeprom_93xx46_dev *edev) + return edev->pdata->quirks & EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH; + } + ++static inline bool has_quirk_extra_read_cycle(struct eeprom_93xx46_dev *edev) ++{ ++ return edev->pdata->quirks & EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE; ++} ++ + static int eeprom_93xx46_read(void *priv, unsigned int off, + void *val, size_t count) + { +@@ -96,6 +105,11 @@ static int eeprom_93xx46_read(void *priv, unsigned int off, + dev_dbg(&edev->spi->dev, "read cmd 0x%x, %d Hz\n", + cmd_addr, edev->spi->max_speed_hz); + ++ if (has_quirk_extra_read_cycle(edev)) { ++ cmd_addr <<= 1; ++ bits += 1; ++ } ++ + spi_message_init(&m); + + t[0].tx_buf = (char *)&cmd_addr; +@@ -363,6 +377,7 @@ static void select_deassert(void *context) + static const struct of_device_id eeprom_93xx46_of_table[] = { + { .compatible = "eeprom-93xx46", }, + { .compatible = "atmel,at93c46d", .data = &atmel_at93c46d_data, }, ++ { .compatible = "microchip,93lc46b", .data = µchip_93lc46b_data, }, + {} + }; + MODULE_DEVICE_TABLE(of, eeprom_93xx46_of_table); +diff --git a/include/linux/eeprom_93xx46.h b/include/linux/eeprom_93xx46.h +index eec7928ff8fe..99580c22f91a 100644 +--- a/include/linux/eeprom_93xx46.h ++++ b/include/linux/eeprom_93xx46.h +@@ -16,6 +16,8 @@ struct eeprom_93xx46_platform_data { + #define EEPROM_93XX46_QUIRK_SINGLE_WORD_READ (1 << 0) + /* Instructions such as EWEN are (addrlen + 2) in length. */ + #define EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH (1 << 1) ++/* Add extra cycle after address during a read */ ++#define EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE BIT(2) + + /* + * optional hooks to control additional logic +-- +2.30.1 + diff --git a/queue-5.11/mmc-sdhci-of-dwcmshc-set-sdhci_quirk2_preset_value_b.patch b/queue-5.11/mmc-sdhci-of-dwcmshc-set-sdhci_quirk2_preset_value_b.patch new file mode 100644 index 00000000000..479c4cb4952 --- /dev/null +++ b/queue-5.11/mmc-sdhci-of-dwcmshc-set-sdhci_quirk2_preset_value_b.patch @@ -0,0 +1,35 @@ +From 5eb5766b5326893d2160054e5fe99b2f54521671 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 10 Dec 2020 16:55:10 +0800 +Subject: mmc: sdhci-of-dwcmshc: set SDHCI_QUIRK2_PRESET_VALUE_BROKEN + +From: Jisheng Zhang + +[ Upstream commit 5f7dfda4f2cec580c135fd81d96a05006651c128 ] + +The SDHCI_PRESET_FOR_* registers are not set(all read as zeros), so +set the quirk. + +Signed-off-by: Jisheng Zhang +Link: https://lore.kernel.org/r/20201210165510.76b917e5@xhacker.debian +Signed-off-by: Ulf Hansson +Signed-off-by: Sasha Levin +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c +index d90020ed3622..59d8d96ce206 100644 +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -112,6 +112,7 @@ static const struct sdhci_ops sdhci_dwcmshc_ops = { + static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { + .ops = &sdhci_dwcmshc_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, ++ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }; + + static int dwcmshc_probe(struct platform_device *pdev) +-- +2.30.1 + diff --git a/queue-5.11/nvme-pci-add-quirks-for-lexar-256gb-ssd.patch b/queue-5.11/nvme-pci-add-quirks-for-lexar-256gb-ssd.patch new file mode 100644 index 00000000000..8959cdef94d --- /dev/null +++ b/queue-5.11/nvme-pci-add-quirks-for-lexar-256gb-ssd.patch @@ -0,0 +1,38 @@ +From d9d432c2fc460090958694e6cd6d7e933dd9c7d4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 23 Feb 2021 22:10:46 +0000 +Subject: nvme-pci: add quirks for Lexar 256GB SSD + +From: Pascal Terjan + +[ Upstream commit 6e6a6828c517fb6819479bf5187df5f39084eb9e ] + +Add the NVME_QUIRK_NO_NS_DESC_LIST and NVME_QUIRK_IGNORE_DEV_SUBNQN +quirks for this buggy device. + +Reported and tested in https://bugs.mageia.org/show_bug.cgi?id=28417 + +Signed-off-by: Pascal Terjan +Signed-off-by: Christoph Hellwig +Signed-off-by: Sasha Levin +--- + drivers/nvme/host/pci.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c +index 14c5b52400ef..806a5d071ef6 100644 +--- a/drivers/nvme/host/pci.c ++++ b/drivers/nvme/host/pci.c +@@ -3245,6 +3245,9 @@ static const struct pci_device_id nvme_id_table[] = { + NVME_QUIRK_IGNORE_DEV_SUBNQN, }, + { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ + .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, ++ { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ ++ .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | ++ NVME_QUIRK_IGNORE_DEV_SUBNQN, }, + { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ + .driver_data = NVME_QUIRK_LIGHTNVM, }, + { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ +-- +2.30.1 + diff --git a/queue-5.11/nvme-pci-mark-kingston-skc2000-as-not-supporting-the.patch b/queue-5.11/nvme-pci-mark-kingston-skc2000-as-not-supporting-the.patch new file mode 100644 index 00000000000..9f7ed33802b --- /dev/null +++ b/queue-5.11/nvme-pci-mark-kingston-skc2000-as-not-supporting-the.patch @@ -0,0 +1,48 @@ +From 59682e5462075e2fdd9bfb183263b369d31aacfd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 21 Feb 2021 06:12:16 +0100 +Subject: nvme-pci: mark Kingston SKC2000 as not supporting the deepest power + state +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Zoltán Böszörményi + +[ Upstream commit dc22c1c058b5c4fe967a20589e36f029ee42a706 ] + +My 2TB SKC2000 showed the exact same symptoms that were provided +in 538e4a8c57 ("nvme-pci: avoid the deepest sleep state on +Kingston A2000 SSDs"), i.e. a complete NVME lockup that needed +cold boot to get it back. + +According to some sources, the A2000 is simply a rebadged +SKC2000 with a slightly optimized firmware. + +Adding the SKC2000 PCI ID to the quirk list with the same workaround +as the A2000 made my laptop survive a 5 hours long Yocto bootstrap +buildfest which reliably triggered the SSD lockup previously. + +Signed-off-by: Zoltán Böszörményi +Signed-off-by: Christoph Hellwig +Signed-off-by: Sasha Levin +--- + drivers/nvme/host/pci.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c +index 7a38d764b486..14c5b52400ef 100644 +--- a/drivers/nvme/host/pci.c ++++ b/drivers/nvme/host/pci.c +@@ -3262,6 +3262,8 @@ static const struct pci_device_id nvme_id_table[] = { + .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, + { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ + .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, ++ { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ ++ .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, + { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ + .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, + { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), +-- +2.30.1 + diff --git a/queue-5.11/nvme-pci-mark-seagate-nytro-xm1440-as-quirk_no_ns_de.patch b/queue-5.11/nvme-pci-mark-seagate-nytro-xm1440-as-quirk_no_ns_de.patch new file mode 100644 index 00000000000..c52a7d7458c --- /dev/null +++ b/queue-5.11/nvme-pci-mark-seagate-nytro-xm1440-as-quirk_no_ns_de.patch @@ -0,0 +1,51 @@ +From a94e980f7bff5e11cb41317ed7f0597a19dd4b3d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 16 Feb 2021 13:25:43 +0100 +Subject: nvme-pci: mark Seagate Nytro XM1440 as QUIRK_NO_NS_DESC_LIST. + +From: Julian Einwag + +[ Upstream commit 5e112d3fb89703a4981ded60561b5647db3693bf ] + +The kernel fails to fully detect these SSDs, only the character devices +are present: + +[ 10.785605] nvme nvme0: pci function 0000:04:00.0 +[ 10.876787] nvme nvme1: pci function 0000:81:00.0 +[ 13.198614] nvme nvme0: missing or invalid SUBNQN field. +[ 13.198658] nvme nvme1: missing or invalid SUBNQN field. +[ 13.206896] nvme nvme0: Shutdown timeout set to 20 seconds +[ 13.215035] nvme nvme1: Shutdown timeout set to 20 seconds +[ 13.225407] nvme nvme0: 16/0/0 default/read/poll queues +[ 13.233602] nvme nvme1: 16/0/0 default/read/poll queues +[ 13.239627] nvme nvme0: Identify Descriptors failed (8194) +[ 13.246315] nvme nvme1: Identify Descriptors failed (8194) + +Adding the NVME_QUIRK_NO_NS_DESC_LIST fixes this problem. + +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=205679 +Signed-off-by: Julian Einwag +Signed-off-by: Christoph Hellwig +Reviewed-by: Keith Busch +Signed-off-by: Sasha Levin +--- + drivers/nvme/host/pci.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c +index 6bad4d4dcdf0..7a38d764b486 100644 +--- a/drivers/nvme/host/pci.c ++++ b/drivers/nvme/host/pci.c +@@ -3230,7 +3230,8 @@ static const struct pci_device_id nvme_id_table[] = { + { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ + .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, }, + { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ +- .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, ++ .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | ++ NVME_QUIRK_NO_NS_DESC_LIST, }, + { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ + .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, + { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ +-- +2.30.1 + diff --git a/queue-5.11/pci-cadence-retrain-link-to-work-around-gen2-trainin.patch b/queue-5.11/pci-cadence-retrain-link-to-work-around-gen2-trainin.patch new file mode 100644 index 00000000000..80b53f43078 --- /dev/null +++ b/queue-5.11/pci-cadence-retrain-link-to-work-around-gen2-trainin.patch @@ -0,0 +1,202 @@ +From 7eed9052367022eb3654be70eec211c4d8d6c575 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 9 Feb 2021 15:46:21 +0100 +Subject: PCI: cadence: Retrain Link to work around Gen2 training defect + +From: Nadeem Athani + +[ Upstream commit 4740b969aaf58adeca6829947a3ad8da423976cf ] + +Cadence controller will not initiate autonomous speed change if strapped +as Gen2. The Retrain Link bit is set as quirk to enable this speed change. + +Link: https://lore.kernel.org/r/20210209144622.26683-3-nadeem@cadence.com +Signed-off-by: Nadeem Athani +Signed-off-by: Lorenzo Pieralisi +Signed-off-by: Sasha Levin +--- + drivers/pci/controller/cadence/pci-j721e.c | 3 + + .../controller/cadence/pcie-cadence-host.c | 81 ++++++++++++++----- + drivers/pci/controller/cadence/pcie-cadence.h | 11 ++- + 3 files changed, 76 insertions(+), 19 deletions(-) + +diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c +index dac1ac8a7615..849f1e416ea5 100644 +--- a/drivers/pci/controller/cadence/pci-j721e.c ++++ b/drivers/pci/controller/cadence/pci-j721e.c +@@ -64,6 +64,7 @@ enum j721e_pcie_mode { + + struct j721e_pcie_data { + enum j721e_pcie_mode mode; ++ bool quirk_retrain_flag; + }; + + static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) +@@ -280,6 +281,7 @@ static struct pci_ops cdns_ti_pcie_host_ops = { + + static const struct j721e_pcie_data j721e_pcie_rc_data = { + .mode = PCI_MODE_RC, ++ .quirk_retrain_flag = true, + }; + + static const struct j721e_pcie_data j721e_pcie_ep_data = { +@@ -388,6 +390,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) + + bridge->ops = &cdns_ti_pcie_host_ops; + rc = pci_host_bridge_priv(bridge); ++ rc->quirk_retrain_flag = data->quirk_retrain_flag; + + cdns_pcie = &rc->pcie; + cdns_pcie->dev = dev; +diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c +index 1cb7cfc75d6e..73dcf8cf98fb 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence-host.c ++++ b/drivers/pci/controller/cadence/pcie-cadence-host.c +@@ -77,6 +77,68 @@ static struct pci_ops cdns_pcie_host_ops = { + .write = pci_generic_config_write, + }; + ++static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) ++{ ++ struct device *dev = pcie->dev; ++ int retries; ++ ++ /* Check if the link is up or not */ ++ for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { ++ if (cdns_pcie_link_up(pcie)) { ++ dev_info(dev, "Link up\n"); ++ return 0; ++ } ++ usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); ++ } ++ ++ return -ETIMEDOUT; ++} ++ ++static int cdns_pcie_retrain(struct cdns_pcie *pcie) ++{ ++ u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; ++ u16 lnk_stat, lnk_ctl; ++ int ret = 0; ++ ++ /* ++ * Set retrain bit if current speed is 2.5 GB/s, ++ * but the PCIe root port support is > 2.5 GB/s. ++ */ ++ ++ lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + ++ PCI_EXP_LNKCAP)); ++ if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) ++ return ret; ++ ++ lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); ++ if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { ++ lnk_ctl = cdns_pcie_rp_readw(pcie, ++ pcie_cap_off + PCI_EXP_LNKCTL); ++ lnk_ctl |= PCI_EXP_LNKCTL_RL; ++ cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, ++ lnk_ctl); ++ ++ ret = cdns_pcie_host_wait_for_link(pcie); ++ } ++ return ret; ++} ++ ++static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ int ret; ++ ++ ret = cdns_pcie_host_wait_for_link(pcie); ++ ++ /* ++ * Retrain link for Gen2 training defect ++ * if quirk flag is set. ++ */ ++ if (!ret && rc->quirk_retrain_flag) ++ ret = cdns_pcie_retrain(pcie); ++ ++ return ret; ++} + + static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) + { +@@ -399,23 +461,6 @@ static int cdns_pcie_host_init(struct device *dev, + return cdns_pcie_host_init_address_translation(rc); + } + +-static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) +-{ +- struct device *dev = pcie->dev; +- int retries; +- +- /* Check if the link is up or not */ +- for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { +- if (cdns_pcie_link_up(pcie)) { +- dev_info(dev, "Link up\n"); +- return 0; +- } +- usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); +- } +- +- return -ETIMEDOUT; +-} +- + int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) + { + struct device *dev = rc->pcie.dev; +@@ -458,7 +503,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) + return ret; + } + +- ret = cdns_pcie_host_wait_for_link(pcie); ++ ret = cdns_pcie_host_start_link(rc); + if (ret) + dev_dbg(dev, "PCIe link never came up\n"); + +diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h +index 30eba6cafe2c..254d2570f8c9 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence.h ++++ b/drivers/pci/controller/cadence/pcie-cadence.h +@@ -119,7 +119,7 @@ + * Root Port Registers (PCI configuration space for the root port function) + */ + #define CDNS_PCIE_RP_BASE 0x00200000 +- ++#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 + + /* + * Address Translation Registers +@@ -291,6 +291,7 @@ struct cdns_pcie { + * @device_id: PCI device ID + * @avail_ib_bar: Satus of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or + * available ++ * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 + */ + struct cdns_pcie_rc { + struct cdns_pcie pcie; +@@ -299,6 +300,7 @@ struct cdns_pcie_rc { + u32 vendor_id; + u32 device_id; + bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; ++ bool quirk_retrain_flag; + }; + + /** +@@ -414,6 +416,13 @@ static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, + cdns_pcie_write_sz(addr, 0x2, value); + } + ++static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) ++{ ++ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; ++ ++ return cdns_pcie_read_sz(addr, 0x2); ++} ++ + /* Endpoint Function register access */ + static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, + u32 reg, u8 value) +-- +2.30.1 + diff --git a/queue-5.11/scsi-ufs-add-a-quirk-to-permit-overriding-unipro-def.patch b/queue-5.11/scsi-ufs-add-a-quirk-to-permit-overriding-unipro-def.patch new file mode 100644 index 00000000000..eb6ec4e9908 --- /dev/null +++ b/queue-5.11/scsi-ufs-add-a-quirk-to-permit-overriding-unipro-def.patch @@ -0,0 +1,110 @@ +From d793ed7a38065e145daa7e461f9f8c26bdc3b5f9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 21 Dec 2020 10:24:40 +0900 +Subject: scsi: ufs: Add a quirk to permit overriding UniPro defaults + +From: Kiwoong Kim + +[ Upstream commit b1d0d2eb89d4e3a25b212a9d836587503537067e ] + +The UniPro specification states that attribute IDs of the following +parameters are vendor-specific so some SoCs could have no regions at the +defined addresses: + + - DME_LocalFC0ProtectionTimeOutVal + - DME_LocalTC0ReplayTimeOutVal + - DME_LocalAFC0ReqTimeOutVal + +In addition, the following parameters should be set considering the +compatibility between host and device. + + - PA_PWRMODEUSERDATA0 + - PA_PWRMODEUSERDATA1 + - PA_PWRMODEUSERDATA2 + - PA_PWRMODEUSERDATA3 + - PA_PWRMODEUSERDATA4 + - PA_PWRMODEUSERDATA5 + +Introduce a quirk to allow vendor drivers to override the UniPro defaults. + +Link: https://lore.kernel.org/r/1fedd3dea0ccc980913a5995a10510d86a5b01b9.1608513782.git.kwmad.kim@samsung.com +Acked-by: Avri Altman +Signed-off-by: Kiwoong Kim +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +--- + drivers/scsi/ufs/ufshcd.c | 40 ++++++++++++++++++++------------------- + drivers/scsi/ufs/ufshcd.h | 6 ++++++ + 2 files changed, 27 insertions(+), 19 deletions(-) + +diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c +index 728168cd18f5..8ecdd53c9746 100644 +--- a/drivers/scsi/ufs/ufshcd.c ++++ b/drivers/scsi/ufs/ufshcd.c +@@ -4220,25 +4220,27 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba, + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), + pwr_mode->hs_rate); + +- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), +- DL_FC0ProtectionTimeOutVal_Default); +- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), +- DL_TC0ReplayTimeOutVal_Default); +- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), +- DL_AFC0ReqTimeOutVal_Default); +- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), +- DL_FC1ProtectionTimeOutVal_Default); +- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), +- DL_TC1ReplayTimeOutVal_Default); +- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), +- DL_AFC1ReqTimeOutVal_Default); +- +- ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), +- DL_FC0ProtectionTimeOutVal_Default); +- ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), +- DL_TC0ReplayTimeOutVal_Default); +- ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), +- DL_AFC0ReqTimeOutVal_Default); ++ if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) { ++ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), ++ DL_FC0ProtectionTimeOutVal_Default); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), ++ DL_TC0ReplayTimeOutVal_Default); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), ++ DL_AFC0ReqTimeOutVal_Default); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), ++ DL_FC1ProtectionTimeOutVal_Default); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), ++ DL_TC1ReplayTimeOutVal_Default); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), ++ DL_AFC1ReqTimeOutVal_Default); ++ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), ++ DL_FC0ProtectionTimeOutVal_Default); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), ++ DL_TC0ReplayTimeOutVal_Default); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), ++ DL_AFC0ReqTimeOutVal_Default); ++ } + + ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 + | pwr_mode->pwr_tx); +diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h +index aa9ea3552323..85f9d0fbfbd9 100644 +--- a/drivers/scsi/ufs/ufshcd.h ++++ b/drivers/scsi/ufs/ufshcd.h +@@ -551,6 +551,12 @@ enum ufshcd_quirks { + */ + UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, + ++ /* ++ * This quirk needs to disable unipro timeout values ++ * before power mode change ++ */ ++ UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, ++ + }; + + enum ufshcd_caps { +-- +2.30.1 + diff --git a/queue-5.11/scsi-ufs-fix-a-duplicate-dev-quirk-number.patch b/queue-5.11/scsi-ufs-fix-a-duplicate-dev-quirk-number.patch new file mode 100644 index 00000000000..9a6b81b1617 --- /dev/null +++ b/queue-5.11/scsi-ufs-fix-a-duplicate-dev-quirk-number.patch @@ -0,0 +1,35 @@ +From 709c5871bcc1519ec07bb8f5a034e4daf544ffa8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 11 Feb 2021 12:46:38 +0200 +Subject: scsi: ufs: Fix a duplicate dev quirk number + +From: Avri Altman + +[ Upstream commit 9599a1cf23330008d90b7c232efe95de7510ff29 ] + +Fixes: 2b2bfc8aa519 ("scsi: ufs: Introduce a quirk to allow only page-aligned sg entries") +Link: https://lore.kernel.org/r/20210211104638.292499-1-avri.altman@wdc.com +Reviewed-by: Bean Huo +Signed-off-by: Avri Altman +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +--- + drivers/scsi/ufs/ufshcd.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h +index 8cb64ae95462..1885ec9126c4 100644 +--- a/drivers/scsi/ufs/ufshcd.h ++++ b/drivers/scsi/ufs/ufshcd.h +@@ -560,7 +560,7 @@ enum ufshcd_quirks { + /* + * This quirk allows only sg entries aligned with page size. + */ +- UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE = 1 << 13, ++ UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE = 1 << 14, + }; + + enum ufshcd_caps { +-- +2.30.1 + diff --git a/queue-5.11/scsi-ufs-introduce-a-quirk-to-allow-only-page-aligne.patch b/queue-5.11/scsi-ufs-introduce-a-quirk-to-allow-only-page-aligne.patch new file mode 100644 index 00000000000..d9e0042749b --- /dev/null +++ b/queue-5.11/scsi-ufs-introduce-a-quirk-to-allow-only-page-aligne.patch @@ -0,0 +1,67 @@ +From ea6da28f04ee02a8ec23a0e57833987d27df9716 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Jan 2021 12:33:41 +0900 +Subject: scsi: ufs: Introduce a quirk to allow only page-aligned sg entries + +From: Kiwoong Kim + +[ Upstream commit 2b2bfc8aa519f696087475ed8e8c61850c673272 ] + +Some SoCs require a single scatterlist entry for smaller than page size, +i.e. 4KB. When dispatching commands with more than one scatterlist entry +under 4KB in size the following behavior is observed: + +A command to read a block range is dispatched with two scatterlist entries +that are named AAA and BBB. After dispatching, the host builds two PRDT +entries and during transmission, device sends just one DATA IN because +device doesn't care about host DMA. The host then transfers the combined +amount of data from start address of the area named AAA. As a consequence, +the area that follows AAA in memory would be corrupted. + + |<------------->| + +-------+------------ +-------+ + + AAA + (corrupted) ... + BBB + + +-------+------------ +-------+ + +To avoid this we need to enforce page size alignment for sg entries. + +Link: https://lore.kernel.org/r/56dddef94f60bd9466fd77e69f64bbbd657ed2a1.1611026909.git.kwmad.kim@samsung.com +Signed-off-by: Kiwoong Kim +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +--- + drivers/scsi/ufs/ufshcd.c | 2 ++ + drivers/scsi/ufs/ufshcd.h | 4 ++++ + 2 files changed, 6 insertions(+) + +diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c +index 8ecdd53c9746..428b9e0ac47e 100644 +--- a/drivers/scsi/ufs/ufshcd.c ++++ b/drivers/scsi/ufs/ufshcd.c +@@ -4831,6 +4831,8 @@ static int ufshcd_slave_configure(struct scsi_device *sdev) + struct request_queue *q = sdev->request_queue; + + blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1); ++ if (hba->quirks & UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE) ++ blk_queue_update_dma_alignment(q, PAGE_SIZE - 1); + + if (ufshcd_is_rpm_autosuspend_allowed(hba)) + sdev->rpm_autosuspend = 1; +diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h +index 85f9d0fbfbd9..8cb64ae95462 100644 +--- a/drivers/scsi/ufs/ufshcd.h ++++ b/drivers/scsi/ufs/ufshcd.h +@@ -557,6 +557,10 @@ enum ufshcd_quirks { + */ + UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, + ++ /* ++ * This quirk allows only sg entries aligned with page size. ++ */ ++ UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE = 1 << 13, + }; + + enum ufshcd_caps { +-- +2.30.1 + diff --git a/queue-5.11/scsi-ufs-mediatek-enable-ufshci_quirk_skip_manual_wb.patch b/queue-5.11/scsi-ufs-mediatek-enable-ufshci_quirk_skip_manual_wb.patch new file mode 100644 index 00000000000..bd14916e614 --- /dev/null +++ b/queue-5.11/scsi-ufs-mediatek-enable-ufshci_quirk_skip_manual_wb.patch @@ -0,0 +1,37 @@ +From e154dc45e8e46be16dcb9822ce3aaf9c6e375740 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 22 Dec 2020 15:29:28 +0800 +Subject: scsi: ufs-mediatek: Enable UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL + +From: Stanley Chu + +[ Upstream commit 46ec9592ffd679fa26142dcb9e5119aad7e60b55 ] + +Flush during hibern8 is sufficient on MediaTek platforms, thus enable +UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL to skip enabling +fWriteBoosterBufferFlush during WriteBooster initialization. + +Link: https://lore.kernel.org/r/20201222072928.32328-1-stanley.chu@mediatek.com +Reviewed-by: Avri Altman +Signed-off-by: Stanley Chu +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +--- + drivers/scsi/ufs/ufs-mediatek.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c +index 80618af7c872..c55202b92a43 100644 +--- a/drivers/scsi/ufs/ufs-mediatek.c ++++ b/drivers/scsi/ufs/ufs-mediatek.c +@@ -661,6 +661,7 @@ static int ufs_mtk_init(struct ufs_hba *hba) + + /* Enable WriteBooster */ + hba->caps |= UFSHCD_CAP_WB_EN; ++ hba->quirks |= UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL; + hba->vps->wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(80); + + if (host->caps & UFS_MTK_CAP_DISABLE_AH8) +-- +2.30.1 + diff --git a/queue-5.11/scsi-ufs-ufs-exynos-apply-vendor-specific-values-for.patch b/queue-5.11/scsi-ufs-ufs-exynos-apply-vendor-specific-values-for.patch new file mode 100644 index 00000000000..27ea6313dda --- /dev/null +++ b/queue-5.11/scsi-ufs-ufs-exynos-apply-vendor-specific-values-for.patch @@ -0,0 +1,55 @@ +From 7194800b6853e94f45c716728a05e9a62077916b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 21 Dec 2020 10:24:41 +0900 +Subject: scsi: ufs: ufs-exynos: Apply vendor-specific values for three + timeouts + +From: Kiwoong Kim + +[ Upstream commit a967ddb22d94eb476ccef983b5f2730fa4d184d0 ] + +Set optimized values for the following timeouts: + + - FC0_PROTECTION_TIMER + - TC0_REPLAY_TIMER + - AFC0_REQUEST_TIMER + +Exynos doesn't yet use traffic class #1. + +Link: https://lore.kernel.org/r/a0ff44f665a4f31d2f945fd71de03571204c576c.1608513782.git.kwmad.kim@samsung.com +Signed-off-by: Kiwoong Kim +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +--- + drivers/scsi/ufs/ufs-exynos.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c +index a8770ff14588..5ca21d1550df 100644 +--- a/drivers/scsi/ufs/ufs-exynos.c ++++ b/drivers/scsi/ufs/ufs-exynos.c +@@ -640,6 +640,11 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, + } + } + ++ /* setting for three timeout values for traffic class #0 */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 8064); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 28224); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 20160); ++ + return 0; + out: + return ret; +@@ -1236,7 +1241,8 @@ struct exynos_ufs_drv_data exynos_ufs_drvs = { + UFSHCI_QUIRK_BROKEN_HCE | + UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | + UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | +- UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL, ++ UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL | ++ UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, + .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL | + EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | + EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX | +-- +2.30.1 + diff --git a/queue-5.11/scsi-ufs-ufs-exynos-use-ufshcd_quirk_align_sg_with_p.patch b/queue-5.11/scsi-ufs-ufs-exynos-use-ufshcd_quirk_align_sg_with_p.patch new file mode 100644 index 00000000000..900de29aab7 --- /dev/null +++ b/queue-5.11/scsi-ufs-ufs-exynos-use-ufshcd_quirk_align_sg_with_p.patch @@ -0,0 +1,38 @@ +From 8db69b92a3e72b3ab73ce013bfbe4e3630a24914 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Jan 2021 12:33:42 +0900 +Subject: scsi: ufs: ufs-exynos: Use UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE + +From: Kiwoong Kim + +[ Upstream commit f1ef9047aaab036edb39261b0a7a6bdcf3010b87 ] + +Exynos needs scatterlist entries aligned to page size because it isn't +capable of transferring data contained in one DATA IN operation to seversal +areas in memory. + +Link: https://lore.kernel.org/r/80d7e27d6ec537e650a6bd74897b6c60618efcdc.1611026909.git.kwmad.kim@samsung.com +Signed-off-by: Kiwoong Kim +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +--- + drivers/scsi/ufs/ufs-exynos.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c +index 5ca21d1550df..267943a13a94 100644 +--- a/drivers/scsi/ufs/ufs-exynos.c ++++ b/drivers/scsi/ufs/ufs-exynos.c +@@ -1242,7 +1242,8 @@ struct exynos_ufs_drv_data exynos_ufs_drvs = { + UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | + UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | + UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL | +- UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, ++ UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING | ++ UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE, + .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL | + EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | + EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX | +-- +2.30.1 + diff --git a/queue-5.11/series b/queue-5.11/series index c73e97314fe..64de92ee4cc 100644 --- a/queue-5.11/series +++ b/queue-5.11/series @@ -1 +1,21 @@ acpica-fix-race-in-generic_serial_bus-i2c-and-gpio-op_region-parameter-handling.patch +scsi-ufs-mediatek-enable-ufshci_quirk_skip_manual_wb.patch +scsi-ufs-add-a-quirk-to-permit-overriding-unipro-def.patch +misc-eeprom_93xx46-add-quirk-to-support-microchip-93.patch +scsi-ufs-introduce-a-quirk-to-allow-only-page-aligne.patch +scsi-ufs-ufs-exynos-apply-vendor-specific-values-for.patch +scsi-ufs-ufs-exynos-use-ufshcd_quirk_align_sg_with_p.patch +drm-msm-a5xx-remove-overwriting-a5xx_pc_dbg_eco_cntl.patch +mmc-sdhci-of-dwcmshc-set-sdhci_quirk2_preset_value_b.patch +hid-i2c-hid-add-i2c_hid_quirk_no_irq_after_reset-for.patch +alsa-usb-audio-add-djm750-to-pioneer-mixer-quirk.patch +alsa-usb-audio-add-mixer-quirks-for-pioneer-djm-900n.patch +hid-ite-enable-quirk_touchpad_on_off_report-on-acer-.patch +pci-cadence-retrain-link-to-work-around-gen2-trainin.patch +asoc-intel-sof_sdw-reorganize-quirks-by-generation.patch +asoc-intel-sof_sdw-add-quirk-for-hp-spectre-x360-con.patch +scsi-ufs-fix-a-duplicate-dev-quirk-number.patch +kvm-svm-clear-the-cr4-register-on-reset.patch +nvme-pci-mark-seagate-nytro-xm1440-as-quirk_no_ns_de.patch +nvme-pci-mark-kingston-skc2000-as-not-supporting-the.patch +nvme-pci-add-quirks-for-lexar-256gb-ssd.patch