From: Greg Kroah-Hartman Date: Mon, 10 Nov 2014 04:05:33 +0000 (+0900) Subject: 3.17-stable patches X-Git-Tag: v3.10.60~50 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=18d876facd1d8fe1213bdc7328d36ec9a4a8a3c2;p=thirdparty%2Fkernel%2Fstable-queue.git 3.17-stable patches added patches: cpufreq-expose-scaling_cur_freq-sysfs-file-for-set_policy-drivers.patch cpufreq-intel_pstate-fix-setting-max_perf_pct-in-performance-policy.patch cpufreq-intel_pstate-reflect-current-no_turbo-state-correctly.patch x86-add-cpu_detect_cache_sizes-to-init_intel-add-quark-legacy_cache.patch x86-platform-intel-iosf-add-braswell-pci-id.patch --- diff --git a/queue-3.17/cpufreq-expose-scaling_cur_freq-sysfs-file-for-set_policy-drivers.patch b/queue-3.17/cpufreq-expose-scaling_cur_freq-sysfs-file-for-set_policy-drivers.patch new file mode 100644 index 00000000000..24135082932 --- /dev/null +++ b/queue-3.17/cpufreq-expose-scaling_cur_freq-sysfs-file-for-set_policy-drivers.patch @@ -0,0 +1,63 @@ +From c034b02e213d271b98c45c4a7b54af8f69aaac1e Mon Sep 17 00:00:00 2001 +From: Dirk Brandewie +Date: Mon, 13 Oct 2014 08:37:40 -0700 +Subject: cpufreq: expose scaling_cur_freq sysfs file for set_policy() drivers + +From: Dirk Brandewie + +commit c034b02e213d271b98c45c4a7b54af8f69aaac1e upstream. + +Currently the core does not expose scaling_cur_freq for set_policy() +drivers this breaks some userspace monitoring tools. +Change the core to expose this file for all drivers and if the +set_policy() driver supports the get() callback use it to retrieve the +current frequency. + +Link: https://bugzilla.kernel.org/show_bug.cgi?id=73741 +Signed-off-by: Dirk Brandewie +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/cpufreq/cpufreq.c | 23 +++++++++++++++++------ + 1 file changed, 17 insertions(+), 6 deletions(-) + +--- a/drivers/cpufreq/cpufreq.c ++++ b/drivers/cpufreq/cpufreq.c +@@ -512,7 +512,18 @@ show_one(cpuinfo_max_freq, cpuinfo.max_f + show_one(cpuinfo_transition_latency, cpuinfo.transition_latency); + show_one(scaling_min_freq, min); + show_one(scaling_max_freq, max); +-show_one(scaling_cur_freq, cur); ++ ++static ssize_t show_scaling_cur_freq( ++ struct cpufreq_policy *policy, char *buf) ++{ ++ ssize_t ret; ++ ++ if (cpufreq_driver && cpufreq_driver->setpolicy && cpufreq_driver->get) ++ ret = sprintf(buf, "%u\n", cpufreq_driver->get(policy->cpu)); ++ else ++ ret = sprintf(buf, "%u\n", policy->cur); ++ return ret; ++} + + static int cpufreq_set_policy(struct cpufreq_policy *policy, + struct cpufreq_policy *new_policy); +@@ -906,11 +917,11 @@ static int cpufreq_add_dev_interface(str + if (ret) + goto err_out_kobj_put; + } +- if (has_target()) { +- ret = sysfs_create_file(&policy->kobj, &scaling_cur_freq.attr); +- if (ret) +- goto err_out_kobj_put; +- } ++ ++ ret = sysfs_create_file(&policy->kobj, &scaling_cur_freq.attr); ++ if (ret) ++ goto err_out_kobj_put; ++ + if (cpufreq_driver->bios_limit) { + ret = sysfs_create_file(&policy->kobj, &bios_limit.attr); + if (ret) diff --git a/queue-3.17/cpufreq-intel_pstate-fix-setting-max_perf_pct-in-performance-policy.patch b/queue-3.17/cpufreq-intel_pstate-fix-setting-max_perf_pct-in-performance-policy.patch new file mode 100644 index 00000000000..0a8eb4c6888 --- /dev/null +++ b/queue-3.17/cpufreq-intel_pstate-fix-setting-max_perf_pct-in-performance-policy.patch @@ -0,0 +1,76 @@ +From 36b4bed5cd8f6e17019fa7d380e0836872c7b367 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Thu, 16 Oct 2014 01:16:51 +0200 +Subject: cpufreq: intel_pstate: Fix setting max_perf_pct in performance policy +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= + +commit 36b4bed5cd8f6e17019fa7d380e0836872c7b367 upstream. + +Code which changes policy to powersave changes also max_policy_pct based on +max_freq. Code which change max_perf_pct has upper limit base on value +max_policy_pct. When policy is changing from powersave back to performance +then max_policy_pct is not changed. Which means that changing max_perf_pct is +not possible to high values if max_freq was too low in powersave policy. + +Test case: + +$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq +800000 +$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq +3300000 +$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor +performance +$ cat /sys/devices/system/cpu/intel_pstate/max_perf_pct +100 + +$ echo powersave > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor +$ echo 800000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq +$ echo 20 > /sys/devices/system/cpu/intel_pstate/max_perf_pct + +$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor +powersave +$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq +800000 +$ cat /sys/devices/system/cpu/intel_pstate/max_perf_pct +20 + +$ echo performance > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor +$ echo 3300000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq +$ echo 100 > /sys/devices/system/cpu/intel_pstate/max_perf_pct + +$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor +performance +$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq +3300000 +$ cat /sys/devices/system/cpu/intel_pstate/max_perf_pct +24 + +And now intel_pstate driver allows to set maximal value for max_perf_pct based +on max_policy_pct which is 24 for previous powersave max_freq 800000. + +This patch will set default value for max_policy_pct when setting policy to +performance so it will allow to set also max value for max_perf_pct. + +Signed-off-by: Pali Rohár +Acked-by: Dirk Brandewie +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/cpufreq/intel_pstate.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/cpufreq/intel_pstate.c ++++ b/drivers/cpufreq/intel_pstate.c +@@ -745,6 +745,7 @@ static int intel_pstate_set_policy(struc + if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { + limits.min_perf_pct = 100; + limits.min_perf = int_tofp(1); ++ limits.max_policy_pct = 100; + limits.max_perf_pct = 100; + limits.max_perf = int_tofp(1); + limits.no_turbo = 0; diff --git a/queue-3.17/cpufreq-intel_pstate-reflect-current-no_turbo-state-correctly.patch b/queue-3.17/cpufreq-intel_pstate-reflect-current-no_turbo-state-correctly.patch new file mode 100644 index 00000000000..a356876f117 --- /dev/null +++ b/queue-3.17/cpufreq-intel_pstate-reflect-current-no_turbo-state-correctly.patch @@ -0,0 +1,148 @@ +From 4521e1a0ce173daa23dfef8312d09051e057ff8e Mon Sep 17 00:00:00 2001 +From: Gabriele Mazzotta +Date: Mon, 13 Oct 2014 08:37:41 -0700 +Subject: cpufreq: intel_pstate: Reflect current no_turbo state correctly + +From: Gabriele Mazzotta + +commit 4521e1a0ce173daa23dfef8312d09051e057ff8e upstream. + +Some BIOSes modify the state of MSR_IA32_MISC_ENABLE_TURBO_DISABLE +based on the current power source for the system battery AC vs +battery. Reflect the correct current state and ability to modify the +no_turbo sysfs file based on current state of +MSR_IA32_MISC_ENABLE_TURBO_DISABLE. + +Link: https://bugzilla.kernel.org/show_bug.cgi?id=83151 +Signed-off-by: Gabriele Mazzotta +Signed-off-by: Dirk Brandewie +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/cpufreq/intel_pstate.c | 48 ++++++++++++++++++++++++++++++----------- + 1 file changed, 36 insertions(+), 12 deletions(-) + +--- a/drivers/cpufreq/intel_pstate.c ++++ b/drivers/cpufreq/intel_pstate.c +@@ -138,6 +138,7 @@ struct perf_limits { + + static struct perf_limits limits = { + .no_turbo = 0, ++ .turbo_disabled = 0, + .max_perf_pct = 100, + .max_perf = int_tofp(1), + .min_perf_pct = 0, +@@ -218,6 +219,18 @@ static inline void intel_pstate_reset_al + } + } + ++static inline void update_turbo_state(void) ++{ ++ u64 misc_en; ++ struct cpudata *cpu; ++ ++ cpu = all_cpu_data[0]; ++ rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); ++ limits.turbo_disabled = ++ (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || ++ cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); ++} ++ + /************************** debugfs begin ************************/ + static int pid_param_set(void *data, u64 val) + { +@@ -274,6 +287,20 @@ static void __init intel_pstate_debug_ex + return sprintf(buf, "%u\n", limits.object); \ + } + ++static ssize_t show_no_turbo(struct kobject *kobj, ++ struct attribute *attr, char *buf) ++{ ++ ssize_t ret; ++ ++ update_turbo_state(); ++ if (limits.turbo_disabled) ++ ret = sprintf(buf, "%u\n", limits.turbo_disabled); ++ else ++ ret = sprintf(buf, "%u\n", limits.no_turbo); ++ ++ return ret; ++} ++ + static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, + const char *buf, size_t count) + { +@@ -283,11 +310,14 @@ static ssize_t store_no_turbo(struct kob + ret = sscanf(buf, "%u", &input); + if (ret != 1) + return -EINVAL; +- limits.no_turbo = clamp_t(int, input, 0 , 1); ++ ++ update_turbo_state(); + if (limits.turbo_disabled) { + pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); +- limits.no_turbo = limits.turbo_disabled; ++ return -EPERM; + } ++ limits.no_turbo = clamp_t(int, input, 0, 1); ++ + return count; + } + +@@ -323,7 +353,6 @@ static ssize_t store_min_perf_pct(struct + return count; + } + +-show_one(no_turbo, no_turbo); + show_one(max_perf_pct, max_perf_pct); + show_one(min_perf_pct, min_perf_pct); + +@@ -501,7 +530,7 @@ static void intel_pstate_get_min_max(str + int max_perf_adj; + int min_perf; + +- if (limits.no_turbo) ++ if (limits.no_turbo || limits.turbo_disabled) + max_perf = cpu->pstate.max_pstate; + + max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf)); +@@ -516,6 +545,8 @@ static void intel_pstate_set_pstate(stru + { + int max_perf, min_perf; + ++ update_turbo_state(); ++ + intel_pstate_get_min_max(cpu, &min_perf, &max_perf); + + pstate = clamp_t(int, pstate, min_perf, max_perf); +@@ -716,7 +747,7 @@ static int intel_pstate_set_policy(struc + limits.min_perf = int_tofp(1); + limits.max_perf_pct = 100; + limits.max_perf = int_tofp(1); +- limits.no_turbo = limits.turbo_disabled; ++ limits.no_turbo = 0; + return 0; + } + limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq; +@@ -759,7 +790,6 @@ static int intel_pstate_cpu_init(struct + { + struct cpudata *cpu; + int rc; +- u64 misc_en; + + rc = intel_pstate_init_cpu(policy->cpu); + if (rc) +@@ -767,12 +797,6 @@ static int intel_pstate_cpu_init(struct + + cpu = all_cpu_data[policy->cpu]; + +- rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); +- if (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || +- cpu->pstate.max_pstate == cpu->pstate.turbo_pstate) { +- limits.turbo_disabled = 1; +- limits.no_turbo = 1; +- } + if (limits.min_perf_pct == 100 && limits.max_perf_pct == 100) + policy->policy = CPUFREQ_POLICY_PERFORMANCE; + else diff --git a/queue-3.17/series b/queue-3.17/series index 525f0819129..bcb36fac0a4 100644 --- a/queue-3.17/series +++ b/queue-3.17/series @@ -169,3 +169,8 @@ drm-i915-properly-reenable-gen8-pipe-irqs.patch drm-radeon-fix-speaker-allocation-setup.patch drm-radeon-use-gart-memory-for-dma-ring-tests.patch drm-radeon-fix-vm-page-table-block-size-calculation.patch +cpufreq-expose-scaling_cur_freq-sysfs-file-for-set_policy-drivers.patch +cpufreq-intel_pstate-reflect-current-no_turbo-state-correctly.patch +cpufreq-intel_pstate-fix-setting-max_perf_pct-in-performance-policy.patch +x86-platform-intel-iosf-add-braswell-pci-id.patch +x86-add-cpu_detect_cache_sizes-to-init_intel-add-quark-legacy_cache.patch diff --git a/queue-3.17/x86-add-cpu_detect_cache_sizes-to-init_intel-add-quark-legacy_cache.patch b/queue-3.17/x86-add-cpu_detect_cache_sizes-to-init_intel-add-quark-legacy_cache.patch new file mode 100644 index 00000000000..76011c70557 --- /dev/null +++ b/queue-3.17/x86-add-cpu_detect_cache_sizes-to-init_intel-add-quark-legacy_cache.patch @@ -0,0 +1,86 @@ +From aece118e487a744eafcdd0c77fe32b55ee2092a1 Mon Sep 17 00:00:00 2001 +From: Bryan O'Donoghue +Date: Tue, 7 Oct 2014 01:19:49 +0100 +Subject: x86: Add cpu_detect_cache_sizes to init_intel() add Quark legacy_cache() + +From: Bryan O'Donoghue + +commit aece118e487a744eafcdd0c77fe32b55ee2092a1 upstream. + +Intel processors which don't report cache information via cpuid(2) +or cpuid(4) need quirk code in the legacy_cache_size callback to +report this data. For Intel that callback is is intel_size_cache(). + +This patch enables calling of cpu_detect_cache_sizes() inside of +init_intel() and hence the calling of the legacy_cache callback in +intel_size_cache(). Adding this call will ensure that PIII Tualatin +currently in intel_size_cache() and Quark SoC X1000 being added to +intel_size_cache() in this patch will report their respective cache +sizes. + +This model of calling cpu_detect_cache_sizes() is consistent with +AMD/Via/Cirix/Transmeta and Centaur. + +Also added is a string to idenitfy the Quark as Quark SoC X1000 +giving better and more descriptive output via /proc/cpuinfo + +Adding cpu_detect_cache_sizes to init_intel() will enable calling +of intel_size_cache() on Intel processors which currently no code +can reach. Therefore this patch will also re-enable reporting +of PIII Tualatin cache size information as well as add +Quark SoC X1000 support. + +Comment text and cache flow logic suggested by Thomas Gleixner + +Signed-off-by: Bryan O'Donoghue +Cc: davej@redhat.com +Cc: hmh@hmh.eng.br +Link: http://lkml.kernel.org/r/1412641189-12415-3-git-send-email-pure.logic@nexus-software.ie +Signed-off-by: Thomas Gleixner +Signed-off-by: Chang Rebecca Swee Fun +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/kernel/cpu/intel.c | 17 ++++++++++++++++- + 1 file changed, 16 insertions(+), 1 deletion(-) + +--- a/arch/x86/kernel/cpu/intel.c ++++ b/arch/x86/kernel/cpu/intel.c +@@ -397,6 +397,13 @@ static void init_intel(struct cpuinfo_x8 + } + + l2 = init_intel_cacheinfo(c); ++ ++ /* Detect legacy cache sizes if init_intel_cacheinfo did not */ ++ if (l2 == 0) { ++ cpu_detect_cache_sizes(c); ++ l2 = c->x86_cache_size; ++ } ++ + if (c->cpuid_level > 9) { + unsigned eax = cpuid_eax(10); + /* Check for version and the number of counters */ +@@ -500,6 +507,13 @@ static unsigned int intel_size_cache(str + */ + if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) + size = 256; ++ ++ /* ++ * Intel Quark SoC X1000 contains a 4-way set associative ++ * 16K cache with a 16 byte cache line and 256 lines per tag ++ */ ++ if ((c->x86 == 5) && (c->x86_model == 9)) ++ size = 16; + return size; + } + #endif +@@ -701,7 +715,8 @@ static const struct cpu_dev intel_cpu_de + [3] = "OverDrive PODP5V83", + [4] = "Pentium MMX", + [7] = "Mobile Pentium 75 - 200", +- [8] = "Mobile Pentium MMX" ++ [8] = "Mobile Pentium MMX", ++ [9] = "Quark SoC X1000", + } + }, + { .family = 6, .model_names = diff --git a/queue-3.17/x86-platform-intel-iosf-add-braswell-pci-id.patch b/queue-3.17/x86-platform-intel-iosf-add-braswell-pci-id.patch new file mode 100644 index 00000000000..3ac9547ef87 --- /dev/null +++ b/queue-3.17/x86-platform-intel-iosf-add-braswell-pci-id.patch @@ -0,0 +1,39 @@ +From 849f5d894383d25c49132437aa289c9a9c98d5df Mon Sep 17 00:00:00 2001 +From: "David E. Box" +Date: Wed, 17 Sep 2014 22:13:49 -0700 +Subject: x86/platform/intel/iosf: Add Braswell PCI ID + +From: "David E. Box" + +commit 849f5d894383d25c49132437aa289c9a9c98d5df upstream. + +Add Braswell PCI ID to list of supported ID's for the IOSF driver. + +Signed-off-by: David E. Box +Link: http://lkml.kernel.org/r/1411017231-20807-2-git-send-email-david.e.box@linux.intel.com +Signed-off-by: Ingo Molnar +Signed-off-by: Chang Rebecca Swee Fun +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/kernel/iosf_mbi.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/x86/kernel/iosf_mbi.c ++++ b/arch/x86/kernel/iosf_mbi.c +@@ -26,6 +26,7 @@ + #include + + #define PCI_DEVICE_ID_BAYTRAIL 0x0F00 ++#define PCI_DEVICE_ID_BRASWELL 0x2280 + #define PCI_DEVICE_ID_QUARK_X1000 0x0958 + + static DEFINE_SPINLOCK(iosf_mbi_lock); +@@ -204,6 +205,7 @@ static int iosf_mbi_probe(struct pci_dev + + static const struct pci_device_id iosf_mbi_pci_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BAYTRAIL) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRASWELL) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_QUARK_X1000) }, + { 0, }, + };