From: Greg Kroah-Hartman Date: Fri, 24 Nov 2023 14:54:49 +0000 (+0000) Subject: 6.1-stable patches X-Git-Tag: v4.14.331~39 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=19456d970e8615d4415377608101de68585e90e4;p=thirdparty%2Fkernel%2Fstable-queue.git 6.1-stable patches added patches: drm-amd-display-change-the-dmcub-mailbox-memory-location-from-fb-to-inbox.patch drm-amd-display-enable-fast-plane-updates-on-dcn3.2-and-above.patch drm-amd-display-fix-a-null-pointer-dereference-in-amdgpu_dm_i2c_xfer.patch drm-amd-pm-fix-error-of-maco-flag-setting-code.patch drm-amdgpu-don-t-use-atrm-for-external-devices.patch drm-amdgpu-don-t-use-pci_is_thunderbolt_attached.patch drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_get.patch drm-amdgpu-lower-cs-errors-to-debug-severity.patch drm-amdgpu-smu13-drop-compute-workload-workaround.patch drm-i915-bump-glk-cdclk-frequency-when-driving-multiple-pipes.patch drm-i915-fix-potential-spectre-vulnerability.patch --- diff --git a/queue-6.1/drm-amd-display-change-the-dmcub-mailbox-memory-location-from-fb-to-inbox.patch b/queue-6.1/drm-amd-display-change-the-dmcub-mailbox-memory-location-from-fb-to-inbox.patch new file mode 100644 index 00000000000..df996fc9835 --- /dev/null +++ b/queue-6.1/drm-amd-display-change-the-dmcub-mailbox-memory-location-from-fb-to-inbox.patch @@ -0,0 +1,208 @@ +From 5911d02cac70d7fb52009fbd37423e63f8f6f9bc Mon Sep 17 00:00:00 2001 +From: Lewis Huang +Date: Thu, 19 Oct 2023 17:22:21 +0800 +Subject: drm/amd/display: Change the DMCUB mailbox memory location from FB to inbox + +From: Lewis Huang + +commit 5911d02cac70d7fb52009fbd37423e63f8f6f9bc upstream. + +[WHY] +Flush command sent to DMCUB spends more time for execution on +a dGPU than on an APU. This causes cursor lag when using high +refresh rate mouses. + +[HOW] +1. Change the DMCUB mailbox memory location from FB to inbox. +2. Only change windows memory to inbox. + +Cc: Mario Limonciello +Cc: Alex Deucher +Cc: stable@vger.kernel.org +Reviewed-by: Nicholas Kazlauskas +Acked-by: Alex Hung +Signed-off-by: Lewis Huang +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++++---- + drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 22 +++++++++------ + drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 32 ++++++++++++++++------ + 3 files changed, 45 insertions(+), 22 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -2057,7 +2057,7 @@ static int dm_dmub_sw_init(struct amdgpu + struct dmub_srv_create_params create_params; + struct dmub_srv_region_params region_params; + struct dmub_srv_region_info region_info; +- struct dmub_srv_fb_params fb_params; ++ struct dmub_srv_memory_params memory_params; + struct dmub_srv_fb_info *fb_info; + struct dmub_srv *dmub_srv; + const struct dmcub_firmware_header_v1_0 *hdr; +@@ -2188,6 +2188,7 @@ static int dm_dmub_sw_init(struct amdgpu + adev->dm.dmub_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes) + + PSP_HEADER_BYTES; ++ region_params.is_mailbox_in_inbox = false; + + status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, + ®ion_info); +@@ -2209,10 +2210,10 @@ static int dm_dmub_sw_init(struct amdgpu + return r; + + /* Rebase the regions on the framebuffer address. */ +- memset(&fb_params, 0, sizeof(fb_params)); +- fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr; +- fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr; +- fb_params.region_info = ®ion_info; ++ memset(&memory_params, 0, sizeof(memory_params)); ++ memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr; ++ memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr; ++ memory_params.region_info = ®ion_info; + + adev->dm.dmub_fb_info = + kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); +@@ -2224,7 +2225,7 @@ static int dm_dmub_sw_init(struct amdgpu + return -ENOMEM; + } + +- status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info); ++ status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info); + if (status != DMUB_STATUS_OK) { + DRM_ERROR("Error calculating DMUB FB info: %d\n", status); + return -EINVAL; +--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h ++++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +@@ -174,6 +174,7 @@ struct dmub_srv_region_params { + uint32_t vbios_size; + const uint8_t *fw_inst_const; + const uint8_t *fw_bss_data; ++ bool is_mailbox_in_inbox; + }; + + /** +@@ -193,20 +194,25 @@ struct dmub_srv_region_params { + */ + struct dmub_srv_region_info { + uint32_t fb_size; ++ uint32_t inbox_size; + uint8_t num_regions; + struct dmub_region regions[DMUB_WINDOW_TOTAL]; + }; + + /** +- * struct dmub_srv_fb_params - parameters used for driver fb setup ++ * struct dmub_srv_memory_params - parameters used for driver fb setup + * @region_info: region info calculated by dmub service +- * @cpu_addr: base cpu address for the framebuffer +- * @gpu_addr: base gpu virtual address for the framebuffer ++ * @cpu_fb_addr: base cpu address for the framebuffer ++ * @cpu_inbox_addr: base cpu address for the gart ++ * @gpu_fb_addr: base gpu virtual address for the framebuffer ++ * @gpu_inbox_addr: base gpu virtual address for the gart + */ +-struct dmub_srv_fb_params { ++struct dmub_srv_memory_params { + const struct dmub_srv_region_info *region_info; +- void *cpu_addr; +- uint64_t gpu_addr; ++ void *cpu_fb_addr; ++ void *cpu_inbox_addr; ++ uint64_t gpu_fb_addr; ++ uint64_t gpu_inbox_addr; + }; + + /** +@@ -524,8 +530,8 @@ dmub_srv_calc_region_info(struct dmub_sr + * DMUB_STATUS_OK - success + * DMUB_STATUS_INVALID - unspecified error + */ +-enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, +- const struct dmub_srv_fb_params *params, ++enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, ++ const struct dmub_srv_memory_params *params, + struct dmub_srv_fb_info *out); + + /** +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +@@ -384,7 +384,7 @@ dmub_srv_calc_region_info(struct dmub_sr + uint32_t fw_state_size = DMUB_FW_STATE_SIZE; + uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; + uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; +- ++ uint32_t previous_top = 0; + if (!dmub->sw_init) + return DMUB_STATUS_INVALID; + +@@ -409,8 +409,15 @@ dmub_srv_calc_region_info(struct dmub_sr + bios->base = dmub_align(stack->top, 256); + bios->top = bios->base + params->vbios_size; + +- mail->base = dmub_align(bios->top, 256); +- mail->top = mail->base + DMUB_MAILBOX_SIZE; ++ if (params->is_mailbox_in_inbox) { ++ mail->base = 0; ++ mail->top = mail->base + DMUB_MAILBOX_SIZE; ++ previous_top = bios->top; ++ } else { ++ mail->base = dmub_align(bios->top, 256); ++ mail->top = mail->base + DMUB_MAILBOX_SIZE; ++ previous_top = mail->top; ++ } + + fw_info = dmub_get_fw_meta_info(params); + +@@ -429,7 +436,7 @@ dmub_srv_calc_region_info(struct dmub_sr + dmub->fw_version = fw_info->fw_version; + } + +- trace_buff->base = dmub_align(mail->top, 256); ++ trace_buff->base = dmub_align(previous_top, 256); + trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); + + fw_state->base = dmub_align(trace_buff->top, 256); +@@ -440,11 +447,14 @@ dmub_srv_calc_region_info(struct dmub_sr + + out->fb_size = dmub_align(scratch_mem->top, 4096); + ++ if (params->is_mailbox_in_inbox) ++ out->inbox_size = dmub_align(mail->top, 4096); ++ + return DMUB_STATUS_OK; + } + +-enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, +- const struct dmub_srv_fb_params *params, ++enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, ++ const struct dmub_srv_memory_params *params, + struct dmub_srv_fb_info *out) + { + uint8_t *cpu_base; +@@ -459,8 +469,8 @@ enum dmub_status dmub_srv_calc_fb_info(s + if (params->region_info->num_regions != DMUB_NUM_WINDOWS) + return DMUB_STATUS_INVALID; + +- cpu_base = (uint8_t *)params->cpu_addr; +- gpu_base = params->gpu_addr; ++ cpu_base = (uint8_t *)params->cpu_fb_addr; ++ gpu_base = params->gpu_fb_addr; + + for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { + const struct dmub_region *reg = +@@ -468,6 +478,12 @@ enum dmub_status dmub_srv_calc_fb_info(s + + out->fb[i].cpu_addr = cpu_base + reg->base; + out->fb[i].gpu_addr = gpu_base + reg->base; ++ ++ if (i == DMUB_WINDOW_4_MAILBOX && params->cpu_inbox_addr != 0) { ++ out->fb[i].cpu_addr = (uint8_t *)params->cpu_inbox_addr + reg->base; ++ out->fb[i].gpu_addr = params->gpu_inbox_addr + reg->base; ++ } ++ + out->fb[i].size = reg->top - reg->base; + } + diff --git a/queue-6.1/drm-amd-display-enable-fast-plane-updates-on-dcn3.2-and-above.patch b/queue-6.1/drm-amd-display-enable-fast-plane-updates-on-dcn3.2-and-above.patch new file mode 100644 index 00000000000..aeb78db52f3 --- /dev/null +++ b/queue-6.1/drm-amd-display-enable-fast-plane-updates-on-dcn3.2-and-above.patch @@ -0,0 +1,51 @@ +From 435f5b369657cffee4b04db1f5805b48599f4dbe Mon Sep 17 00:00:00 2001 +From: Tianci Yin +Date: Wed, 1 Nov 2023 09:47:13 +0800 +Subject: drm/amd/display: Enable fast plane updates on DCN3.2 and above + +From: Tianci Yin + +commit 435f5b369657cffee4b04db1f5805b48599f4dbe upstream. + +[WHY] +When cursor moves across screen boarder, lag cursor observed, +since subvp settings need to sync up with vblank that causes +cursor updates being delayed. + +[HOW] +Enable fast plane updates on DCN3.2 to fix it. + +Cc: Mario Limonciello +Cc: Alex Deucher +Cc: stable@vger.kernel.org +Reviewed-by: Aurabindo Pillai +Acked-by: Alex Hung +Signed-off-by: Tianci Yin +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -9285,14 +9285,14 @@ static bool should_reset_plane(struct dr + struct drm_plane *other; + struct drm_plane_state *old_other_state, *new_other_state; + struct drm_crtc_state *new_crtc_state; ++ struct amdgpu_device *adev = drm_to_adev(plane->dev); + int i; + + /* +- * TODO: Remove this hack once the checks below are sufficient +- * enough to determine when we need to reset all the planes on +- * the stream. ++ * TODO: Remove this hack for all asics once it proves that the ++ * fast updates works fine on DCN3.2+. + */ +- if (state->allow_modeset) ++ if (adev->ip_versions[DCE_HWIP][0] < IP_VERSION(3, 2, 0) && state->allow_modeset) + return true; + + /* Exit early if we know that we're adding or removing the plane. */ diff --git a/queue-6.1/drm-amd-display-fix-a-null-pointer-dereference-in-amdgpu_dm_i2c_xfer.patch b/queue-6.1/drm-amd-display-fix-a-null-pointer-dereference-in-amdgpu_dm_i2c_xfer.patch new file mode 100644 index 00000000000..eee8221c7cd --- /dev/null +++ b/queue-6.1/drm-amd-display-fix-a-null-pointer-dereference-in-amdgpu_dm_i2c_xfer.patch @@ -0,0 +1,40 @@ +From b71f4ade1b8900d30c661d6c27f87c35214c398c Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Wed, 8 Nov 2023 13:31:57 -0600 +Subject: drm/amd/display: fix a NULL pointer dereference in amdgpu_dm_i2c_xfer() + +From: Mario Limonciello + +commit b71f4ade1b8900d30c661d6c27f87c35214c398c upstream. + +When ddc_service_construct() is called, it explicitly checks both the +link type and whether there is something on the link which will +dictate whether the pin is marked as hw_supported. + +If the pin isn't set or the link is not set (such as from +unloading/reloading amdgpu in an IGT test) then fail the +amdgpu_dm_i2c_xfer() call. + +Cc: stable@vger.kernel.org +Fixes: 22676bc500c2 ("drm/amd/display: Fix dmub soft hang for PSR 1") +Link: https://github.com/fwupd/fwupd/issues/6327 +Signed-off-by: Mario Limonciello +Reviewed-by: Harry Wentland +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -7219,6 +7219,9 @@ static int amdgpu_dm_i2c_xfer(struct i2c + int i; + int result = -EIO; + ++ if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported) ++ return result; ++ + cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); + + if (!cmd.payloads) diff --git a/queue-6.1/drm-amd-pm-fix-error-of-maco-flag-setting-code.patch b/queue-6.1/drm-amd-pm-fix-error-of-maco-flag-setting-code.patch new file mode 100644 index 00000000000..8b46d690818 --- /dev/null +++ b/queue-6.1/drm-amd-pm-fix-error-of-maco-flag-setting-code.patch @@ -0,0 +1,60 @@ +From 7f3e6b840fa8b0889d776639310a5dc672c1e9e1 Mon Sep 17 00:00:00 2001 +From: Ma Jun +Date: Tue, 31 Oct 2023 11:11:04 +0800 +Subject: drm/amd/pm: Fix error of MACO flag setting code + +From: Ma Jun + +commit 7f3e6b840fa8b0889d776639310a5dc672c1e9e1 upstream. + +MACO only works if BACO is supported + +Signed-off-by: Ma Jun +Reviewed-by: Kenneth Feng +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 8 ++++---- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 9 +++++---- + 2 files changed, 9 insertions(+), 8 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +@@ -324,12 +324,12 @@ static int smu_v13_0_0_check_powerplay_t + if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC) + smu->dc_controlled_by_gpio = true; + +- if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO || +- powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) ++ if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO) { + smu_baco->platform_support = true; + +- if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) +- smu_baco->maco_support = true; ++ if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) ++ smu_baco->maco_support = true; ++ } + + table_context->thermal_controller_type = + powerplay_table->thermal_controller_type; +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +@@ -326,12 +326,13 @@ static int smu_v13_0_7_check_powerplay_t + if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC) + smu->dc_controlled_by_gpio = true; + +- if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO || +- powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO) ++ if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO) { + smu_baco->platform_support = true; + +- if (smu_baco->platform_support && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled)) +- smu_baco->maco_support = true; ++ if ((powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO) ++ && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled)) ++ smu_baco->maco_support = true; ++ } + + table_context->thermal_controller_type = + powerplay_table->thermal_controller_type; diff --git a/queue-6.1/drm-amdgpu-don-t-use-atrm-for-external-devices.patch b/queue-6.1/drm-amdgpu-don-t-use-atrm-for-external-devices.patch new file mode 100644 index 00000000000..913ee8f0d71 --- /dev/null +++ b/queue-6.1/drm-amdgpu-don-t-use-atrm-for-external-devices.patch @@ -0,0 +1,48 @@ +From 432e664e7c98c243fab4c3c95bd463bea3aeed28 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Tue, 17 Oct 2023 15:40:01 -0400 +Subject: drm/amdgpu: don't use ATRM for external devices + +From: Alex Deucher + +commit 432e664e7c98c243fab4c3c95bd463bea3aeed28 upstream. + +The ATRM ACPI method is for fetching the dGPU vbios rom +image on laptops and all-in-one systems. It should not be +used for external add in cards. If the dGPU is thunderbolt +connected, don't try ATRM. + +v2: pci_is_thunderbolt_attached only works for Intel. Use + pdev->external_facing instead. +v3: dev_is_removable() seems to be what we want + +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2925 +Reviewed-by: Mario Limonciello +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +@@ -29,6 +29,7 @@ + #include "amdgpu.h" + #include "atom.h" + ++#include + #include + #include + #include +@@ -289,6 +290,10 @@ static bool amdgpu_atrm_get_bios(struct + if (adev->flags & AMD_IS_APU) + return false; + ++ /* ATRM is for on-platform devices only */ ++ if (dev_is_removable(&adev->pdev->dev)) ++ return false; ++ + while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { + dhandle = ACPI_HANDLE(&pdev->dev); + if (!dhandle) diff --git a/queue-6.1/drm-amdgpu-don-t-use-pci_is_thunderbolt_attached.patch b/queue-6.1/drm-amdgpu-don-t-use-pci_is_thunderbolt_attached.patch new file mode 100644 index 00000000000..91da3a6f166 --- /dev/null +++ b/queue-6.1/drm-amdgpu-don-t-use-pci_is_thunderbolt_attached.patch @@ -0,0 +1,96 @@ +From 7b1c6263eaf4fd64ffe1cafdc504a42ee4bfbb33 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Tue, 17 Oct 2023 16:30:00 -0400 +Subject: drm/amdgpu: don't use pci_is_thunderbolt_attached() + +From: Alex Deucher + +commit 7b1c6263eaf4fd64ffe1cafdc504a42ee4bfbb33 upstream. + +It's only valid on Intel systems with the Intel VSEC. +Use dev_is_removable() instead. This should do the right +thing regardless of the platform. + +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2925 +Reviewed-by: Mario Limonciello +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++++---- + drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 5 +++-- + 2 files changed, 7 insertions(+), 6 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -41,6 +41,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -2105,7 +2106,6 @@ out: + */ + static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) + { +- struct drm_device *dev = adev_to_drm(adev); + struct pci_dev *parent; + int i, r; + +@@ -2175,7 +2175,7 @@ static int amdgpu_device_ip_early_init(s + (amdgpu_is_atpx_hybrid() || + amdgpu_has_atpx_dgpu_power_cntl()) && + ((adev->flags & AMD_IS_APU) == 0) && +- !pci_is_thunderbolt_attached(to_pci_dev(dev->dev))) ++ !dev_is_removable(&adev->pdev->dev)) + adev->flags |= AMD_IS_PX; + + if (!(adev->flags & AMD_IS_APU)) { +@@ -3968,7 +3968,7 @@ fence_driver_init: + + px = amdgpu_device_supports_px(ddev); + +- if (px || (!pci_is_thunderbolt_attached(adev->pdev) && ++ if (px || (!dev_is_removable(&adev->pdev->dev) && + apple_gmux_detect(NULL, NULL))) + vga_switcheroo_register_client(adev->pdev, + &amdgpu_switcheroo_ops, px); +@@ -4117,7 +4117,7 @@ void amdgpu_device_fini_sw(struct amdgpu + + px = amdgpu_device_supports_px(adev_to_drm(adev)); + +- if (px || (!pci_is_thunderbolt_attached(adev->pdev) && ++ if (px || (!dev_is_removable(&adev->pdev->dev) && + apple_gmux_detect(NULL, NULL))) + vga_switcheroo_unregister_client(adev->pdev); + +--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c ++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +@@ -28,6 +28,7 @@ + #include "nbio/nbio_2_3_offset.h" + #include "nbio/nbio_2_3_sh_mask.h" + #include ++#include + #include + + #define smnPCIE_CONFIG_CNTL 0x11180044 +@@ -361,7 +362,7 @@ static void nbio_v2_3_enable_aspm(struct + + data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; + +- if (pci_is_thunderbolt_attached(adev->pdev)) ++ if (dev_is_removable(&adev->pdev->dev)) + data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; + else + data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; +@@ -480,7 +481,7 @@ static void nbio_v2_3_program_aspm(struc + + def = data = RREG32_PCIE(smnPCIE_LC_CNTL); + data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; +- if (pci_is_thunderbolt_attached(adev->pdev)) ++ if (dev_is_removable(&adev->pdev->dev)) + data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; + else + data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; diff --git a/queue-6.1/drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_get.patch b/queue-6.1/drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_get.patch new file mode 100644 index 00000000000..cdd4cac08f8 --- /dev/null +++ b/queue-6.1/drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_get.patch @@ -0,0 +1,35 @@ +From 12f76050d8d4d10dab96333656b821bd4620d103 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Thu, 9 Nov 2023 10:12:39 +0100 +Subject: drm/amdgpu: fix error handling in amdgpu_bo_list_get() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christian König + +commit 12f76050d8d4d10dab96333656b821bd4620d103 upstream. + +We should not leak the pointer where we couldn't grab the reference +on to the caller because it can be that the error handling still +tries to put the reference then. + +Signed-off-by: Christian König +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +@@ -179,6 +179,7 @@ int amdgpu_bo_list_get(struct amdgpu_fpr + } + + rcu_read_unlock(); ++ *result = NULL; + return -ENOENT; + } + diff --git a/queue-6.1/drm-amdgpu-lower-cs-errors-to-debug-severity.patch b/queue-6.1/drm-amdgpu-lower-cs-errors-to-debug-severity.patch new file mode 100644 index 00000000000..f9a8ab70e1b --- /dev/null +++ b/queue-6.1/drm-amdgpu-lower-cs-errors-to-debug-severity.patch @@ -0,0 +1,34 @@ +From 17daf01ab4e3e5a5929747aa05cc15eb2bad5438 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Thu, 9 Nov 2023 10:14:14 +0100 +Subject: drm/amdgpu: lower CS errors to debug severity +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christian König + +commit 17daf01ab4e3e5a5929747aa05cc15eb2bad5438 upstream. + +Otherwise userspace can spam the logs by using incorrect input values. + +Signed-off-by: Christian König +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +@@ -1391,7 +1391,7 @@ int amdgpu_cs_ioctl(struct drm_device *d + if (r == -ENOMEM) + DRM_ERROR("Not enough memory for command submission!\n"); + else if (r != -ERESTARTSYS && r != -EAGAIN) +- DRM_ERROR("Failed to process the buffer list %d!\n", r); ++ DRM_DEBUG("Failed to process the buffer list %d!\n", r); + goto error_fini; + } + diff --git a/queue-6.1/drm-amdgpu-smu13-drop-compute-workload-workaround.patch b/queue-6.1/drm-amdgpu-smu13-drop-compute-workload-workaround.patch new file mode 100644 index 00000000000..4eaad347a57 --- /dev/null +++ b/queue-6.1/drm-amdgpu-smu13-drop-compute-workload-workaround.patch @@ -0,0 +1,63 @@ +From 23170863ea0a0965d224342c0eb2ad8303b1f267 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Wed, 1 Nov 2023 15:48:14 -0400 +Subject: drm/amdgpu/smu13: drop compute workload workaround + +From: Alex Deucher + +commit 23170863ea0a0965d224342c0eb2ad8303b1f267 upstream. + +This was fixed in PMFW before launch and is no longer +required. + +Reviewed-by: Yang Wang +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 32 +------------------ + 1 file changed, 2 insertions(+), 30 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +@@ -1645,38 +1645,10 @@ static int smu_v13_0_0_set_power_profile + } + } + +- if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE && +- (((smu->adev->pdev->device == 0x744C) && (smu->adev->pdev->revision == 0xC8)) || +- ((smu->adev->pdev->device == 0x744C) && (smu->adev->pdev->revision == 0xCC)))) { +- ret = smu_cmn_update_table(smu, +- SMU_TABLE_ACTIVITY_MONITOR_COEFF, +- WORKLOAD_PPLIB_COMPUTE_BIT, +- (void *)(&activity_monitor_external), +- false); +- if (ret) { +- dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); +- return ret; +- } +- +- ret = smu_cmn_update_table(smu, +- SMU_TABLE_ACTIVITY_MONITOR_COEFF, +- WORKLOAD_PPLIB_CUSTOM_BIT, +- (void *)(&activity_monitor_external), +- true); +- if (ret) { +- dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); +- return ret; +- } +- +- workload_type = smu_cmn_to_asic_specific_index(smu, +- CMN2ASIC_MAPPING_WORKLOAD, +- PP_SMC_POWER_PROFILE_CUSTOM); +- } else { +- /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ +- workload_type = smu_cmn_to_asic_specific_index(smu, ++ /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ ++ workload_type = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_WORKLOAD, + smu->power_profile_mode); +- } + + if (workload_type < 0) + return -EINVAL; diff --git a/queue-6.1/drm-i915-bump-glk-cdclk-frequency-when-driving-multiple-pipes.patch b/queue-6.1/drm-i915-bump-glk-cdclk-frequency-when-driving-multiple-pipes.patch new file mode 100644 index 00000000000..f3e60afecc7 --- /dev/null +++ b/queue-6.1/drm-i915-bump-glk-cdclk-frequency-when-driving-multiple-pipes.patch @@ -0,0 +1,62 @@ +From 0cb89cd42fd22bbdec0b046c48f35775f5b88bdb Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Tue, 31 Oct 2023 18:08:00 +0200 +Subject: drm/i915: Bump GLK CDCLK frequency when driving multiple pipes +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 0cb89cd42fd22bbdec0b046c48f35775f5b88bdb upstream. + +On GLK CDCLK frequency needs to be at least 2*96 MHz when accessing +the audio hardware. Currently we bump the CDCLK frequency up +temporarily (if not high enough already) whenever audio hardware +is being accessed, and drop it back down afterwards. + +With a single active pipe this works just fine as we can switch +between all the valid CDCLK frequencies by changing the cd2x +divider, which doesn't require a full modeset. However with +multiple active pipes the cd2x divider trick no longer works, +and thus we end up blinking all displays off and back on. + +To avoid this let's just bump the CDCLK frequency to >=2*96MHz +whenever multiple pipes are active. The downside is slightly +higher power consumption, but that seems like an acceptable +tradeoff. With a single active pipe we can stick to the current +more optiomal (from power comsumption POV) behaviour. + +Cc: stable@vger.kernel.org +Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9599 +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20231031160800.18371-1-ville.syrjala@linux.intel.com +Reviewed-by: Jani Nikula +(cherry picked from commit 451eaa1a614c911f5a51078dcb68022874e4cb12) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/gpu/drm/i915/display/intel_cdclk.c ++++ b/drivers/gpu/drm/i915/display/intel_cdclk.c +@@ -2368,6 +2368,18 @@ static int intel_compute_min_cdclk(struc + for_each_pipe(dev_priv, pipe) + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); + ++ /* ++ * Avoid glk_force_audio_cdclk() causing excessive screen ++ * blinking when multiple pipes are active by making sure ++ * CDCLK frequency is always high enough for audio. With a ++ * single active pipe we can always change CDCLK frequency ++ * by changing the cd2x divider (see glk_cdclk_table[]) and ++ * thus a full modeset won't be needed then. ++ */ ++ if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes && ++ !is_power_of_2(cdclk_state->active_pipes)) ++ min_cdclk = max(2 * 96000, min_cdclk); ++ + if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { + drm_dbg_kms(&dev_priv->drm, + "required cdclk (%d kHz) exceeds max (%d kHz)\n", diff --git a/queue-6.1/drm-i915-fix-potential-spectre-vulnerability.patch b/queue-6.1/drm-i915-fix-potential-spectre-vulnerability.patch new file mode 100644 index 00000000000..1879f8633f8 --- /dev/null +++ b/queue-6.1/drm-i915-fix-potential-spectre-vulnerability.patch @@ -0,0 +1,36 @@ +From 1a8e9bad6ef563c28ab0f8619628d5511be55431 Mon Sep 17 00:00:00 2001 +From: Kunwu Chan +Date: Fri, 3 Nov 2023 11:09:22 +0000 +Subject: drm/i915: Fix potential spectre vulnerability + +From: Kunwu Chan + +commit 1a8e9bad6ef563c28ab0f8619628d5511be55431 upstream. + +Fix smatch warning: +drivers/gpu/drm/i915/gem/i915_gem_context.c:847 set_proto_ctx_sseu() +warn: potential spectre issue 'pc->user_engines' [r] (local cap) + +Fixes: d4433c7600f7 ("drm/i915/gem: Use the proto-context to handle create parameters (v5)") +Cc: # v5.15+ +Signed-off-by: Kunwu Chan +Reviewed-by: Tvrtko Ursulin +Signed-off-by: Tvrtko Ursulin +Link: https://patchwork.freedesktop.org/patch/msgid/20231103110922.430122-1-tvrtko.ursulin@linux.intel.com +(cherry picked from commit 27b086382c22efb7e0a16442f7bdc2e120108ef3) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c ++++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c +@@ -844,6 +844,7 @@ static int set_proto_ctx_sseu(struct drm + if (idx >= pc->num_user_engines) + return -EINVAL; + ++ idx = array_index_nospec(idx, pc->num_user_engines); + pe = &pc->user_engines[idx]; + + /* Only render engine supports RPCS configuration. */ diff --git a/queue-6.1/series b/queue-6.1/series index d19866ea512..20be0ca28d6 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -355,3 +355,14 @@ ext4-remove-gdb-backup-copy-for-meta-bg-in-setup_new_flex_group_blocks.patch ext4-add-missed-brelse-in-update_backups.patch ext4-properly-sync-file-size-update-after-o_sync-direct-io.patch drm-amd-pm-handle-non-terminated-overdrive-commands.patch +drm-i915-bump-glk-cdclk-frequency-when-driving-multiple-pipes.patch +drm-i915-fix-potential-spectre-vulnerability.patch +drm-amd-pm-fix-error-of-maco-flag-setting-code.patch +drm-amdgpu-smu13-drop-compute-workload-workaround.patch +drm-amdgpu-don-t-use-pci_is_thunderbolt_attached.patch +drm-amdgpu-don-t-use-atrm-for-external-devices.patch +drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_get.patch +drm-amdgpu-lower-cs-errors-to-debug-severity.patch +drm-amd-display-fix-a-null-pointer-dereference-in-amdgpu_dm_i2c_xfer.patch +drm-amd-display-enable-fast-plane-updates-on-dcn3.2-and-above.patch +drm-amd-display-change-the-dmcub-mailbox-memory-location-from-fb-to-inbox.patch