From: VMware, Inc <> Date: Thu, 2 Aug 2012 06:49:18 +0000 (-0700) Subject: Internal branch sync. Included in this change: X-Git-Tag: 2012.10.14-874563~68 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=1b622431be6344bd8d1a8b49208339cfa0cb032d;p=thirdparty%2Fopen-vm-tools.git Internal branch sync. Included in this change: . turn VGauth support back on now that all name changes are pushed through . lib/misc - add StrUtil_CapacityToBytes() . changes in shared code that don't affect open-vm-tools functionality Signed-off-by: Dmitry Torokhov --- diff --git a/open-vm-tools/lib/include/strutil.h b/open-vm-tools/lib/include/strutil.h index 5003f4596..7fed680a2 100644 --- a/open-vm-tools/lib/include/strutil.h +++ b/open-vm-tools/lib/include/strutil.h @@ -46,6 +46,8 @@ Bool StrUtil_StrToInt64(int64 *out, const char *str); Bool StrUtil_StrToUint64(uint64 *out, const char *str); Bool StrUtil_StrToSizet(size_t *out, const char *str); Bool StrUtil_StrToDouble(double *out, const char *str); +Bool StrUtil_CapacityToBytes(SectorType *out, const char *str, + unsigned int bytes); Bool StrUtil_CapacityToSectorType(SectorType *out, const char *str, unsigned int bytes); char *StrUtil_FormatSizeInBytesUnlocalized(uint64 size); diff --git a/open-vm-tools/lib/include/vm_api.h b/open-vm-tools/lib/include/vm_api.h index fdfea286c..41c4553a8 100644 --- a/open-vm-tools/lib/include/vm_api.h +++ b/open-vm-tools/lib/include/vm_api.h @@ -74,12 +74,15 @@ #ifdef _MSC_VER # define VMW_IMPORT __declspec(dllimport) # define VMW_EXPORT __declspec(dllexport) +# define VMW_STATIC #elif defined __GNUC__ && __GNUC__ >= 4 /* !_MSC_VER */ -# define VMW_IMPORT +# define VMW_IMPORT __attribute__ ((visibility ("default"))) # define VMW_EXPORT __attribute__ ((visibility ("default"))) +# define VMW_STATIC __attribute__ ((visibility ("hidden"))) #else # define VMW_IMPORT # define VMW_EXPORT +# define VMW_STATIC #endif /* _MSC_VER */ diff --git a/open-vm-tools/lib/include/x86cpuid.h b/open-vm-tools/lib/include/x86cpuid.h index a4e804729..7dea75fe7 100644 --- a/open-vm-tools/lib/include/x86cpuid.h +++ b/open-vm-tools/lib/include/x86cpuid.h @@ -276,407 +276,406 @@ typedef enum { CPUID_NUM_FIELD_SUPPORTEDS } CpuidFieldSupported; -/* LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */ -#define CPUID_FIELD_DATA_LEVEL_0 \ -FIELD( 0, 0, EAX, COMMON, 0, 32, NUMLEVELS, ANY, FALSE) \ -FIELD( 0, 0, EBX, COMMON, 0, 32, VENDOR1, YES, TRUE) \ -FIELD( 0, 0, ECX, COMMON, 0, 32, VENDOR3, YES, TRUE) \ -FIELD( 0, 0, EDX, COMMON, 0, 32, VENDOR2, YES, TRUE) +/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, CPL3 */ +#define CPUID_FIELD_DATA_LEVEL_0 \ +FIELD( 0, 0, EAX, 0, 32, NUMLEVELS, ANY, FALSE) \ +FIELD( 0, 0, EBX, 0, 32, VENDOR1, YES, TRUE) \ +FIELD( 0, 0, ECX, 0, 32, VENDOR3, YES, TRUE) \ +FIELD( 0, 0, EDX, 0, 32, VENDOR2, YES, TRUE) -/* LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */ -#define CPUID_FIELD_DATA_LEVEL_1 \ -FIELD( 1, 0, EAX, COMMON, 0, 4, STEPPING, ANY, FALSE) \ -FIELD( 1, 0, EAX, COMMON, 4, 4, MODEL, ANY, FALSE) \ -FIELD( 1, 0, EAX, COMMON, 8, 4, FAMILY, YES, FALSE) \ -FIELD( 1, 0, EAX, COMMON, 12, 2, TYPE, ANY, FALSE) \ -FIELD( 1, 0, EAX, COMMON, 16, 4, EXTENDED_MODEL, ANY, FALSE) \ -FIELD( 1, 0, EAX, COMMON, 20, 8, EXTENDED_FAMILY, YES, FALSE) \ -FIELD( 1, 0, EBX, COMMON, 0, 8, BRAND_ID, ANY, FALSE) \ -FIELD( 1, 0, EBX, COMMON, 8, 8, CLFL_SIZE, ANY, FALSE) \ -FIELD( 1, 0, EBX, COMMON, 16, 8, LCPU_COUNT, ANY, FALSE) \ -FIELD( 1, 0, EBX, COMMON, 24, 8, APICID, ANY, FALSE) \ -FLAG( 1, 0, ECX, COMMON, 0, 1, SSE3, YES, TRUE) \ -FLAG( 1, 0, ECX, COMMON, 1, 1, PCLMULQDQ, YES, TRUE) \ -FLAG( 1, 0, ECX, INTEL, 2, 1, DTES64, NO, FALSE) \ -FLAG( 1, 0, ECX, COMMON, 3, 1, MWAIT, YES, FALSE) \ -FLAG( 1, 0, ECX, INTEL, 4, 1, DSCPL, NO, FALSE) \ -FLAG( 1, 0, ECX, INTEL, 5, 1, VMX, YES, FALSE) \ -FLAG( 1, 0, ECX, INTEL, 6, 1, SMX, NO, FALSE) \ -FLAG( 1, 0, ECX, INTEL, 7, 1, EIST, NO, FALSE) \ -FLAG( 1, 0, ECX, INTEL, 8, 1, TM2, NO, FALSE) \ -FLAG( 1, 0, ECX, COMMON, 9, 1, SSSE3, YES, TRUE) \ -FLAG( 1, 0, ECX, INTEL, 10, 1, CNXTID, NO, FALSE) \ -FLAG( 1, 0, ECX, INTEL, 11, 1, NDA11, NO, FALSE) \ -FLAG( 1, 0, ECX, COMMON, 12, 1, FMA, YES, TRUE) \ -FLAG( 1, 0, ECX, COMMON, 13, 1, CMPXCHG16B, YES, TRUE) \ -FLAG( 1, 0, ECX, INTEL, 14, 1, xTPR, NO, FALSE) \ -FLAG( 1, 0, ECX, INTEL, 15, 1, PDCM, NO, FALSE) \ -FLAG( 1, 0, ECX, INTEL, 17, 1, PCID, YES, FALSE) \ -FLAG( 1, 0, ECX, INTEL, 18, 1, DCA, NO, FALSE) \ -FLAG( 1, 0, ECX, COMMON, 19, 1, SSE41, YES, TRUE) \ -FLAG( 1, 0, ECX, COMMON, 20, 1, SSE42, YES, TRUE) \ -FLAG( 1, 0, ECX, COMMON, 21, 1, x2APIC, ANY, FALSE) \ -FLAG( 1, 0, ECX, INTEL, 22, 1, MOVBE, YES, TRUE) \ -FLAG( 1, 0, ECX, COMMON, 23, 1, POPCNT, YES, TRUE) \ -FLAG( 1, 0, ECX, COMMON, 24, 1, TSC_DEADLINE, NO, FALSE) \ -FLAG( 1, 0, ECX, COMMON, 25, 1, AES, YES, TRUE) \ -FLAG( 1, 0, ECX, COMMON, 26, 1, XSAVE, YES, FALSE) \ -FLAG( 1, 0, ECX, COMMON, 27, 1, OSXSAVE, ANY, FALSE) \ -FLAG( 1, 0, ECX, COMMON, 28, 1, AVX, YES, FALSE) \ -FLAG( 1, 0, ECX, COMMON, 29, 1, F16C, YES, TRUE) \ -FLAG( 1, 0, ECX, COMMON, 30, 1, RDRAND, YES, TRUE) \ -FLAG( 1, 0, ECX, COMMON, 31, 1, HYPERVISOR, ANY, TRUE) \ -FLAG( 1, 0, EDX, COMMON, 0, 1, FPU, YES, TRUE) \ -FLAG( 1, 0, EDX, COMMON, 1, 1, VME, YES, FALSE) \ -FLAG( 1, 0, EDX, COMMON, 2, 1, DE, YES, FALSE) \ -FLAG( 1, 0, EDX, COMMON, 3, 1, PSE, YES, FALSE) \ -FLAG( 1, 0, EDX, COMMON, 4, 1, TSC, YES, TRUE) \ -FLAG( 1, 0, EDX, COMMON, 5, 1, MSR, YES, FALSE) \ -FLAG( 1, 0, EDX, COMMON, 6, 1, PAE, YES, FALSE) \ -FLAG( 1, 0, EDX, COMMON, 7, 1, MCE, YES, FALSE) \ -FLAG( 1, 0, EDX, COMMON, 8, 1, CX8, YES, TRUE) \ -FLAG( 1, 0, EDX, COMMON, 9, 1, APIC, ANY, FALSE) \ -FLAG( 1, 0, EDX, COMMON, 11, 1, SEP, YES, TRUE) \ -FLAG( 1, 0, EDX, COMMON, 12, 1, MTRR, YES, FALSE) \ -FLAG( 1, 0, EDX, COMMON, 13, 1, PGE, YES, FALSE) \ -FLAG( 1, 0, EDX, COMMON, 14, 1, MCA, YES, FALSE) \ -FLAG( 1, 0, EDX, COMMON, 15, 1, CMOV, YES, TRUE) \ -FLAG( 1, 0, EDX, COMMON, 16, 1, PAT, YES, FALSE) \ -FLAG( 1, 0, EDX, COMMON, 17, 1, PSE36, YES, FALSE) \ -FLAG( 1, 0, EDX, INTEL, 18, 1, PSN, YES, FALSE) \ -FLAG( 1, 0, EDX, COMMON, 19, 1, CLFSH, YES, TRUE) \ -FLAG( 1, 0, EDX, INTEL, 21, 1, DS, YES, FALSE) \ -FLAG( 1, 0, EDX, INTEL, 22, 1, ACPI, ANY, FALSE) \ -FLAG( 1, 0, EDX, COMMON, 23, 1, MMX, YES, TRUE) \ -FLAG( 1, 0, EDX, COMMON, 24, 1, FXSR, YES, TRUE) \ -FLAG( 1, 0, EDX, COMMON, 25, 1, SSE, YES, TRUE) \ -FLAG( 1, 0, EDX, COMMON, 26, 1, SSE2, YES, TRUE) \ -FLAG( 1, 0, EDX, INTEL, 27, 1, SS, YES, FALSE) \ -FLAG( 1, 0, EDX, COMMON, 28, 1, HTT, ANY, FALSE) \ -FLAG( 1, 0, EDX, INTEL, 29, 1, TM, NO, FALSE) \ -FLAG( 1, 0, EDX, INTEL, 30, 1, IA64, NO, FALSE) \ -FLAG( 1, 0, EDX, INTEL, 31, 1, PBE, NO, FALSE) - -/* LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */ -#define CPUID_FIELD_DATA_LEVEL_4 \ -FIELD( 4, 0, EAX, INTEL, 0, 5, LEAF4_CACHE_TYPE, NA, FALSE) \ -FIELD( 4, 0, EAX, INTEL, 5, 3, LEAF4_CACHE_LEVEL, NA, FALSE) \ -FLAG( 4, 0, EAX, INTEL, 8, 1, LEAF4_CACHE_SELF_INIT, NA, FALSE) \ -FLAG( 4, 0, EAX, INTEL, 9, 1, LEAF4_CACHE_FULLY_ASSOC, NA, FALSE) \ -FIELD( 4, 0, EAX, INTEL, 14, 12, LEAF4_CACHE_NUMHT_SHARING, NA, FALSE) \ -FIELD( 4, 0, EAX, INTEL, 26, 6, LEAF4_CORE_COUNT, NA, FALSE) \ -FIELD( 4, 0, EBX, INTEL, 0, 12, LEAF4_CACHE_LINE, NA, FALSE) \ -FIELD( 4, 0, EBX, INTEL, 12, 10, LEAF4_CACHE_PART, NA, FALSE) \ -FIELD( 4, 0, EBX, INTEL, 22, 10, LEAF4_CACHE_WAYS, NA, FALSE) \ -FIELD( 4, 0, ECX, INTEL, 0, 32, LEAF4_CACHE_SETS, NA, FALSE) \ -FLAG( 4, 0, EDX, INTEL, 0, 1, LEAF4_CACHE_WBINVD_NOT_GUARANTEED, NA, FALSE) \ -FLAG( 4, 0, EDX, INTEL, 1, 1, LEAF4_CACHE_IS_INCLUSIVE, NA, FALSE) \ -FLAG( 4, 0, EDX, INTEL, 2, 1, LEAF4_CACHE_COMPLEX_INDEXING, NA, FALSE) - -/* LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */ -#define CPUID_FIELD_DATA_LEVEL_5 \ -FIELD( 5, 0, EAX, COMMON, 0, 16, MWAIT_MIN_SIZE, NA, FALSE) \ -FIELD( 5, 0, EBX, COMMON, 0, 16, MWAIT_MAX_SIZE, NA, FALSE) \ -FLAG( 5, 0, ECX, COMMON, 0, 1, MWAIT_EXTENSIONS, NA, FALSE) \ -FLAG( 5, 0, ECX, COMMON, 1, 1, MWAIT_INTR_BREAK, NA, FALSE) \ -FIELD( 5, 0, EDX, INTEL, 0, 4, MWAIT_C0_SUBSTATE, NA, FALSE) \ -FIELD( 5, 0, EDX, INTEL, 4, 4, MWAIT_C1_SUBSTATE, NA, FALSE) \ -FIELD( 5, 0, EDX, INTEL, 8, 4, MWAIT_C2_SUBSTATE, NA, FALSE) \ -FIELD( 5, 0, EDX, INTEL, 12, 4, MWAIT_C3_SUBSTATE, NA, FALSE) \ -FIELD( 5, 0, EDX, INTEL, 16, 4, MWAIT_C4_SUBSTATE, NA, FALSE) - -/* LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */ -#define CPUID_FIELD_DATA_LEVEL_6 \ -FLAG( 6, 0, EAX, INTEL, 0, 1, THERMAL_SENSOR, NA, FALSE) \ -FLAG( 6, 0, EAX, INTEL, 1, 1, TURBO_MODE, NA, FALSE) \ -FLAG( 6, 0, EAX, INTEL, 2, 1, APIC_INVARIANT, NA, FALSE) \ -FIELD( 6, 0, EBX, INTEL, 0, 4, NUM_INTR_THRESHOLDS, NA, FALSE) \ -FLAG( 6, 0, ECX, INTEL, 0, 1, HW_COORD_FEEDBACK, NA, FALSE) \ -FLAG( 6, 0, ECX, INTEL, 3, 1, ENERGY_PERF_BIAS, NA, FALSE) +/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, CPL3 */ +#define CPUID_FIELD_DATA_LEVEL_1 \ +FIELD( 1, 0, EAX, 0, 4, STEPPING, ANY, FALSE) \ +FIELD( 1, 0, EAX, 4, 4, MODEL, ANY, FALSE) \ +FIELD( 1, 0, EAX, 8, 4, FAMILY, YES, FALSE) \ +FIELD( 1, 0, EAX, 12, 2, TYPE, ANY, FALSE) \ +FIELD( 1, 0, EAX, 16, 4, EXTENDED_MODEL, ANY, FALSE) \ +FIELD( 1, 0, EAX, 20, 8, EXTENDED_FAMILY, YES, FALSE) \ +FIELD( 1, 0, EBX, 0, 8, BRAND_ID, ANY, FALSE) \ +FIELD( 1, 0, EBX, 8, 8, CLFL_SIZE, ANY, FALSE) \ +FIELD( 1, 0, EBX, 16, 8, LCPU_COUNT, ANY, FALSE) \ +FIELD( 1, 0, EBX, 24, 8, APICID, ANY, FALSE) \ +FLAG( 1, 0, ECX, 0, 1, SSE3, YES, TRUE) \ +FLAG( 1, 0, ECX, 1, 1, PCLMULQDQ, YES, TRUE) \ +FLAG( 1, 0, ECX, 2, 1, DTES64, NO, FALSE) \ +FLAG( 1, 0, ECX, 3, 1, MWAIT, YES, FALSE) \ +FLAG( 1, 0, ECX, 4, 1, DSCPL, NO, FALSE) \ +FLAG( 1, 0, ECX, 5, 1, VMX, YES, FALSE) \ +FLAG( 1, 0, ECX, 6, 1, SMX, NO, FALSE) \ +FLAG( 1, 0, ECX, 7, 1, EIST, NO, FALSE) \ +FLAG( 1, 0, ECX, 8, 1, TM2, NO, FALSE) \ +FLAG( 1, 0, ECX, 9, 1, SSSE3, YES, TRUE) \ +FLAG( 1, 0, ECX, 10, 1, CNXTID, NO, FALSE) \ +FLAG( 1, 0, ECX, 11, 1, NDA11, NO, FALSE) \ +FLAG( 1, 0, ECX, 12, 1, FMA, YES, TRUE) \ +FLAG( 1, 0, ECX, 13, 1, CMPXCHG16B, YES, TRUE) \ +FLAG( 1, 0, ECX, 14, 1, xTPR, NO, FALSE) \ +FLAG( 1, 0, ECX, 15, 1, PDCM, NO, FALSE) \ +FLAG( 1, 0, ECX, 17, 1, PCID, YES, FALSE) \ +FLAG( 1, 0, ECX, 18, 1, DCA, NO, FALSE) \ +FLAG( 1, 0, ECX, 19, 1, SSE41, YES, TRUE) \ +FLAG( 1, 0, ECX, 20, 1, SSE42, YES, TRUE) \ +FLAG( 1, 0, ECX, 21, 1, x2APIC, ANY, FALSE) \ +FLAG( 1, 0, ECX, 22, 1, MOVBE, YES, TRUE) \ +FLAG( 1, 0, ECX, 23, 1, POPCNT, YES, TRUE) \ +FLAG( 1, 0, ECX, 24, 1, TSC_DEADLINE, NO, FALSE) \ +FLAG( 1, 0, ECX, 25, 1, AES, YES, TRUE) \ +FLAG( 1, 0, ECX, 26, 1, XSAVE, YES, FALSE) \ +FLAG( 1, 0, ECX, 27, 1, OSXSAVE, ANY, FALSE) \ +FLAG( 1, 0, ECX, 28, 1, AVX, YES, FALSE) \ +FLAG( 1, 0, ECX, 29, 1, F16C, YES, TRUE) \ +FLAG( 1, 0, ECX, 30, 1, RDRAND, YES, TRUE) \ +FLAG( 1, 0, ECX, 31, 1, HYPERVISOR, ANY, TRUE) \ +FLAG( 1, 0, EDX, 0, 1, FPU, YES, TRUE) \ +FLAG( 1, 0, EDX, 1, 1, VME, YES, FALSE) \ +FLAG( 1, 0, EDX, 2, 1, DE, YES, FALSE) \ +FLAG( 1, 0, EDX, 3, 1, PSE, YES, FALSE) \ +FLAG( 1, 0, EDX, 4, 1, TSC, YES, TRUE) \ +FLAG( 1, 0, EDX, 5, 1, MSR, YES, FALSE) \ +FLAG( 1, 0, EDX, 6, 1, PAE, YES, FALSE) \ +FLAG( 1, 0, EDX, 7, 1, MCE, YES, FALSE) \ +FLAG( 1, 0, EDX, 8, 1, CX8, YES, TRUE) \ +FLAG( 1, 0, EDX, 9, 1, APIC, ANY, FALSE) \ +FLAG( 1, 0, EDX, 11, 1, SEP, YES, TRUE) \ +FLAG( 1, 0, EDX, 12, 1, MTRR, YES, FALSE) \ +FLAG( 1, 0, EDX, 13, 1, PGE, YES, FALSE) \ +FLAG( 1, 0, EDX, 14, 1, MCA, YES, FALSE) \ +FLAG( 1, 0, EDX, 15, 1, CMOV, YES, TRUE) \ +FLAG( 1, 0, EDX, 16, 1, PAT, YES, FALSE) \ +FLAG( 1, 0, EDX, 17, 1, PSE36, YES, FALSE) \ +FLAG( 1, 0, EDX, 18, 1, PSN, YES, FALSE) \ +FLAG( 1, 0, EDX, 19, 1, CLFSH, YES, TRUE) \ +FLAG( 1, 0, EDX, 21, 1, DS, YES, FALSE) \ +FLAG( 1, 0, EDX, 22, 1, ACPI, ANY, FALSE) \ +FLAG( 1, 0, EDX, 23, 1, MMX, YES, TRUE) \ +FLAG( 1, 0, EDX, 24, 1, FXSR, YES, TRUE) \ +FLAG( 1, 0, EDX, 25, 1, SSE, YES, TRUE) \ +FLAG( 1, 0, EDX, 26, 1, SSE2, YES, TRUE) \ +FLAG( 1, 0, EDX, 27, 1, SS, YES, FALSE) \ +FLAG( 1, 0, EDX, 28, 1, HTT, ANY, FALSE) \ +FLAG( 1, 0, EDX, 29, 1, TM, NO, FALSE) \ +FLAG( 1, 0, EDX, 30, 1, IA64, NO, FALSE) \ +FLAG( 1, 0, EDX, 31, 1, PBE, NO, FALSE) + +/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, CPL3 */ +#define CPUID_FIELD_DATA_LEVEL_4 \ +FIELD( 4, 0, EAX, 0, 5, LEAF4_CACHE_TYPE, NA, FALSE) \ +FIELD( 4, 0, EAX, 5, 3, LEAF4_CACHE_LEVEL, NA, FALSE) \ +FLAG( 4, 0, EAX, 8, 1, LEAF4_CACHE_SELF_INIT, NA, FALSE) \ +FLAG( 4, 0, EAX, 9, 1, LEAF4_CACHE_FULLY_ASSOC, NA, FALSE) \ +FIELD( 4, 0, EAX, 14, 12, LEAF4_CACHE_NUMHT_SHARING, NA, FALSE) \ +FIELD( 4, 0, EAX, 26, 6, LEAF4_CORE_COUNT, NA, FALSE) \ +FIELD( 4, 0, EBX, 0, 12, LEAF4_CACHE_LINE, NA, FALSE) \ +FIELD( 4, 0, EBX, 12, 10, LEAF4_CACHE_PART, NA, FALSE) \ +FIELD( 4, 0, EBX, 22, 10, LEAF4_CACHE_WAYS, NA, FALSE) \ +FIELD( 4, 0, ECX, 0, 32, LEAF4_CACHE_SETS, NA, FALSE) \ +FLAG( 4, 0, EDX, 0, 1, LEAF4_CACHE_WBINVD_NOT_GUARANTEED, NA, FALSE) \ +FLAG( 4, 0, EDX, 1, 1, LEAF4_CACHE_IS_INCLUSIVE, NA, FALSE) \ +FLAG( 4, 0, EDX, 2, 1, LEAF4_CACHE_COMPLEX_INDEXING, NA, FALSE) + +/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, CPL3 */ +#define CPUID_FIELD_DATA_LEVEL_5 \ +FIELD( 5, 0, EAX, 0, 16, MWAIT_MIN_SIZE, NA, FALSE) \ +FIELD( 5, 0, EBX, 0, 16, MWAIT_MAX_SIZE, NA, FALSE) \ +FLAG( 5, 0, ECX, 0, 1, MWAIT_EXTENSIONS, NA, FALSE) \ +FLAG( 5, 0, ECX, 1, 1, MWAIT_INTR_BREAK, NA, FALSE) \ +FIELD( 5, 0, EDX, 0, 4, MWAIT_C0_SUBSTATE, NA, FALSE) \ +FIELD( 5, 0, EDX, 4, 4, MWAIT_C1_SUBSTATE, NA, FALSE) \ +FIELD( 5, 0, EDX, 8, 4, MWAIT_C2_SUBSTATE, NA, FALSE) \ +FIELD( 5, 0, EDX, 12, 4, MWAIT_C3_SUBSTATE, NA, FALSE) \ +FIELD( 5, 0, EDX, 16, 4, MWAIT_C4_SUBSTATE, NA, FALSE) + +/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, CPL3 */ +#define CPUID_FIELD_DATA_LEVEL_6 \ +FLAG( 6, 0, EAX, 0, 1, THERMAL_SENSOR, NA, FALSE) \ +FLAG( 6, 0, EAX, 1, 1, TURBO_MODE, NA, FALSE) \ +FLAG( 6, 0, EAX, 2, 1, APIC_INVARIANT, NA, FALSE) \ +FIELD( 6, 0, EBX, 0, 4, NUM_INTR_THRESHOLDS, NA, FALSE) \ +FLAG( 6, 0, ECX, 0, 1, HW_COORD_FEEDBACK, NA, FALSE) \ +FLAG( 6, 0, ECX, 3, 1, ENERGY_PERF_BIAS, NA, FALSE) #define CPUID_7_EBX_13 -/* LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */ -#define CPUID_FIELD_DATA_LEVEL_7 \ -FLAG( 7, 0, EBX, INTEL, 0, 1, FSGSBASE, YES, FALSE) \ -FLAG( 7, 0, EBX, COMMON, 3, 1, BMI1, YES, TRUE ) \ -FLAG( 7, 0, EBX, INTEL, 4, 1, HLE, YES, TRUE) \ -FLAG( 7, 0, EBX, INTEL, 5, 1, AVX2, YES, TRUE) \ -FLAG( 7, 0, EBX, INTEL, 7, 1, SMEP, YES, FALSE) \ -FLAG( 7, 0, EBX, INTEL, 8, 1, BMI2, YES, TRUE) \ -FLAG( 7, 0, EBX, INTEL, 9, 1, ENFSTRG, YES, FALSE) \ -FLAG( 7, 0, EBX, INTEL, 10, 1, INVPCID, NO, FALSE) \ -FLAG( 7, 0, EBX, INTEL, 11, 1, RTM, NO, TRUE) \ +/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, CPL3 */ +#define CPUID_FIELD_DATA_LEVEL_7 \ +FLAG( 7, 0, EBX, 0, 1, FSGSBASE, YES, FALSE) \ +FLAG( 7, 0, EBX, 3, 1, BMI1, YES, TRUE) \ +FLAG( 7, 0, EBX, 4, 1, HLE, YES, TRUE) \ +FLAG( 7, 0, EBX, 5, 1, AVX2, YES, TRUE) \ +FLAG( 7, 0, EBX, 7, 1, SMEP, YES, FALSE) \ +FLAG( 7, 0, EBX, 8, 1, BMI2, YES, TRUE) \ +FLAG( 7, 0, EBX, 9, 1, ENFSTRG, YES, FALSE) \ +FLAG( 7, 0, EBX, 10, 1, INVPCID, NO, FALSE) \ +FLAG( 7, 0, EBX, 11, 1, RTM, NO, TRUE) \ CPUID_7_EBX_13 -/* LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */ -#define CPUID_FIELD_DATA_LEVEL_A \ -FIELD( A, 0, EAX, INTEL, 0, 8, PMC_VERSION, NA, FALSE) \ -FIELD( A, 0, EAX, INTEL, 8, 8, PMC_NUM_GEN, NA, FALSE) \ -FIELD( A, 0, EAX, INTEL, 16, 8, PMC_WIDTH_GEN, NA, FALSE) \ -FIELD( A, 0, EAX, INTEL, 24, 8, PMC_EBX_LENGTH, NA, FALSE) \ -FLAG( A, 0, EBX, INTEL, 0, 1, PMC_CORE_CYCLES, NA, FALSE) \ -FLAG( A, 0, EBX, INTEL, 1, 1, PMC_INSTR_RETIRED, NA, FALSE) \ -FLAG( A, 0, EBX, INTEL, 2, 1, PMC_REF_CYCLES, NA, FALSE) \ -FLAG( A, 0, EBX, INTEL, 3, 1, PMC_LAST_LVL_CREF, NA, FALSE) \ -FLAG( A, 0, EBX, INTEL, 4, 1, PMC_LAST_LVL_CMISS, NA, FALSE) \ -FLAG( A, 0, EBX, INTEL, 5, 1, PMC_BR_INST_RETIRED, NA, FALSE) \ -FLAG( A, 0, EBX, INTEL, 6, 1, PMC_BR_MISS_RETIRED, NA, FALSE) \ -FIELD( A, 0, EDX, INTEL, 0, 5, PMC_NUM_FIXED, NA, FALSE) \ -FIELD( A, 0, EDX, INTEL, 5, 8, PMC_WIDTH_FIXED, NA, FALSE) - -/* LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */ -#define CPUID_FIELD_DATA_LEVEL_B \ -FIELD( B, 0, EAX, INTEL, 0, 5, TOPOLOGY_MASK_WIDTH, NA, FALSE) \ -FIELD( B, 0, EBX, INTEL, 0, 16, TOPOLOGY_CPUS_SHARING_LEVEL, NA, FALSE) \ -FIELD( B, 0, ECX, INTEL, 0, 8, TOPOLOGY_LEVEL_NUMBER, NA, FALSE) \ -FIELD( B, 0, ECX, INTEL, 8, 8, TOPOLOGY_LEVEL_TYPE, NA, FALSE) \ -FIELD( B, 0, EDX, INTEL, 0, 32, TOPOLOGY_X2APIC_ID, NA, FALSE) - -/* LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */ -#define CPUID_FIELD_DATA_LEVEL_D \ -FLAG( D, 0, EAX, COMMON, 0, 1, XCR0_MASTER_LEGACY_FP, YES, FALSE) \ -FLAG( D, 0, EAX, COMMON, 1, 1, XCR0_MASTER_SSE, YES, FALSE) \ -FLAG( D, 0, EAX, COMMON, 2, 1, XCR0_MASTER_YMM_H, YES, FALSE) \ -FIELD( D, 0, EAX, COMMON, 3, 29, XCR0_MASTER_LOWER, NO, FALSE) \ -FIELD( D, 0, EBX, COMMON, 0, 32, XSAVE_ENABLED_SIZE, ANY, FALSE) \ -FIELD( D, 0, ECX, COMMON, 0, 32, XSAVE_MAX_SIZE, YES, FALSE) \ -FIELD( D, 0, EDX, COMMON, 0, 29, XCR0_MASTER_UPPER, NO, FALSE) \ -FLAG( D, 0, EDX, AMD, 30, 1, XCR0_MASTER_LWP, NO, FALSE) \ -FLAG( D, 0, EDX, COMMON, 31, 1, XCR0_MASTER_EXTENDED_XSAVE, NO, FALSE) \ -FLAG( D, 1, EAX, COMMON, 0, 1, XSAVEOPT, NO, FALSE) \ -FIELD( D, 2, EAX, COMMON, 0, 32, XSAVE_YMM_SIZE, YES, FALSE) \ -FIELD( D, 2, EBX, COMMON, 0, 32, XSAVE_YMM_OFFSET, YES, FALSE) \ -FIELD( D, 2, ECX, COMMON, 0, 32, XSAVE_YMM_RSVD1, YES, FALSE) \ -FIELD( D, 2, EDX, COMMON, 0, 32, XSAVE_YMM_RSVD2, YES, FALSE) \ -FIELD( D, 62, EAX, AMD, 0, 32, XSAVE_LWP_SIZE, NO, FALSE) \ -FIELD( D, 62, EBX, AMD, 0, 32, XSAVE_LWP_OFFSET, NO, FALSE) \ -FIELD( D, 62, ECX, AMD, 0, 32, XSAVE_LWP_RSVD1, NO, FALSE) \ -FIELD( D, 62, EDX, AMD, 0, 32, XSAVE_LWP_RSVD2, NO, FALSE) - - -/* LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */ -#define CPUID_FIELD_DATA_LEVEL_400 \ -FIELD(400, 0, EAX, COMMON, 0, 32, NUM_HYP_LEVELS, NA, FALSE) \ -FIELD(400, 0, EBX, COMMON, 0, 32, HYPERVISOR1, NA, FALSE) \ -FIELD(400, 0, ECX, COMMON, 0, 32, HYPERVISOR2, NA, FALSE) \ -FIELD(400, 0, EDX, COMMON, 0, 32, HYPERVISOR3, NA, FALSE) - -/* LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */ -#define CPUID_FIELD_DATA_LEVEL_410 \ -FIELD(410, 0, EAX, COMMON, 0, 32, TSC_HZ, NA, FALSE) \ -FIELD(410, 0, EBX, COMMON, 0, 32, ACPIBUS_HZ, NA, FALSE) - -/* LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */ -#define CPUID_FIELD_DATA_LEVEL_80 \ -FIELD( 80, 0, EAX, COMMON, 0, 32, NUM_EXT_LEVELS, NA, FALSE) \ -FIELD( 80, 0, EBX, AMD, 0, 32, LEAF80_VENDOR1, NA, FALSE) \ -FIELD( 80, 0, ECX, AMD, 0, 32, LEAF80_VENDOR3, NA, FALSE) \ -FIELD( 80, 0, EDX, AMD, 0, 32, LEAF80_VENDOR2, NA, FALSE) +/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, CPL3 */ +#define CPUID_FIELD_DATA_LEVEL_A \ +FIELD( A, 0, EAX, 0, 8, PMC_VERSION, NA, FALSE) \ +FIELD( A, 0, EAX, 8, 8, PMC_NUM_GEN, NA, FALSE) \ +FIELD( A, 0, EAX, 16, 8, PMC_WIDTH_GEN, NA, FALSE) \ +FIELD( A, 0, EAX, 24, 8, PMC_EBX_LENGTH, NA, FALSE) \ +FLAG( A, 0, EBX, 0, 1, PMC_CORE_CYCLES, NA, FALSE) \ +FLAG( A, 0, EBX, 1, 1, PMC_INSTR_RETIRED, NA, FALSE) \ +FLAG( A, 0, EBX, 2, 1, PMC_REF_CYCLES, NA, FALSE) \ +FLAG( A, 0, EBX, 3, 1, PMC_LAST_LVL_CREF, NA, FALSE) \ +FLAG( A, 0, EBX, 4, 1, PMC_LAST_LVL_CMISS, NA, FALSE) \ +FLAG( A, 0, EBX, 5, 1, PMC_BR_INST_RETIRED, NA, FALSE) \ +FLAG( A, 0, EBX, 6, 1, PMC_BR_MISS_RETIRED, NA, FALSE) \ +FIELD( A, 0, EDX, 0, 5, PMC_NUM_FIXED, NA, FALSE) \ +FIELD( A, 0, EDX, 5, 8, PMC_WIDTH_FIXED, NA, FALSE) + +/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, CPL3 */ +#define CPUID_FIELD_DATA_LEVEL_B \ +FIELD( B, 0, EAX, 0, 5, TOPOLOGY_MASK_WIDTH, NA, FALSE) \ +FIELD( B, 0, EBX, 0, 16, TOPOLOGY_CPUS_SHARING_LEVEL, NA, FALSE) \ +FIELD( B, 0, ECX, 0, 8, TOPOLOGY_LEVEL_NUMBER, NA, FALSE) \ +FIELD( B, 0, ECX, 8, 8, TOPOLOGY_LEVEL_TYPE, NA, FALSE) \ +FIELD( B, 0, EDX, 0, 32, TOPOLOGY_X2APIC_ID, NA, FALSE) + +/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, CPL3 */ +#define CPUID_FIELD_DATA_LEVEL_D \ +FLAG( D, 0, EAX, 0, 1, XCR0_MASTER_LEGACY_FP, YES, FALSE) \ +FLAG( D, 0, EAX, 1, 1, XCR0_MASTER_SSE, YES, FALSE) \ +FLAG( D, 0, EAX, 2, 1, XCR0_MASTER_YMM_H, YES, FALSE) \ +FIELD( D, 0, EAX, 3, 29, XCR0_MASTER_LOWER, NO, FALSE) \ +FIELD( D, 0, EBX, 0, 32, XSAVE_ENABLED_SIZE, ANY, FALSE) \ +FIELD( D, 0, ECX, 0, 32, XSAVE_MAX_SIZE, YES, FALSE) \ +FIELD( D, 0, EDX, 0, 29, XCR0_MASTER_UPPER, NO, FALSE) \ +FLAG( D, 0, EDX, 30, 1, XCR0_MASTER_LWP, NO, FALSE) \ +FLAG( D, 0, EDX, 31, 1, XCR0_MASTER_EXTENDED_XSAVE, NO, FALSE) \ +FLAG( D, 1, EAX, 0, 1, XSAVEOPT, NO, FALSE) \ +FIELD( D, 2, EAX, 0, 32, XSAVE_YMM_SIZE, YES, FALSE) \ +FIELD( D, 2, EBX, 0, 32, XSAVE_YMM_OFFSET, YES, FALSE) \ +FIELD( D, 2, ECX, 0, 32, XSAVE_YMM_RSVD1, YES, FALSE) \ +FIELD( D, 2, EDX, 0, 32, XSAVE_YMM_RSVD2, YES, FALSE) \ +FIELD( D, 62, EAX, 0, 32, XSAVE_LWP_SIZE, NO, FALSE) \ +FIELD( D, 62, EBX, 0, 32, XSAVE_LWP_OFFSET, NO, FALSE) \ +FIELD( D, 62, ECX, 0, 32, XSAVE_LWP_RSVD1, NO, FALSE) \ +FIELD( D, 62, EDX, 0, 32, XSAVE_LWP_RSVD2, NO, FALSE) + + +/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, CPL3 */ +#define CPUID_FIELD_DATA_LEVEL_400 \ +FIELD(400, 0, EAX, 0, 32, NUM_HYP_LEVELS, NA, FALSE) \ +FIELD(400, 0, EBX, 0, 32, HYPERVISOR1, NA, FALSE) \ +FIELD(400, 0, ECX, 0, 32, HYPERVISOR2, NA, FALSE) \ +FIELD(400, 0, EDX, 0, 32, HYPERVISOR3, NA, FALSE) + +/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, CPL3 */ +#define CPUID_FIELD_DATA_LEVEL_410 \ +FIELD(410, 0, EAX, 0, 32, TSC_HZ, NA, FALSE) \ +FIELD(410, 0, EBX, 0, 32, ACPIBUS_HZ, NA, FALSE) + +/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, CPL3 */ +#define CPUID_FIELD_DATA_LEVEL_80 \ +FIELD( 80, 0, EAX, 0, 32, NUM_EXT_LEVELS, NA, FALSE) \ +FIELD( 80, 0, EBX, 0, 32, LEAF80_VENDOR1, NA, FALSE) \ +FIELD( 80, 0, ECX, 0, 32, LEAF80_VENDOR3, NA, FALSE) \ +FIELD( 80, 0, EDX, 0, 32, LEAF80_VENDOR2, NA, FALSE) #define CPUID_81_ECX_17 -/* LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */ -#define CPUID_FIELD_DATA_LEVEL_81 \ -FIELD( 81, 0, EAX, INTEL, 0, 32, UNKNOWN81EAX, ANY, FALSE) \ -FIELD( 81, 0, EAX, AMD, 0, 4, LEAF81_STEPPING, ANY, FALSE) \ -FIELD( 81, 0, EAX, AMD, 4, 4, LEAF81_MODEL, ANY, FALSE) \ -FIELD( 81, 0, EAX, AMD, 8, 4, LEAF81_FAMILY, ANY, FALSE) \ -FIELD( 81, 0, EAX, AMD, 12, 2, LEAF81_TYPE, ANY, FALSE) \ -FIELD( 81, 0, EAX, AMD, 16, 4, LEAF81_EXTENDED_MODEL, ANY, FALSE) \ -FIELD( 81, 0, EAX, AMD, 20, 8, LEAF81_EXTENDED_FAMILY, ANY, FALSE) \ -FIELD( 81, 0, EBX, INTEL, 0, 32, UNKNOWN81EBX, ANY, FALSE) \ -FIELD( 81, 0, EBX, AMD, 0, 16, LEAF81_BRAND_ID, ANY, FALSE) \ -FIELD( 81, 0, EBX, AMD, 16, 16, UNDEF, ANY, FALSE) \ -FLAG( 81, 0, ECX, COMMON, 0, 1, LAHF64, YES, TRUE) \ -FLAG( 81, 0, ECX, AMD, 1, 1, CMPLEGACY, ANY, FALSE) \ -FLAG( 81, 0, ECX, AMD, 2, 1, SVM, YES, FALSE) \ -FLAG( 81, 0, ECX, AMD, 3, 1, EXTAPICSPC, YES, FALSE) \ -FLAG( 81, 0, ECX, AMD, 4, 1, CR8AVAIL, YES, FALSE) \ -FLAG( 81, 0, ECX, COMMON, 5, 1, ABM, YES, TRUE) \ -FLAG( 81, 0, ECX, AMD, 6, 1, SSE4A, YES, TRUE) \ -FLAG( 81, 0, ECX, AMD, 7, 1, MISALIGNED_SSE, YES, TRUE) \ -FLAG( 81, 0, ECX, AMD, 8, 1, 3DNPREFETCH, YES, TRUE) \ -FLAG( 81, 0, ECX, AMD, 9, 1, OSVW, ANY, FALSE) \ -FLAG( 81, 0, ECX, AMD, 10, 1, IBS, NO, FALSE) \ -FLAG( 81, 0, ECX, AMD, 11, 1, XOP, YES, TRUE) \ -FLAG( 81, 0, ECX, AMD, 12, 1, SKINIT, NO, FALSE) \ -FLAG( 81, 0, ECX, AMD, 13, 1, WATCHDOG, NO, FALSE) \ -FLAG( 81, 0, ECX, AMD, 15, 1, LWP, NO, FALSE) \ -FLAG( 81, 0, ECX, AMD, 16, 1, FMA4, YES, TRUE) \ +/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, CPL3 */ +#define CPUID_FIELD_DATA_LEVEL_81 \ +FIELD( 81, 0, EAX, 0, 32, UNKNOWN81EAX, ANY, FALSE) \ +FIELD( 81, 0, EAX, 0, 4, LEAF81_STEPPING, ANY, FALSE) \ +FIELD( 81, 0, EAX, 4, 4, LEAF81_MODEL, ANY, FALSE) \ +FIELD( 81, 0, EAX, 8, 4, LEAF81_FAMILY, ANY, FALSE) \ +FIELD( 81, 0, EAX, 12, 2, LEAF81_TYPE, ANY, FALSE) \ +FIELD( 81, 0, EAX, 16, 4, LEAF81_EXTENDED_MODEL, ANY, FALSE) \ +FIELD( 81, 0, EAX, 20, 8, LEAF81_EXTENDED_FAMILY, ANY, FALSE) \ +FIELD( 81, 0, EBX, 0, 32, UNKNOWN81EBX, ANY, FALSE) \ +FIELD( 81, 0, EBX, 0, 16, LEAF81_BRAND_ID, ANY, FALSE) \ +FIELD( 81, 0, EBX, 16, 16, UNDEF, ANY, FALSE) \ +FLAG( 81, 0, ECX, 0, 1, LAHF64, YES, TRUE) \ +FLAG( 81, 0, ECX, 1, 1, CMPLEGACY, ANY, FALSE) \ +FLAG( 81, 0, ECX, 2, 1, SVM, YES, FALSE) \ +FLAG( 81, 0, ECX, 3, 1, EXTAPICSPC, YES, FALSE) \ +FLAG( 81, 0, ECX, 4, 1, CR8AVAIL, YES, FALSE) \ +FLAG( 81, 0, ECX, 5, 1, ABM, YES, TRUE) \ +FLAG( 81, 0, ECX, 6, 1, SSE4A, YES, TRUE) \ +FLAG( 81, 0, ECX, 7, 1, MISALIGNED_SSE, YES, TRUE) \ +FLAG( 81, 0, ECX, 8, 1, 3DNPREFETCH, YES, TRUE) \ +FLAG( 81, 0, ECX, 9, 1, OSVW, ANY, FALSE) \ +FLAG( 81, 0, ECX, 10, 1, IBS, NO, FALSE) \ +FLAG( 81, 0, ECX, 11, 1, XOP, YES, TRUE) \ +FLAG( 81, 0, ECX, 12, 1, SKINIT, NO, FALSE) \ +FLAG( 81, 0, ECX, 13, 1, WATCHDOG, NO, FALSE) \ +FLAG( 81, 0, ECX, 15, 1, LWP, NO, FALSE) \ +FLAG( 81, 0, ECX, 16, 1, FMA4, YES, TRUE) \ CPUID_81_ECX_17 \ -FLAG( 81, 0, ECX, AMD, 19, 1, NODEID_MSR, NO, FALSE) \ -FLAG( 81, 0, ECX, AMD, 21, 1, TBM, YES, TRUE) \ -FLAG( 81, 0, ECX, AMD, 22, 1, TOPOLOGY, NO, FALSE) \ -FLAG( 81, 0, EDX, AMD, 0, 1, LEAF81_FPU, YES, TRUE) \ -FLAG( 81, 0, EDX, AMD, 1, 1, LEAF81_VME, YES, FALSE) \ -FLAG( 81, 0, EDX, AMD, 2, 1, LEAF81_DE, YES, FALSE) \ -FLAG( 81, 0, EDX, AMD, 3, 1, LEAF81_PSE, YES, FALSE) \ -FLAG( 81, 0, EDX, AMD, 4, 1, LEAF81_TSC, YES, TRUE) \ -FLAG( 81, 0, EDX, AMD, 5, 1, LEAF81_MSR, YES, FALSE) \ -FLAG( 81, 0, EDX, AMD, 6, 1, LEAF81_PAE, YES, FALSE) \ -FLAG( 81, 0, EDX, AMD, 7, 1, LEAF81_MCE, YES, FALSE) \ -FLAG( 81, 0, EDX, AMD, 8, 1, LEAF81_CX8, YES, TRUE) \ -FLAG( 81, 0, EDX, AMD, 9, 1, LEAF81_APIC, ANY, FALSE) \ -FLAG( 81, 0, EDX, COMMON, 11, 1, SYSC, ANY, TRUE) \ -FLAG( 81, 0, EDX, AMD, 12, 1, LEAF81_MTRR, YES, FALSE) \ -FLAG( 81, 0, EDX, AMD, 13, 1, LEAF81_PGE, YES, FALSE) \ -FLAG( 81, 0, EDX, AMD, 14, 1, LEAF81_MCA, YES, FALSE) \ -FLAG( 81, 0, EDX, AMD, 15, 1, LEAF81_CMOV, YES, TRUE) \ -FLAG( 81, 0, EDX, AMD, 16, 1, LEAF81_PAT, YES, FALSE) \ -FLAG( 81, 0, EDX, AMD, 17, 1, LEAF81_PSE36, YES, FALSE) \ -FLAG( 81, 0, EDX, COMMON, 20, 1, NX, YES, FALSE) \ -FLAG( 81, 0, EDX, AMD, 22, 1, MMXEXT, YES, TRUE) \ -FLAG( 81, 0, EDX, AMD, 23, 1, LEAF81_MMX, YES, TRUE) \ -FLAG( 81, 0, EDX, AMD, 24, 1, LEAF81_FXSR, YES, TRUE) \ -FLAG( 81, 0, EDX, AMD, 25, 1, FFXSR, YES, FALSE) \ -FLAG( 81, 0, EDX, COMMON, 26, 1, PDPE1GB, YES, FALSE) \ -FLAG( 81, 0, EDX, COMMON, 27, 1, RDTSCP, YES, TRUE) \ -FLAG( 81, 0, EDX, COMMON, 29, 1, LM, YES, FALSE) \ -FLAG( 81, 0, EDX, AMD, 30, 1, 3DNOWPLUS, YES, TRUE) \ -FLAG( 81, 0, EDX, AMD, 31, 1, 3DNOW, YES, TRUE) +FLAG( 81, 0, ECX, 19, 1, NODEID_MSR, NO, FALSE) \ +FLAG( 81, 0, ECX, 21, 1, TBM, YES, TRUE) \ +FLAG( 81, 0, ECX, 22, 1, TOPOLOGY, NO, FALSE) \ +FLAG( 81, 0, EDX, 0, 1, LEAF81_FPU, YES, TRUE) \ +FLAG( 81, 0, EDX, 1, 1, LEAF81_VME, YES, FALSE) \ +FLAG( 81, 0, EDX, 2, 1, LEAF81_DE, YES, FALSE) \ +FLAG( 81, 0, EDX, 3, 1, LEAF81_PSE, YES, FALSE) \ +FLAG( 81, 0, EDX, 4, 1, LEAF81_TSC, YES, TRUE) \ +FLAG( 81, 0, EDX, 5, 1, LEAF81_MSR, YES, FALSE) \ +FLAG( 81, 0, EDX, 6, 1, LEAF81_PAE, YES, FALSE) \ +FLAG( 81, 0, EDX, 7, 1, LEAF81_MCE, YES, FALSE) \ +FLAG( 81, 0, EDX, 8, 1, LEAF81_CX8, YES, TRUE) \ +FLAG( 81, 0, EDX, 9, 1, LEAF81_APIC, ANY, FALSE) \ +FLAG( 81, 0, EDX, 11, 1, SYSC, ANY, TRUE) \ +FLAG( 81, 0, EDX, 12, 1, LEAF81_MTRR, YES, FALSE) \ +FLAG( 81, 0, EDX, 13, 1, LEAF81_PGE, YES, FALSE) \ +FLAG( 81, 0, EDX, 14, 1, LEAF81_MCA, YES, FALSE) \ +FLAG( 81, 0, EDX, 15, 1, LEAF81_CMOV, YES, TRUE) \ +FLAG( 81, 0, EDX, 16, 1, LEAF81_PAT, YES, FALSE) \ +FLAG( 81, 0, EDX, 17, 1, LEAF81_PSE36, YES, FALSE) \ +FLAG( 81, 0, EDX, 20, 1, NX, YES, FALSE) \ +FLAG( 81, 0, EDX, 22, 1, MMXEXT, YES, TRUE) \ +FLAG( 81, 0, EDX, 23, 1, LEAF81_MMX, YES, TRUE) \ +FLAG( 81, 0, EDX, 24, 1, LEAF81_FXSR, YES, TRUE) \ +FLAG( 81, 0, EDX, 25, 1, FFXSR, YES, FALSE) \ +FLAG( 81, 0, EDX, 26, 1, PDPE1GB, YES, FALSE) \ +FLAG( 81, 0, EDX, 27, 1, RDTSCP, YES, TRUE) \ +FLAG( 81, 0, EDX, 29, 1, LM, YES, FALSE) \ +FLAG( 81, 0, EDX, 30, 1, 3DNOWPLUS, YES, TRUE) \ +FLAG( 81, 0, EDX, 31, 1, 3DNOW, YES, TRUE) #define CPUID_8A_EDX_11 \ -FLAG( 8A, 0, EDX, AMD, 11, 1, SVMEDX_RSVD1, NO, FALSE) +FLAG( 8A, 0, EDX, 11, 1, SVMEDX_RSVD1, NO, FALSE) #define CPUID_8A_EDX_13_31 \ -FIELD( 8A, 0, EDX, AMD, 13, 19, SVMEDX_RSVD2, NO, FALSE) - -/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */ -#define CPUID_FIELD_DATA_LEVEL_8x \ -FIELD( 85, 0, EAX, AMD, 0, 8, ITLB_ENTRIES_2M4M_PGS, NA, FALSE) \ -FIELD( 85, 0, EAX, AMD, 8, 8, ITLB_ASSOC_2M4M_PGS, NA, FALSE) \ -FIELD( 85, 0, EAX, AMD, 16, 8, DTLB_ENTRIES_2M4M_PGS, NA, FALSE) \ -FIELD( 85, 0, EAX, AMD, 24, 8, DTLB_ASSOC_2M4M_PGS, NA, FALSE) \ -FIELD( 85, 0, EBX, AMD, 0, 8, ITLB_ENTRIES_4K_PGS, NA, FALSE) \ -FIELD( 85, 0, EBX, AMD, 8, 8, ITLB_ASSOC_4K_PGS, NA, FALSE) \ -FIELD( 85, 0, EBX, AMD, 16, 8, DTLB_ENTRIES_4K_PGS, NA, FALSE) \ -FIELD( 85, 0, EBX, AMD, 24, 8, DTLB_ASSOC_4K_PGS, NA, FALSE) \ -FIELD( 85, 0, ECX, AMD, 0, 8, L1_DCACHE_LINE_SIZE, NA, FALSE) \ -FIELD( 85, 0, ECX, AMD, 8, 8, L1_DCACHE_LINES_PER_TAG, NA, FALSE) \ -FIELD( 85, 0, ECX, AMD, 16, 8, L1_DCACHE_ASSOC, NA, FALSE) \ -FIELD( 85, 0, ECX, AMD, 24, 8, L1_DCACHE_SIZE, NA, FALSE) \ -FIELD( 85, 0, EDX, AMD, 0, 8, L1_ICACHE_LINE_SIZE, NA, FALSE) \ -FIELD( 85, 0, EDX, AMD, 8, 8, L1_ICACHE_LINES_PER_TAG, NA, FALSE) \ -FIELD( 85, 0, EDX, AMD, 16, 8, L1_ICACHE_ASSOC, NA, FALSE) \ -FIELD( 85, 0, EDX, AMD, 24, 8, L1_ICACHE_SIZE, NA, FALSE) \ -FIELD( 86, 0, EAX, AMD, 0, 12, L2_ITLB_ENTRIES_2M4M_PGS, NA, FALSE) \ -FIELD( 86, 0, EAX, AMD, 12, 4, L2_ITLB_ASSOC_2M4M_PGS, NA, FALSE) \ -FIELD( 86, 0, EAX, AMD, 16, 12, L2_DTLB_ENTRIES_2M4M_PGS, NA, FALSE) \ -FIELD( 86, 0, EAX, AMD, 28, 4, L2_DTLB_ASSOC_2M4M_PGS, NA, FALSE) \ -FIELD( 86, 0, EBX, AMD, 0, 12, L2_ITLB_ENTRIES_4K_PGS, NA, FALSE) \ -FIELD( 86, 0, EBX, AMD, 12, 4, L2_ITLB_ASSOC_4K_PGS, NA, FALSE) \ -FIELD( 86, 0, EBX, AMD, 16, 12, L2_DTLB_ENTRIES_4K_PGS, NA, FALSE) \ -FIELD( 86, 0, EBX, AMD, 28, 4, L2_DTLB_ASSOC_4K_PGS, NA, FALSE) \ -FIELD( 86, 0, ECX, AMD, 0, 8, L2CACHE_LINE, NA, FALSE) \ -FIELD( 86, 0, ECX, AMD, 8, 4, L2CACHE_LINE_PER_TAG, NA, FALSE) \ -FIELD( 86, 0, ECX, AMD, 12, 4, L2CACHE_WAYS, NA, FALSE) \ -FIELD( 86, 0, ECX, AMD, 16, 16, L2CACHE_SIZE, NA, FALSE) \ -FIELD( 86, 0, EDX, AMD, 0, 8, L3CACHE_LINE, NA, FALSE) \ -FIELD( 86, 0, EDX, AMD, 8, 4, L3CACHE_LINE_PER_TAG, NA, FALSE) \ -FIELD( 86, 0, EDX, AMD, 12, 4, L3CACHE_WAYS, NA, FALSE) \ -FIELD( 86, 0, EDX, AMD, 18, 14, L3CACHE_SIZE, NA, FALSE) \ -FLAG( 87, 0, EDX, AMD, 0, 1, TS, NA, FALSE) \ -FLAG( 87, 0, EDX, AMD, 1, 1, FID, NA, FALSE) \ -FLAG( 87, 0, EDX, AMD, 2, 1, VID, NA, FALSE) \ -FLAG( 87, 0, EDX, AMD, 3, 1, TTP, NA, FALSE) \ -FLAG( 87, 0, EDX, AMD, 4, 1, LEAF87_TM, NA, FALSE) \ -FLAG( 87, 0, EDX, AMD, 5, 1, STC, NA, FALSE) \ -FLAG( 87, 0, EDX, AMD, 6, 1, 100MHZSTEPS, NA, FALSE) \ -FLAG( 87, 0, EDX, AMD, 7, 1, HWPSTATE, NA, FALSE) \ -FLAG( 87, 0, EDX, COMMON, 8, 1, TSC_INVARIANT, NA, FALSE) \ -FLAG( 87, 0, EDX, COMMON, 9, 1, CORE_PERF_BOOST, NA, FALSE) \ -FIELD( 88, 0, EAX, COMMON, 0, 8, PHYS_BITS, NA, FALSE) \ -FIELD( 88, 0, EAX, COMMON, 8, 8, VIRT_BITS, NA, FALSE) \ -FIELD( 88, 0, EAX, COMMON, 16, 8, GUEST_PHYS_ADDR_SZ, NA, FALSE) \ -FIELD( 88, 0, ECX, AMD, 0, 8, LEAF88_CORE_COUNT, NA, FALSE) \ -FIELD( 88, 0, ECX, AMD, 12, 4, APICID_COREID_SIZE, NA, FALSE) \ -FIELD( 8A, 0, EAX, AMD, 0, 8, SVM_REVISION, YES, FALSE) \ -FLAG( 8A, 0, EAX, AMD, 8, 1, SVM_HYPERVISOR, NO, FALSE) \ -FIELD( 8A, 0, EAX, AMD, 9, 23, SVMEAX_RSVD, NO, FALSE) \ -FIELD( 8A, 0, EBX, AMD, 0, 32, SVM_NUM_ASIDS, YES, FALSE) \ -FIELD( 8A, 0, ECX, AMD, 0, 32, SVMECX_RSVD, NO, FALSE) \ -FLAG( 8A, 0, EDX, AMD, 0, 1, SVM_NPT, YES, FALSE) \ -FLAG( 8A, 0, EDX, AMD, 1, 1, SVM_LBR, NO, FALSE) \ -FLAG( 8A, 0, EDX, AMD, 2, 1, SVM_LOCK, ANY, FALSE) \ -FLAG( 8A, 0, EDX, AMD, 3, 1, SVM_NRIP, YES, FALSE) \ -FLAG( 8A, 0, EDX, AMD, 4, 1, SVM_TSC_RATE_MSR, NO, FALSE) \ -FLAG( 8A, 0, EDX, AMD, 5, 1, SVM_VMCB_CLEAN, YES, FALSE) \ -FLAG( 8A, 0, EDX, AMD, 6, 1, SVM_FLUSH_BY_ASID, YES, FALSE) \ -FLAG( 8A, 0, EDX, AMD, 7, 1, SVM_DECODE_ASSISTS, YES, FALSE) \ -FIELD( 8A, 0, EDX, AMD, 8, 2, SVMEDX_RSVD0, NO, FALSE) \ -FLAG( 8A, 0, EDX, AMD, 10, 1, SVM_PAUSE_FILTER, NO, FALSE) \ +FIELD( 8A, 0, EDX, 13, 19, SVMEDX_RSVD2, NO, FALSE) + +/* LEVEL, REG, POS, SIZE, NAME, MON SUPP, CPL3 */ +#define CPUID_FIELD_DATA_LEVEL_8x \ +FIELD( 85, 0, EAX, 0, 8, ITLB_ENTRIES_2M4M_PGS, NA, FALSE) \ +FIELD( 85, 0, EAX, 8, 8, ITLB_ASSOC_2M4M_PGS, NA, FALSE) \ +FIELD( 85, 0, EAX, 16, 8, DTLB_ENTRIES_2M4M_PGS, NA, FALSE) \ +FIELD( 85, 0, EAX, 24, 8, DTLB_ASSOC_2M4M_PGS, NA, FALSE) \ +FIELD( 85, 0, EBX, 0, 8, ITLB_ENTRIES_4K_PGS, NA, FALSE) \ +FIELD( 85, 0, EBX, 8, 8, ITLB_ASSOC_4K_PGS, NA, FALSE) \ +FIELD( 85, 0, EBX, 16, 8, DTLB_ENTRIES_4K_PGS, NA, FALSE) \ +FIELD( 85, 0, EBX, 24, 8, DTLB_ASSOC_4K_PGS, NA, FALSE) \ +FIELD( 85, 0, ECX, 0, 8, L1_DCACHE_LINE_SIZE, NA, FALSE) \ +FIELD( 85, 0, ECX, 8, 8, L1_DCACHE_LINES_PER_TAG, NA, FALSE) \ +FIELD( 85, 0, ECX, 16, 8, L1_DCACHE_ASSOC, NA, FALSE) \ +FIELD( 85, 0, ECX, 24, 8, L1_DCACHE_SIZE, NA, FALSE) \ +FIELD( 85, 0, EDX, 0, 8, L1_ICACHE_LINE_SIZE, NA, FALSE) \ +FIELD( 85, 0, EDX, 8, 8, L1_ICACHE_LINES_PER_TAG, NA, FALSE) \ +FIELD( 85, 0, EDX, 16, 8, L1_ICACHE_ASSOC, NA, FALSE) \ +FIELD( 85, 0, EDX, 24, 8, L1_ICACHE_SIZE, NA, FALSE) \ +FIELD( 86, 0, EAX, 0, 12, L2_ITLB_ENTRIES_2M4M_PGS, NA, FALSE) \ +FIELD( 86, 0, EAX, 12, 4, L2_ITLB_ASSOC_2M4M_PGS, NA, FALSE) \ +FIELD( 86, 0, EAX, 16, 12, L2_DTLB_ENTRIES_2M4M_PGS, NA, FALSE) \ +FIELD( 86, 0, EAX, 28, 4, L2_DTLB_ASSOC_2M4M_PGS, NA, FALSE) \ +FIELD( 86, 0, EBX, 0, 12, L2_ITLB_ENTRIES_4K_PGS, NA, FALSE) \ +FIELD( 86, 0, EBX, 12, 4, L2_ITLB_ASSOC_4K_PGS, NA, FALSE) \ +FIELD( 86, 0, EBX, 16, 12, L2_DTLB_ENTRIES_4K_PGS, NA, FALSE) \ +FIELD( 86, 0, EBX, 28, 4, L2_DTLB_ASSOC_4K_PGS, NA, FALSE) \ +FIELD( 86, 0, ECX, 0, 8, L2CACHE_LINE, NA, FALSE) \ +FIELD( 86, 0, ECX, 8, 4, L2CACHE_LINE_PER_TAG, NA, FALSE) \ +FIELD( 86, 0, ECX, 12, 4, L2CACHE_WAYS, NA, FALSE) \ +FIELD( 86, 0, ECX, 16, 16, L2CACHE_SIZE, NA, FALSE) \ +FIELD( 86, 0, EDX, 0, 8, L3CACHE_LINE, NA, FALSE) \ +FIELD( 86, 0, EDX, 8, 4, L3CACHE_LINE_PER_TAG, NA, FALSE) \ +FIELD( 86, 0, EDX, 12, 4, L3CACHE_WAYS, NA, FALSE) \ +FIELD( 86, 0, EDX, 18, 14, L3CACHE_SIZE, NA, FALSE) \ +FLAG( 87, 0, EDX, 0, 1, TS, NA, FALSE) \ +FLAG( 87, 0, EDX, 1, 1, FID, NA, FALSE) \ +FLAG( 87, 0, EDX, 2, 1, VID, NA, FALSE) \ +FLAG( 87, 0, EDX, 3, 1, TTP, NA, FALSE) \ +FLAG( 87, 0, EDX, 4, 1, LEAF87_TM, NA, FALSE) \ +FLAG( 87, 0, EDX, 5, 1, STC, NA, FALSE) \ +FLAG( 87, 0, EDX, 6, 1, 100MHZSTEPS, NA, FALSE) \ +FLAG( 87, 0, EDX, 7, 1, HWPSTATE, NA, FALSE) \ +FLAG( 87, 0, EDX, 8, 1, TSC_INVARIANT, NA, FALSE) \ +FLAG( 87, 0, EDX, 9, 1, CORE_PERF_BOOST, NA, FALSE) \ +FIELD( 88, 0, EAX, 0, 8, PHYS_BITS, NA, FALSE) \ +FIELD( 88, 0, EAX, 8, 8, VIRT_BITS, NA, FALSE) \ +FIELD( 88, 0, EAX, 16, 8, GUEST_PHYS_ADDR_SZ, NA, FALSE) \ +FIELD( 88, 0, ECX, 0, 8, LEAF88_CORE_COUNT, NA, FALSE) \ +FIELD( 88, 0, ECX, 12, 4, APICID_COREID_SIZE, NA, FALSE) \ +FIELD( 8A, 0, EAX, 0, 8, SVM_REVISION, YES, FALSE) \ +FLAG( 8A, 0, EAX, 8, 1, SVM_HYPERVISOR, NO, FALSE) \ +FIELD( 8A, 0, EAX, 9, 23, SVMEAX_RSVD, NO, FALSE) \ +FIELD( 8A, 0, EBX, 0, 32, SVM_NUM_ASIDS, YES, FALSE) \ +FIELD( 8A, 0, ECX, 0, 32, SVMECX_RSVD, NO, FALSE) \ +FLAG( 8A, 0, EDX, 0, 1, SVM_NPT, YES, FALSE) \ +FLAG( 8A, 0, EDX, 1, 1, SVM_LBR, NO, FALSE) \ +FLAG( 8A, 0, EDX, 2, 1, SVM_LOCK, ANY, FALSE) \ +FLAG( 8A, 0, EDX, 3, 1, SVM_NRIP, YES, FALSE) \ +FLAG( 8A, 0, EDX, 4, 1, SVM_TSC_RATE_MSR, NO, FALSE) \ +FLAG( 8A, 0, EDX, 5, 1, SVM_VMCB_CLEAN, YES, FALSE) \ +FLAG( 8A, 0, EDX, 6, 1, SVM_FLUSH_BY_ASID, YES, FALSE) \ +FLAG( 8A, 0, EDX, 7, 1, SVM_DECODE_ASSISTS, YES, FALSE) \ +FIELD( 8A, 0, EDX, 8, 2, SVMEDX_RSVD0, NO, FALSE) \ +FLAG( 8A, 0, EDX, 10, 1, SVM_PAUSE_FILTER, NO, FALSE) \ CPUID_8A_EDX_11 \ -FLAG( 8A, 0, EDX, AMD, 12, 1, SVM_PAUSE_THRESHOLD, NO, FALSE) \ +FLAG( 8A, 0, EDX, 12, 1, SVM_PAUSE_THRESHOLD, NO, FALSE) \ CPUID_8A_EDX_13_31 -/* LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */ -#define CPUID_FIELD_DATA_LEVEL_81x \ -FIELD(819, 0, EAX, AMD, 0, 12, L1_ITLB_ENTRIES_1G_PGS, NA, FALSE) \ -FIELD(819, 0, EAX, AMD, 12, 4, L1_ITLB_ASSOC_1G_PGS, NA, FALSE) \ -FIELD(819, 0, EAX, AMD, 16, 12, L1_DTLB_ENTRIES_1G_PGS, NA, FALSE) \ -FIELD(819, 0, EAX, AMD, 28, 4, L1_DTLB_ASSOC_1G_PGS, NA, FALSE) \ -FIELD(819, 0, EBX, AMD, 0, 12, L2_ITLB_ENTRIES_1G_PGS, NA, FALSE) \ -FIELD(819, 0, EBX, AMD, 12, 4, L2_ITLB_ASSOC_1G_PGS, NA, FALSE) \ -FIELD(819, 0, EBX, AMD, 16, 12, L2_DTLB_ENTRIES_1G_PGS, NA, FALSE) \ -FIELD(819, 0, EBX, AMD, 28, 4, L2_DTLB_ASSOC_1G_PGS, NA, FALSE) \ -FLAG( 81A, 0, EAX, AMD, 0, 1, FP128, NA, FALSE) \ -FLAG( 81A, 0, EAX, AMD, 1, 1, MOVU, NA, FALSE) \ -FLAG( 81B, 0, EAX, AMD, 0, 1, IBS_FFV, NA, FALSE) \ -FLAG( 81B, 0, EAX, AMD, 1, 1, IBS_FETCHSAM, NA, FALSE) \ -FLAG( 81B, 0, EAX, AMD, 2, 1, IBS_OPSAM, NA, FALSE) \ -FLAG( 81B, 0, EAX, AMD, 3, 1, RW_OPCOUNT, NA, FALSE) \ -FLAG( 81B, 0, EAX, AMD, 4, 1, OPCOUNT, NA, FALSE) \ -FLAG( 81B, 0, EAX, AMD, 5, 1, BRANCH_TARGET_ADDR, NA, FALSE) \ -FLAG( 81B, 0, EAX, AMD, 6, 1, OPCOUNT_EXT, NA, FALSE) \ -FLAG( 81B, 0, EAX, AMD, 7, 1, RIP_INVALID_CHECK, NA, FALSE) \ -FLAG( 81C, 0, EAX, AMD, 0, 1, LWP_AVAIL, NA, FALSE) \ -FLAG( 81C, 0, EAX, AMD, 1, 1, LWP_VAL_AVAIL, NA, FALSE) \ -FLAG( 81C, 0, EAX, AMD, 2, 1, LWP_IRE_AVAIL, NA, FALSE) \ -FLAG( 81C, 0, EAX, AMD, 3, 1, LWP_BRE_AVAIL, NA, FALSE) \ -FLAG( 81C, 0, EAX, AMD, 4, 1, LWP_DME_AVAIL, NA, FALSE) \ -FLAG( 81C, 0, EAX, AMD, 5, 1, LWP_CNH_AVAIL, NA, FALSE) \ -FLAG( 81C, 0, EAX, AMD, 6, 1, LWP_RNH_AVAIL, NA, FALSE) \ -FLAG( 81C, 0, EAX, AMD, 31, 1, LWP_INT_AVAIL, NA, FALSE) \ -FIELD(81C, 0, EBX, AMD, 0, 8, LWP_CB_SIZE, NA, FALSE) \ -FIELD(81C, 0, EBX, AMD, 8, 8, LWP_EVENT_SIZE, NA, FALSE) \ -FIELD(81C, 0, EBX, AMD, 16, 8, LWP_MAX_EVENTS, NA, FALSE) \ -FIELD(81C, 0, EBX, AMD, 24, 8, LWP_EVENT_OFFSET, NA, FALSE) \ -FIELD(81C, 0, ECX, AMD, 0, 4, LWP_LATENCY_MAX, NA, FALSE) \ -FLAG( 81C, 0, ECX, AMD, 5, 1, LWP_DATA_ADDR_VALID, NA, FALSE) \ -FIELD(81C, 0, ECX, AMD, 6, 3, LWP_LATENCY_ROUND, NA, FALSE) \ -FIELD(81C, 0, ECX, AMD, 9, 7, LWP_VERSION, NA, FALSE) \ -FIELD(81C, 0, ECX, AMD, 16, 8, LWP_MIN_BUF_SIZE, NA, FALSE) \ -FLAG( 81C, 0, ECX, AMD, 28, 1, LWP_BRANCH_PRED, NA, FALSE) \ -FLAG( 81C, 0, ECX, AMD, 29, 1, LWP_IP_FILTERING, NA, FALSE) \ -FLAG( 81C, 0, ECX, AMD, 30, 1, LWP_CACHE_LEVEL, NA, FALSE) \ -FLAG( 81C, 0, ECX, AMD, 31, 1, LWP_CACHE_LATENCY, NA, FALSE) \ -FLAG( 81C, 0, EDX, AMD, 0, 1, LWP_SUPPORTED, NA, FALSE) \ -FLAG( 81C, 0, EDX, AMD, 1, 1, LWP_VAL_SUPPORTED, NA, FALSE) \ -FLAG( 81C, 0, EDX, AMD, 2, 1, LWP_IRE_SUPPORTED, NA, FALSE) \ -FLAG( 81C, 0, EDX, AMD, 3, 1, LWP_BRE_SUPPORTED, NA, FALSE) \ -FLAG( 81C, 0, EDX, AMD, 4, 1, LWP_DME_SUPPORTED, NA, FALSE) \ -FLAG( 81C, 0, EDX, AMD, 5, 1, LWP_CNH_SUPPORTED, NA, FALSE) \ -FLAG( 81C, 0, EDX, AMD, 6, 1, LWP_RNH_SUPPORTED, NA, FALSE) \ -FLAG( 81C, 0, EDX, AMD, 31, 1, LWP_INT_SUPPORTED, NA, FALSE) \ -FIELD(81D, 0, EAX, AMD, 0, 5, LEAF81D_CACHE_TYPE, NA, FALSE) \ -FIELD(81D, 0, EAX, AMD, 5, 3, LEAF81D_CACHE_LEVEL, NA, FALSE) \ -FLAG( 81D, 0, EAX, AMD, 8, 1, LEAF81D_CACHE_SELF_INIT, NA, FALSE) \ -FLAG( 81D, 0, EAX, AMD, 9, 1, LEAF81D_CACHE_FULLY_ASSOC, NA, FALSE) \ -FIELD(81D, 0, EAX, AMD, 14, 12, LEAF81D_NUM_SHARING_CACHE, NA, FALSE) \ -FIELD(81D, 0, EBX, AMD, 0, 12, LEAF81D_CACHE_LINE_SIZE, NA, FALSE) \ -FIELD(81D, 0, EBX, AMD, 12, 10, LEAF81D_CACHE_PHYS_PARTITIONS, NA, FALSE) \ -FIELD(81D, 0, EBX, AMD, 22, 10, LEAF81D_CACHE_WAYS, NA, FALSE) \ -FIELD(81D, 0, ECX, AMD, 0, 32, LEAF81D_CACHE_NUM_SETS, NA, FALSE) \ -FLAG( 81D, 0, EDX, AMD, 0, 1, LEAF81D_CACHE_WBINVD, NA, FALSE) \ -FLAG( 81D, 0, EDX, AMD, 1, 1, LEAF81D_CACHE_INCLUSIVE, NA, FALSE) \ -FIELD(81E, 0, EAX, AMD, 0, 32, EXTENDED_APICID, NA, FALSE) \ -FIELD(81E, 0, EBX, AMD, 0, 8, COMPUTE_UNIT_ID, NA, FALSE) \ -FIELD(81E, 0, EBX, AMD, 8, 2, CORES_PER_COMPUTE_UNIT, NA, FALSE) \ -FIELD(81E, 0, ECX, AMD, 0, 8, NODEID_VAL, NA, FALSE) \ -FIELD(81E, 0, ECX, AMD, 8, 3, NODES_PER_PKG, NA, FALSE) - +/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, CPL3 */ +#define CPUID_FIELD_DATA_LEVEL_81x \ +FIELD(819, 0, EAX, 0, 12, L1_ITLB_ENTRIES_1G_PGS, NA, FALSE) \ +FIELD(819, 0, EAX, 12, 4, L1_ITLB_ASSOC_1G_PGS, NA, FALSE) \ +FIELD(819, 0, EAX, 16, 12, L1_DTLB_ENTRIES_1G_PGS, NA, FALSE) \ +FIELD(819, 0, EAX, 28, 4, L1_DTLB_ASSOC_1G_PGS, NA, FALSE) \ +FIELD(819, 0, EBX, 0, 12, L2_ITLB_ENTRIES_1G_PGS, NA, FALSE) \ +FIELD(819, 0, EBX, 12, 4, L2_ITLB_ASSOC_1G_PGS, NA, FALSE) \ +FIELD(819, 0, EBX, 16, 12, L2_DTLB_ENTRIES_1G_PGS, NA, FALSE) \ +FIELD(819, 0, EBX, 28, 4, L2_DTLB_ASSOC_1G_PGS, NA, FALSE) \ +FLAG( 81A, 0, EAX, 0, 1, FP128, NA, FALSE) \ +FLAG( 81A, 0, EAX, 1, 1, MOVU, NA, FALSE) \ +FLAG( 81B, 0, EAX, 0, 1, IBS_FFV, NA, FALSE) \ +FLAG( 81B, 0, EAX, 1, 1, IBS_FETCHSAM, NA, FALSE) \ +FLAG( 81B, 0, EAX, 2, 1, IBS_OPSAM, NA, FALSE) \ +FLAG( 81B, 0, EAX, 3, 1, RW_OPCOUNT, NA, FALSE) \ +FLAG( 81B, 0, EAX, 4, 1, OPCOUNT, NA, FALSE) \ +FLAG( 81B, 0, EAX, 5, 1, BRANCH_TARGET_ADDR, NA, FALSE) \ +FLAG( 81B, 0, EAX, 6, 1, OPCOUNT_EXT, NA, FALSE) \ +FLAG( 81B, 0, EAX, 7, 1, RIP_INVALID_CHECK, NA, FALSE) \ +FLAG( 81C, 0, EAX, 0, 1, LWP_AVAIL, NA, FALSE) \ +FLAG( 81C, 0, EAX, 1, 1, LWP_VAL_AVAIL, NA, FALSE) \ +FLAG( 81C, 0, EAX, 2, 1, LWP_IRE_AVAIL, NA, FALSE) \ +FLAG( 81C, 0, EAX, 3, 1, LWP_BRE_AVAIL, NA, FALSE) \ +FLAG( 81C, 0, EAX, 4, 1, LWP_DME_AVAIL, NA, FALSE) \ +FLAG( 81C, 0, EAX, 5, 1, LWP_CNH_AVAIL, NA, FALSE) \ +FLAG( 81C, 0, EAX, 6, 1, LWP_RNH_AVAIL, NA, FALSE) \ +FLAG( 81C, 0, EAX, 31, 1, LWP_INT_AVAIL, NA, FALSE) \ +FIELD(81C, 0, EBX, 0, 8, LWP_CB_SIZE, NA, FALSE) \ +FIELD(81C, 0, EBX, 8, 8, LWP_EVENT_SIZE, NA, FALSE) \ +FIELD(81C, 0, EBX, 16, 8, LWP_MAX_EVENTS, NA, FALSE) \ +FIELD(81C, 0, EBX, 24, 8, LWP_EVENT_OFFSET, NA, FALSE) \ +FIELD(81C, 0, ECX, 0, 4, LWP_LATENCY_MAX, NA, FALSE) \ +FLAG( 81C, 0, ECX, 5, 1, LWP_DATA_ADDR_VALID, NA, FALSE) \ +FIELD(81C, 0, ECX, 6, 3, LWP_LATENCY_ROUND, NA, FALSE) \ +FIELD(81C, 0, ECX, 9, 7, LWP_VERSION, NA, FALSE) \ +FIELD(81C, 0, ECX, 16, 8, LWP_MIN_BUF_SIZE, NA, FALSE) \ +FLAG( 81C, 0, ECX, 28, 1, LWP_BRANCH_PRED, NA, FALSE) \ +FLAG( 81C, 0, ECX, 29, 1, LWP_IP_FILTERING, NA, FALSE) \ +FLAG( 81C, 0, ECX, 30, 1, LWP_CACHE_LEVEL, NA, FALSE) \ +FLAG( 81C, 0, ECX, 31, 1, LWP_CACHE_LATENCY, NA, FALSE) \ +FLAG( 81C, 0, EDX, 0, 1, LWP_SUPPORTED, NA, FALSE) \ +FLAG( 81C, 0, EDX, 1, 1, LWP_VAL_SUPPORTED, NA, FALSE) \ +FLAG( 81C, 0, EDX, 2, 1, LWP_IRE_SUPPORTED, NA, FALSE) \ +FLAG( 81C, 0, EDX, 3, 1, LWP_BRE_SUPPORTED, NA, FALSE) \ +FLAG( 81C, 0, EDX, 4, 1, LWP_DME_SUPPORTED, NA, FALSE) \ +FLAG( 81C, 0, EDX, 5, 1, LWP_CNH_SUPPORTED, NA, FALSE) \ +FLAG( 81C, 0, EDX, 6, 1, LWP_RNH_SUPPORTED, NA, FALSE) \ +FLAG( 81C, 0, EDX, 31, 1, LWP_INT_SUPPORTED, NA, FALSE) \ +FIELD(81D, 0, EAX, 0, 5, LEAF81D_CACHE_TYPE, NA, FALSE) \ +FIELD(81D, 0, EAX, 5, 3, LEAF81D_CACHE_LEVEL, NA, FALSE) \ +FLAG( 81D, 0, EAX, 8, 1, LEAF81D_CACHE_SELF_INIT, NA, FALSE) \ +FLAG( 81D, 0, EAX, 9, 1, LEAF81D_CACHE_FULLY_ASSOC, NA, FALSE) \ +FIELD(81D, 0, EAX, 14, 12, LEAF81D_NUM_SHARING_CACHE, NA, FALSE) \ +FIELD(81D, 0, EBX, 0, 12, LEAF81D_CACHE_LINE_SIZE, NA, FALSE) \ +FIELD(81D, 0, EBX, 12, 10, LEAF81D_CACHE_PHYS_PARTITIONS, NA, FALSE) \ +FIELD(81D, 0, EBX, 22, 10, LEAF81D_CACHE_WAYS, NA, FALSE) \ +FIELD(81D, 0, ECX, 0, 32, LEAF81D_CACHE_NUM_SETS, NA, FALSE) \ +FLAG( 81D, 0, EDX, 0, 1, LEAF81D_CACHE_WBINVD, NA, FALSE) \ +FLAG( 81D, 0, EDX, 1, 1, LEAF81D_CACHE_INCLUSIVE, NA, FALSE) \ +FIELD(81E, 0, EAX, 0, 32, EXTENDED_APICID, NA, FALSE) \ +FIELD(81E, 0, EBX, 0, 8, COMPUTE_UNIT_ID, NA, FALSE) \ +FIELD(81E, 0, EBX, 8, 2, CORES_PER_COMPUTE_UNIT, NA, FALSE) \ +FIELD(81E, 0, ECX, 0, 8, NODEID_VAL, NA, FALSE) \ +FIELD(81E, 0, ECX, 8, 3, NODES_PER_PKG, NA, FALSE) #define INTEL_CPUID_FIELD_DATA #define AMD_CPUID_FIELD_DATA @@ -717,17 +716,15 @@ FIELD(81E, 0, ECX, AMD, 8, 3, NODES_PER_PKG, NA, FALSE) */ #define VMW_BIT_MASK(shift) (((1 << (shift - 1)) << 1) - 1) -#define FIELD(lvl, ecxIn, reg, vend, bitpos, size, name, s, c3) \ - CPUID_##vend##_ID##lvl##reg##_##name##_SHIFT = bitpos, \ - CPUID_##vend##_ID##lvl##reg##_##name##_MASK = \ - VMW_BIT_MASK(size) << bitpos, \ - CPUID_FEATURE_##vend##_ID##lvl##reg##_##name = \ - CPUID_##vend##_ID##lvl##reg##_##name##_MASK, \ - CPUID_INTERNAL_SHIFT_##name = bitpos, \ - CPUID_INTERNAL_MASK_##name = VMW_BIT_MASK(size) << bitpos, \ - CPUID_INTERNAL_REG_##name = CPUID_REG_##reg, \ - CPUID_INTERNAL_EAXIN_##name = CPUID_LEVEL_VAL_##lvl, \ - CPUID_INTERNAL_ECXIN_##name = ecxIn, +#define FIELD(lvl, ecxIn, reg, bitpos, size, name, s, c3) \ + CPUID_ID##lvl##reg##_##name##_SHIFT = bitpos, \ + CPUID_ID##lvl##reg##_##name##_MASK = VMW_BIT_MASK(size) << bitpos, \ + CPUID_FEATURE_ID##lvl##reg##_##name = CPUID_ID##lvl##reg##_##name##_MASK, \ + CPUID_INTERNAL_SHIFT_##name = bitpos, \ + CPUID_INTERNAL_MASK_##name = VMW_BIT_MASK(size) << bitpos, \ + CPUID_INTERNAL_REG_##name = CPUID_REG_##reg, \ + CPUID_INTERNAL_EAXIN_##name = CPUID_LEVEL_VAL_##lvl, \ + CPUID_INTERNAL_ECXIN_##name = ecxIn, #define FLAG FIELD diff --git a/open-vm-tools/lib/misc/strutil.c b/open-vm-tools/lib/misc/strutil.c index 6a46969e7..096b5fb7d 100644 --- a/open-vm-tools/lib/misc/strutil.c +++ b/open-vm-tools/lib/misc/strutil.c @@ -520,12 +520,12 @@ StrUtil_StrToDouble(double *out, // OUT: The output value /* *----------------------------------------------------------------------------- * - * StrUtil_CapacityToSectorType -- + * StrUtil_CapacityToBytes -- * - * Converts a string containing a measure of disk capacity (such as - * "100MB" or "1.5k") into an unadorned and primitive quantity of sector + * Converts a string containing a measure of capacity (such as + * "100MB" or "1.5k") into an unadorned and primitive quantity of bytes * capacity. The comment before the switch statement describes the kinds - * of disk capacity expressible. + * of capacity expressible. * * Results: * TRUE if conversion was successful, FALSE otherwise. @@ -538,10 +538,10 @@ StrUtil_StrToDouble(double *out, // OUT: The output value */ Bool -StrUtil_CapacityToSectorType(SectorType *out, // OUT: The output value - const char *str, // IN: String to parse - unsigned int bytes) // IN: Bytes per unit in an - // unadorned string +StrUtil_CapacityToBytes(uint64 *out, // OUT: The output value + const char *str, // IN: String to parse + unsigned int bytes) // IN: Bytes per unit in an + // unadorned string { double quantity; @@ -601,6 +601,44 @@ StrUtil_CapacityToSectorType(SectorType *out, // OUT: The output value quantity *= bytes; } + *out = quantity; + + return TRUE; +} + + +/* + *----------------------------------------------------------------------------- + * + * StrUtil_CapacityToSectorType -- + * + * Converts a string containing a measure of disk capacity (such as + * "100MB" or "1.5k") into an unadorned and primitive quantity of sector + * capacity. + * + * Results: + * TRUE if conversion was successful, FALSE otherwise. + * Value is stored in 'out', which is left undefined in the FALSE case. + * + * Side effects: + * None + * + *----------------------------------------------------------------------------- + */ + +Bool +StrUtil_CapacityToSectorType(SectorType *out, // OUT: The output value + const char *str, // IN: String to parse + unsigned int bytes) // IN: Bytes per unit in an + // unadorned string + +{ + uint64 quantityInBytes; + + if (StrUtil_CapacityToBytes(&quantityInBytes, str, bytes) == FALSE) { + return FALSE; + } + /* * Convert from "number of bytes" to "number of sectors", rounding up or * down appropriately. @@ -609,7 +647,7 @@ StrUtil_CapacityToSectorType(SectorType *out, // OUT: The output value * disklib header dependencies in this file? * */ - *out = (SectorType)((quantity + 256) / 512); + *out = (SectorType)((quantityInBytes + 256) / 512); return TRUE; } diff --git a/open-vm-tools/services/plugins/vix/vixTools.c b/open-vm-tools/services/plugins/vix/vixTools.c index 672ff8757..88397ae2f 100644 --- a/open-vm-tools/services/plugins/vix/vixTools.c +++ b/open-vm-tools/services/plugins/vix/vixTools.c @@ -124,10 +124,7 @@ * No support for open-vm-tools. */ #if (defined(_WIN32) || defined(linux)) && !defined(OPEN_VM_TOOLS) -/* - * XXX Turn off until VGAuth name changes flush through. - */ -#define SUPPORT_VGAUTH 0 +#define SUPPORT_VGAUTH 1 #else #define SUPPORT_VGAUTH 0 #endif