From: Jeffrey A Law <law@cygnus.com>
Date: Thu, 20 Nov 1997 23:21:45 +0000 (+0000)
Subject: pa.md (pre_stwm, [...]): Base register is an in/out operand.
X-Git-Tag: releases/libf2c-0.5.21~532
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=1b8b89f158ea11eb2910df4c625ea1b3126ae189;p=thirdparty%2Fgcc.git

pa.md (pre_stwm, [...]): Base register is an in/out operand.

        * pa.md (pre_stwm, post_stwm, pre_ldwm, post_ldwm): Base register
        is an in/out operand.
        (zero extended variants of stwm/stwm patterns): Similarly.

From-SVN: r16620
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7855dadf6cf4..407814f1643b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -9,6 +9,10 @@ Thu Nov 20 14:42:15 1997  Jason Merrill  <jason@yorick.cygnus.com>
 
 Thu Nov 20 16:11:50 1997  Jeffrey A Law  (law@cygnus.com)
 
+	* pa.md (pre_stwm, post_stwm, pre_ldwm, post_ldwm): Base register
+	is an in/out operand.
+	(zero extended variants of stwm/stwm patterns): Similarly.
+
 	* mips/x-iris (FIXPROTO_DEFINES): Add -D_SGI_SOURCE.
 
 Thu Nov 20 13:19:32 1997  Jason Merrill  <jason@yorick.cygnus.com>
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index f5f0f1314616..d1e89a1ddf19 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -1431,7 +1431,7 @@
 
 (define_insn "pre_ldwm"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "=r")
+	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
 			 (match_operand:SI 2 "pre_cint_operand" ""))))
    (set (match_dup 1)
 	(plus:SI (match_dup 1) (match_dup 2)))]
@@ -1446,7 +1446,7 @@
    (set_attr "length" "4")])
 
 (define_insn "pre_stwm"
-  [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "=r")
+  [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
 			 (match_operand:SI 1 "pre_cint_operand" "")))
 	(match_operand:SI 2 "reg_or_0_operand" "rM"))
    (set (match_dup 0)
@@ -1463,7 +1463,7 @@
 
 (define_insn "post_ldwm"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(mem:SI (match_operand:SI 1 "register_operand" "=r")))
+	(mem:SI (match_operand:SI 1 "register_operand" "+r")))
    (set (match_dup 1)
 	(plus:SI (match_dup 1)
 		 (match_operand:SI 2 "post_cint_operand" "")))]
@@ -1478,7 +1478,7 @@
    (set_attr "length" "4")])
 
 (define_insn "post_stwm"
-  [(set (mem:SI (match_operand:SI 0 "register_operand" "=r"))
+  [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
 	(match_operand:SI 1 "reg_or_0_operand" "rM"))
    (set (match_dup 0)
 	(plus:SI (match_dup 0)
@@ -1807,7 +1807,7 @@
 
 (define_insn ""
   [(set (match_operand:HI 0 "register_operand" "=r")
-	(mem:HI (plus:SI (match_operand:SI 1 "register_operand" "=r")
+	(mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
 			 (match_operand:SI 2 "int5_operand" "L"))))
    (set (match_dup 1)
 	(plus:SI (match_dup 1) (match_dup 2)))]
@@ -1821,7 +1821,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(zero_extend:SI (mem:HI
 			  (plus:SI
-			    (match_operand:SI 1 "register_operand" "=r")
+			    (match_operand:SI 1 "register_operand" "+r")
 			    (match_operand:SI 2 "int5_operand" "L")))))
    (set (match_dup 1)
 	(plus:SI (match_dup 1) (match_dup 2)))]
@@ -1831,7 +1831,7 @@
    (set_attr "length" "4")])
 
 (define_insn ""
-  [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "=r")
+  [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
 			 (match_operand:SI 1 "int5_operand" "L")))
 	(match_operand:HI 2 "reg_or_0_operand" "rM"))
    (set (match_dup 0)
@@ -2011,7 +2011,7 @@
 
 (define_insn ""
   [(set (match_operand:QI 0 "register_operand" "=r")
-	(mem:QI (plus:SI (match_operand:SI 1 "register_operand" "=r")
+	(mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
 			 (match_operand:SI 2 "int5_operand" "L"))))
    (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
   ""
@@ -2023,7 +2023,7 @@
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(zero_extend:SI (mem:QI (plus:SI
-				  (match_operand:SI 1 "register_operand" "=r")
+				  (match_operand:SI 1 "register_operand" "+r")
 				  (match_operand:SI 2 "int5_operand" "L")))))
    (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
   ""
@@ -2034,7 +2034,7 @@
 (define_insn ""
   [(set (match_operand:HI 0 "register_operand" "=r")
 	(zero_extend:HI (mem:QI (plus:SI
-				  (match_operand:SI 1 "register_operand" "=r")
+				  (match_operand:SI 1 "register_operand" "+r")
 				  (match_operand:SI 2 "int5_operand" "L")))))
    (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
   ""
@@ -2043,7 +2043,7 @@
    (set_attr "length" "4")])
 
 (define_insn ""
-  [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "=r")
+  [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
 			 (match_operand:SI 1 "int5_operand" "L")))
 	(match_operand:QI 2 "reg_or_0_operand" "rM"))
    (set (match_dup 0)