From: John Linn <john.linn@xilinx.com>
Date: Wed, 30 Nov 2011 01:12:27 +0000 (-0800)
Subject: Xilinx: ARM: BSP: remove DDR init for zc770
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=1bfada1b0b2a588f7342791b65951adc591ca10f;p=thirdparty%2Fu-boot.git

Xilinx: ARM: BSP: remove DDR init for zc770

This should not be needed as FSBL will be doing it. The DDR init
was causing a hang and was not needed anyway.
---

diff --git a/board/xilinx/dfe/lowlevel_init.S b/board/xilinx/dfe/lowlevel_init.S
index 72c245bf95d..2094abd02c4 100755
--- a/board/xilinx/dfe/lowlevel_init.S
+++ b/board/xilinx/dfe/lowlevel_init.S
@@ -65,12 +65,16 @@ lowlevel_init:
 	ldr r2, =0x767B
 	str r2, [r1]
 
+#ifdef CONFIG_EP107
+	# this should not be needed after EP107
+
 	# Do nothing if DDR already running
 	ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0)
 	ldr r2, [r1]
 	ldr r3, =0x201
 	cmp r2, r3
 	bne doit
+#endif
 
 	mov pc, lr