From: Christian König Date: Thu, 29 Jan 2015 15:01:03 +0000 (+0100) Subject: drm/radeon: fix PLLs on RS880 and older v2 X-Git-Tag: v3.16.35~2872 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=1d5626b98117dac5e0f0034b490cc732b8e6fd70;p=thirdparty%2Fkernel%2Fstable.git drm/radeon: fix PLLs on RS880 and older v2 commit 72edd83cc9e5819ed1ee771519143d7594e059f0 upstream. This is a workaround for RS880 and older chips which seem to have an additional limit on the minimum PLL input frequency. v2: fix signed/unsigned warning bugs: https://bugzilla.kernel.org/show_bug.cgi?id=91861 https://bugzilla.kernel.org/show_bug.cgi?id=83461 Signed-off-by: Christian König Signed-off-by: Alex Deucher Signed-off-by: Luis Henriques --- diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index bf25061c8ac4e..13ac29b1fa0cf 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -1000,6 +1000,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && pll->flags & RADEON_PLL_USE_REF_DIV) ref_div_max = pll->reference_div; + else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) + /* fix for problems on RS880 */ + ref_div_max = min(pll->max_ref_div, 7u); else ref_div_max = pll->max_ref_div;