From: Greg Kroah-Hartman Date: Sat, 23 Jul 2022 14:02:23 +0000 (+0200) Subject: 5.15-stable patches X-Git-Tag: v5.10.133~56 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=1e8d98e601e4b299717fe5465d2353707b2a43f7;p=thirdparty%2Fkernel%2Fstable-queue.git 5.15-stable patches added patches: bus-mhi-host-pci_generic-add-telit-fn980-v1-hardware-revision.patch bus-mhi-host-pci_generic-add-telit-fn990.patch drm-ttm-fix-locking-in-vmap-vunmap-ttm-gem-helpers.patch lockdown-fix-kexec-lockdown-bypass-with-ima-policy.patch mlxsw-spectrum_router-fix-ipv4-nexthop-gateway-indication.patch pinctrl-stm32-fix-optional-irq-support-to-gpios.patch riscv-add-as-options-for-modules-with-assembly-compontents.patch --- diff --git a/queue-5.15/bus-mhi-host-pci_generic-add-telit-fn980-v1-hardware-revision.patch b/queue-5.15/bus-mhi-host-pci_generic-add-telit-fn980-v1-hardware-revision.patch new file mode 100644 index 00000000000..5444dc96db4 --- /dev/null +++ b/queue-5.15/bus-mhi-host-pci_generic-add-telit-fn980-v1-hardware-revision.patch @@ -0,0 +1,73 @@ +From a96ef8b504efb2ad445dfb6d54f9488c3ddf23d2 Mon Sep 17 00:00:00 2001 +From: Daniele Palmas +Date: Wed, 27 Apr 2022 09:26:48 +0200 +Subject: bus: mhi: host: pci_generic: add Telit FN980 v1 hardware revision + +From: Daniele Palmas + +commit a96ef8b504efb2ad445dfb6d54f9488c3ddf23d2 upstream. + +Add Telit FN980 v1 hardware revision: + +01:00.0 Unassigned class [ff00]: Qualcomm Device [17cb:0306] + Subsystem: Device [1c5d:2000] + +Signed-off-by: Daniele Palmas +Reviewed-by: Manivannan Sadhasivam +Link: https://lore.kernel.org/r/20220427072648.17635-1-dnlplm@gmail.com +[mani: Added "host" to the subject] +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Fabio Porcedda +Signed-off-by: Greg Kroah-Hartman +--- + drivers/bus/mhi/pci_generic.c | 38 ++++++++++++++++++++++++++++++++++++++ + 1 file changed, 38 insertions(+) + +--- a/drivers/bus/mhi/pci_generic.c ++++ b/drivers/bus/mhi/pci_generic.c +@@ -406,7 +406,45 @@ static const struct mhi_pci_dev_info mhi + .mru_default = 32768, + }; + ++static const struct mhi_channel_config mhi_telit_fn980_hw_v1_channels[] = { ++ MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), ++ MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), ++ MHI_CHANNEL_CONFIG_UL(20, "IPCR", 16, 0), ++ MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 16, 0), ++ MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), ++ MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), ++}; ++ ++static struct mhi_event_config mhi_telit_fn980_hw_v1_events[] = { ++ MHI_EVENT_CONFIG_CTRL(0, 128), ++ MHI_EVENT_CONFIG_HW_DATA(1, 1024, 100), ++ MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) ++}; ++ ++static struct mhi_controller_config modem_telit_fn980_hw_v1_config = { ++ .max_channels = 128, ++ .timeout_ms = 20000, ++ .num_channels = ARRAY_SIZE(mhi_telit_fn980_hw_v1_channels), ++ .ch_cfg = mhi_telit_fn980_hw_v1_channels, ++ .num_events = ARRAY_SIZE(mhi_telit_fn980_hw_v1_events), ++ .event_cfg = mhi_telit_fn980_hw_v1_events, ++}; ++ ++static const struct mhi_pci_dev_info mhi_telit_fn980_hw_v1_info = { ++ .name = "telit-fn980-hwv1", ++ .fw = "qcom/sdx55m/sbl1.mbn", ++ .edl = "qcom/sdx55m/edl.mbn", ++ .config = &modem_telit_fn980_hw_v1_config, ++ .bar_num = MHI_PCI_DEFAULT_BAR_NUM, ++ .dma_data_width = 32, ++ .mru_default = 32768, ++ .sideband_wake = false, ++}; ++ + static const struct pci_device_id mhi_pci_id_table[] = { ++ /* Telit FN980 hardware revision v1 */ ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x1C5D, 0x2000), ++ .driver_data = (kernel_ulong_t) &mhi_telit_fn980_hw_v1_info }, + { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), + .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, + { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), diff --git a/queue-5.15/bus-mhi-host-pci_generic-add-telit-fn990.patch b/queue-5.15/bus-mhi-host-pci_generic-add-telit-fn990.patch new file mode 100644 index 00000000000..6258c47513d --- /dev/null +++ b/queue-5.15/bus-mhi-host-pci_generic-add-telit-fn990.patch @@ -0,0 +1,82 @@ +From 77fc41204734042861210b9d05338c9b8360affb Mon Sep 17 00:00:00 2001 +From: Daniele Palmas +Date: Mon, 2 May 2022 13:20:36 +0200 +Subject: bus: mhi: host: pci_generic: add Telit FN990 + +From: Daniele Palmas + +commit 77fc41204734042861210b9d05338c9b8360affb upstream. + +Add Telit FN990: + +01:00.0 Unassigned class [ff00]: Qualcomm Device 0308 + Subsystem: Device 1c5d:2010 + +Signed-off-by: Daniele Palmas +Reviewed-by: Manivannan Sadhasivam +Link: https://lore.kernel.org/r/20220502112036.443618-1-dnlplm@gmail.com +[mani: Added "host" to the subject] +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Fabio Porcedda +Signed-off-by: Greg Kroah-Hartman +--- + drivers/bus/mhi/pci_generic.c | 41 +++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 41 insertions(+) + +--- a/drivers/bus/mhi/pci_generic.c ++++ b/drivers/bus/mhi/pci_generic.c +@@ -441,6 +441,44 @@ static const struct mhi_pci_dev_info mhi + .sideband_wake = false, + }; + ++static const struct mhi_channel_config mhi_telit_fn990_channels[] = { ++ MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), ++ MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), ++ MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1), ++ MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1), ++ MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), ++ MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), ++ MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), ++ MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), ++ MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), ++ MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), ++}; ++ ++static struct mhi_event_config mhi_telit_fn990_events[] = { ++ MHI_EVENT_CONFIG_CTRL(0, 128), ++ MHI_EVENT_CONFIG_DATA(1, 128), ++ MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), ++ MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) ++}; ++ ++static const struct mhi_controller_config modem_telit_fn990_config = { ++ .max_channels = 128, ++ .timeout_ms = 20000, ++ .num_channels = ARRAY_SIZE(mhi_telit_fn990_channels), ++ .ch_cfg = mhi_telit_fn990_channels, ++ .num_events = ARRAY_SIZE(mhi_telit_fn990_events), ++ .event_cfg = mhi_telit_fn990_events, ++}; ++ ++static const struct mhi_pci_dev_info mhi_telit_fn990_info = { ++ .name = "telit-fn990", ++ .config = &modem_telit_fn990_config, ++ .bar_num = MHI_PCI_DEFAULT_BAR_NUM, ++ .dma_data_width = 32, ++ .sideband_wake = false, ++ .mru_default = 32768, ++}; ++ + static const struct pci_device_id mhi_pci_id_table[] = { + /* Telit FN980 hardware revision v1 */ + { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x1C5D, 0x2000), +@@ -449,6 +487,9 @@ static const struct pci_device_id mhi_pc + .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, + { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), + .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info }, ++ /* Telit FN990 */ ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2010), ++ .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info }, + { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */ + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, + { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */ diff --git a/queue-5.15/drm-ttm-fix-locking-in-vmap-vunmap-ttm-gem-helpers.patch b/queue-5.15/drm-ttm-fix-locking-in-vmap-vunmap-ttm-gem-helpers.patch new file mode 100644 index 00000000000..5067464fbbc --- /dev/null +++ b/queue-5.15/drm-ttm-fix-locking-in-vmap-vunmap-ttm-gem-helpers.patch @@ -0,0 +1,58 @@ +From dbd0da2453c694f2f74651834d90fb280b57f151 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Fri, 15 Jul 2022 09:57:22 +0200 +Subject: drm/ttm: fix locking in vmap/vunmap TTM GEM helpers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christian König + +commit dbd0da2453c694f2f74651834d90fb280b57f151 upstream. + +I've stumbled over this while reviewing patches for DMA-buf and it looks +like we completely messed the locking up here. + +In general most TTM function should only be called while holding the +appropriate BO resv lock. Without this we could break the internal +buffer object state here. + +Only compile tested! + +Signed-off-by: Christian König +Fixes: 43676605f890 ("drm/ttm: Add vmap/vunmap to TTM and TTM GEM helpers") +Cc: stable@vger.kernel.org +Reviewed-by: Dmitry Osipenko +Link: https://patchwork.freedesktop.org/patch/msgid/20220715111533.467012-1-christian.koenig@amd.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/drm_gem_ttm_helper.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/drm_gem_ttm_helper.c ++++ b/drivers/gpu/drm/drm_gem_ttm_helper.c +@@ -64,8 +64,13 @@ int drm_gem_ttm_vmap(struct drm_gem_obje + struct dma_buf_map *map) + { + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); ++ int ret; + +- return ttm_bo_vmap(bo, map); ++ dma_resv_lock(gem->resv, NULL); ++ ret = ttm_bo_vmap(bo, map); ++ dma_resv_unlock(gem->resv); ++ ++ return ret; + } + EXPORT_SYMBOL(drm_gem_ttm_vmap); + +@@ -82,7 +87,9 @@ void drm_gem_ttm_vunmap(struct drm_gem_o + { + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + ++ dma_resv_lock(gem->resv, NULL); + ttm_bo_vunmap(bo, map); ++ dma_resv_unlock(gem->resv); + } + EXPORT_SYMBOL(drm_gem_ttm_vunmap); + diff --git a/queue-5.15/lockdown-fix-kexec-lockdown-bypass-with-ima-policy.patch b/queue-5.15/lockdown-fix-kexec-lockdown-bypass-with-ima-policy.patch new file mode 100644 index 00000000000..24ec02a1099 --- /dev/null +++ b/queue-5.15/lockdown-fix-kexec-lockdown-bypass-with-ima-policy.patch @@ -0,0 +1,57 @@ +From 543ce63b664e2c2f9533d089a4664b559c3e6b5b Mon Sep 17 00:00:00 2001 +From: Eric Snowberg +Date: Wed, 20 Jul 2022 12:40:27 -0400 +Subject: lockdown: Fix kexec lockdown bypass with ima policy + +From: Eric Snowberg + +commit 543ce63b664e2c2f9533d089a4664b559c3e6b5b upstream. + +The lockdown LSM is primarily used in conjunction with UEFI Secure Boot. +This LSM may also be used on machines without UEFI. It can also be +enabled when UEFI Secure Boot is disabled. One of lockdown's features +is to prevent kexec from loading untrusted kernels. Lockdown can be +enabled through a bootparam or after the kernel has booted through +securityfs. + +If IMA appraisal is used with the "ima_appraise=log" boot param, +lockdown can be defeated with kexec on any machine when Secure Boot is +disabled or unavailable. IMA prevents setting "ima_appraise=log" from +the boot param when Secure Boot is enabled, but this does not cover +cases where lockdown is used without Secure Boot. + +To defeat lockdown, boot without Secure Boot and add ima_appraise=log to +the kernel command line; then: + + $ echo "integrity" > /sys/kernel/security/lockdown + $ echo "appraise func=KEXEC_KERNEL_CHECK appraise_type=imasig" > \ + /sys/kernel/security/ima/policy + $ kexec -ls unsigned-kernel + +Add a call to verify ima appraisal is set to "enforce" whenever lockdown +is enabled. This fixes CVE-2022-21505. + +Cc: stable@vger.kernel.org +Fixes: 29d3c1c8dfe7 ("kexec: Allow kexec_file() with appropriate IMA policy when locked down") +Signed-off-by: Eric Snowberg +Acked-by: Mimi Zohar +Reviewed-by: John Haxby +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman +--- + security/integrity/ima/ima_policy.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/security/integrity/ima/ima_policy.c ++++ b/security/integrity/ima/ima_policy.c +@@ -2034,6 +2034,10 @@ bool ima_appraise_signature(enum kernel_ + if (id >= READING_MAX_ID) + return false; + ++ if (id == READING_KEXEC_IMAGE && !(ima_appraise & IMA_APPRAISE_ENFORCE) ++ && security_locked_down(LOCKDOWN_KEXEC)) ++ return false; ++ + func = read_idmap[id] ?: FILE_CHECK; + + rcu_read_lock(); diff --git a/queue-5.15/mlxsw-spectrum_router-fix-ipv4-nexthop-gateway-indication.patch b/queue-5.15/mlxsw-spectrum_router-fix-ipv4-nexthop-gateway-indication.patch new file mode 100644 index 00000000000..32a0355eb7a --- /dev/null +++ b/queue-5.15/mlxsw-spectrum_router-fix-ipv4-nexthop-gateway-indication.patch @@ -0,0 +1,44 @@ +From e5ec6a2513383fe2ecc2ee3b5f51d97acbbcd4d8 Mon Sep 17 00:00:00 2001 +From: Ido Schimmel +Date: Tue, 19 Jul 2022 15:26:26 +0300 +Subject: mlxsw: spectrum_router: Fix IPv4 nexthop gateway indication + +From: Ido Schimmel + +commit e5ec6a2513383fe2ecc2ee3b5f51d97acbbcd4d8 upstream. + +mlxsw needs to distinguish nexthops with a gateway from connected +nexthops in order to write the former to the adjacency table of the +device. The check used to rely on the fact that nexthops with a gateway +have a 'link' scope whereas connected nexthops have a 'host' scope. This +is no longer correct after commit 747c14307214 ("ip: fix dflt addr +selection for connected nexthop"). + +Fix that by instead checking the address family of the gateway IP. This +is a more direct way and also consistent with the IPv6 counterpart in +mlxsw_sp_rt6_is_gateway(). + +Cc: stable@vger.kernel.org +Fixes: 747c14307214 ("ip: fix dflt addr selection for connected nexthop") +Fixes: 597cfe4fc339 ("nexthop: Add support for IPv4 nexthops") +Signed-off-by: Ido Schimmel +Reviewed-by: Amit Cohen +Reviewed-by: Nicolas Dichtel +Reviewed-by: David Ahern +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman +--- + drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c ++++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c +@@ -5196,7 +5196,7 @@ static bool mlxsw_sp_fi_is_gateway(const + { + const struct fib_nh *nh = fib_info_nh(fi, 0); + +- return nh->fib_nh_scope == RT_SCOPE_LINK || ++ return nh->fib_nh_gw_family || + mlxsw_sp_nexthop4_ipip_type(mlxsw_sp, nh, NULL); + } + diff --git a/queue-5.15/pinctrl-stm32-fix-optional-irq-support-to-gpios.patch b/queue-5.15/pinctrl-stm32-fix-optional-irq-support-to-gpios.patch new file mode 100644 index 00000000000..d5e1532ab1e --- /dev/null +++ b/queue-5.15/pinctrl-stm32-fix-optional-irq-support-to-gpios.patch @@ -0,0 +1,63 @@ +From a1d4ef1adf8bbd302067534ead671a94759687ed Mon Sep 17 00:00:00 2001 +From: Fabien Dessenne +Date: Mon, 27 Jun 2022 16:23:50 +0200 +Subject: pinctrl: stm32: fix optional IRQ support to gpios + +From: Fabien Dessenne + +commit a1d4ef1adf8bbd302067534ead671a94759687ed upstream. + +To act as an interrupt controller, a gpio bank relies on the +"interrupt-parent" of the pin controller. +When this optional "interrupt-parent" misses, do not create any IRQ domain. + +This fixes a "NULL pointer in stm32_gpio_domain_alloc()" kernel crash when +the interrupt-parent = property is not declared in the Device Tree. + +Fixes: 0eb9f683336d ("pinctrl: Add IRQ support to STM32 gpios") +Signed-off-by: Fabien Dessenne +Link: https://lore.kernel.org/r/20220627142350.742973-1-fabien.dessenne@foss.st.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/stm32/pinctrl-stm32.c | 20 ++++++++++++-------- + 1 file changed, 12 insertions(+), 8 deletions(-) + + +--- a/drivers/pinctrl/stm32/pinctrl-stm32.c ++++ b/drivers/pinctrl/stm32/pinctrl-stm32.c +@@ -1299,15 +1299,17 @@ static int stm32_gpiolib_register_bank(s + bank->bank_ioport_nr = bank_ioport_nr; + spin_lock_init(&bank->lock); + +- /* create irq hierarchical domain */ +- bank->fwnode = of_node_to_fwnode(np); ++ if (pctl->domain) { ++ /* create irq hierarchical domain */ ++ bank->fwnode = of_node_to_fwnode(np); ++ ++ bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE, ++ bank->fwnode, &stm32_gpio_domain_ops, ++ bank); + +- bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, +- STM32_GPIO_IRQ_LINE, bank->fwnode, +- &stm32_gpio_domain_ops, bank); +- +- if (!bank->domain) +- return -ENODEV; ++ if (!bank->domain) ++ return -ENODEV; ++ } + + err = gpiochip_add_data(&bank->gpio_chip, bank); + if (err) { +@@ -1477,6 +1479,8 @@ int stm32_pctl_probe(struct platform_dev + pctl->domain = stm32_pctrl_get_irq_domain(np); + if (IS_ERR(pctl->domain)) + return PTR_ERR(pctl->domain); ++ if (!pctl->domain) ++ dev_warn(dev, "pinctrl without interrupt support\n"); + + /* hwspinlock is optional */ + hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); diff --git a/queue-5.15/riscv-add-as-options-for-modules-with-assembly-compontents.patch b/queue-5.15/riscv-add-as-options-for-modules-with-assembly-compontents.patch new file mode 100644 index 00000000000..fc659b399d3 --- /dev/null +++ b/queue-5.15/riscv-add-as-options-for-modules-with-assembly-compontents.patch @@ -0,0 +1,48 @@ +From c1f6eff304e4dfa4558b6a8c6b2d26a91db6c998 Mon Sep 17 00:00:00 2001 +From: Ben Dooks +Date: Sun, 29 May 2022 16:22:00 +0100 +Subject: riscv: add as-options for modules with assembly compontents + +From: Ben Dooks + +commit c1f6eff304e4dfa4558b6a8c6b2d26a91db6c998 upstream. + +When trying to load modules built for RISC-V which include assembly files +the kernel loader errors with "unexpected relocation type 'R_RISCV_ALIGN'" +due to R_RISCV_ALIGN relocations being generated by the assembler. + +The R_RISCV_ALIGN relocations can be removed at the expense of code space +by adding -mno-relax to gcc and as. In commit 7a8e7da42250138 +("RISC-V: Fixes to module loading") -mno-relax is added to the build +variable KBUILD_CFLAGS_MODULE. See [1] for more info. + +The issue is that when kbuild builds a .S file, it invokes gcc with +the -mno-relax flag, but this is not being passed through to the +assembler. Adding -Wa,-mno-relax to KBUILD_AFLAGS_MODULE ensures that +the assembler is invoked correctly. This may have now been fixed in +gcc[2] and this addition should not stop newer gcc and as from working. + +[1] https://github.com/riscv/riscv-elf-psabi-doc/issues/183 +[2] https://github.com/gcc-mirror/gcc/commit/3b0a7d624e64eeb81e4d5e8c62c46d86ef521857 + +Signed-off-by: Ben Dooks +Reviewed-by: Bin Meng +Link: https://lore.kernel.org/r/20220529152200.609809-1-ben.dooks@codethink.co.uk +Fixes: ab1ef68e5401 ("RISC-V: Add sections of PLT and GOT for kernel module") +Cc: stable@vger.kernel.org +Signed-off-by: Palmer Dabbelt +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/Makefile | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -75,6 +75,7 @@ ifeq ($(CONFIG_PERF_EVENTS),y) + endif + + KBUILD_CFLAGS_MODULE += $(call cc-option,-mno-relax) ++KBUILD_AFLAGS_MODULE += $(call as-option,-Wa$(comma)-mno-relax) + + # GCC versions that support the "-mstrict-align" option default to allowing + # unaligned accesses. While unaligned accesses are explicitly allowed in the