From: Sasha Levin Date: Mon, 12 Aug 2024 01:09:15 +0000 (-0400) Subject: Fixes for 6.6 X-Git-Tag: v6.1.105~101 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=1f7445674a9f8e6d784ddd3faf7807fe6a768286;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 6.6 Signed-off-by: Sasha Levin --- diff --git a/queue-6.6/alsa-usb-audio-re-add-scratchamp-quirk-entries.patch b/queue-6.6/alsa-usb-audio-re-add-scratchamp-quirk-entries.patch new file mode 100644 index 00000000000..7467ab9a331 --- /dev/null +++ b/queue-6.6/alsa-usb-audio-re-add-scratchamp-quirk-entries.patch @@ -0,0 +1,44 @@ +From 56b2d490dc8f813cc8493a9a3496ec94e2848141 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Aug 2024 10:18:01 +0200 +Subject: ALSA: usb-audio: Re-add ScratchAmp quirk entries + +From: Takashi Iwai + +[ Upstream commit 03898691d42e0170e7d00f07cbe21ce0e9f3a8fa ] + +At the code refactoring of USB-audio quirk handling, I assumed that +the quirk entries of Stanton ScratchAmp devices were only about the +device name, and moved them completely into the rename table. +But it seems that the device requires the quirk entry so that it's +probed by the driver itself. + +This re-adds back the quirk entries of ScratchAmp, but in a +minimalistic manner. + +Fixes: 5436f59bc5bc ("ALSA: usb-audio: Move device rename and profile quirks to an internal table") +Link: https://patch.msgid.link/20240808081803.22300-1-tiwai@suse.de +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/quirks-table.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h +index 5d72dc8441cbb..af1b8cf5a9883 100644 +--- a/sound/usb/quirks-table.h ++++ b/sound/usb/quirks-table.h +@@ -2594,6 +2594,10 @@ YAMAHA_DEVICE(0x7010, "UB99"), + } + }, + ++/* Stanton ScratchAmp */ ++{ USB_DEVICE(0x103d, 0x0100) }, ++{ USB_DEVICE(0x103d, 0x0101) }, ++ + /* Novation EMS devices */ + { + USB_DEVICE_VENDOR_SPEC(0x1235, 0x0001), +-- +2.43.0 + diff --git a/queue-6.6/arm64-add-neoverse-v2-part.patch b/queue-6.6/arm64-add-neoverse-v2-part.patch new file mode 100644 index 00000000000..560b0457e39 --- /dev/null +++ b/queue-6.6/arm64-add-neoverse-v2-part.patch @@ -0,0 +1,45 @@ +From 1cf0e45c05a8bf1b9b099b6f3748f95c5e7f0054 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 10:57:33 +0100 +Subject: arm64: Add Neoverse-V2 part + +From: Besar Wicaksono + +[ Upstream commit f4d9d9dcc70b96b5e5d7801bd5fbf8491b07b13d ] + +Add the part number and MIDR for Neoverse-V2 + +Signed-off-by: Besar Wicaksono +Reviewed-by: James Clark +Link: https://lore.kernel.org/r/20240109192310.16234-2-bwicaksono@nvidia.com +Signed-off-by: Will Deacon +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 52f076afeb960..936389e9aecbc 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -86,6 +86,7 @@ + #define ARM_CPU_PART_CORTEX_X2 0xD48 + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B ++#define ARM_CPU_PART_NEOVERSE_V2 0xD4F + + #define APM_CPU_PART_XGENE 0x000 + #define APM_CPU_VAR_POTENZA 0x00 +@@ -159,6 +160,7 @@ + #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) ++#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-6.6/arm64-barrier-restore-spec_bar-macro.patch b/queue-6.6/arm64-barrier-restore-spec_bar-macro.patch new file mode 100644 index 00000000000..54cfe0dded5 --- /dev/null +++ b/queue-6.6/arm64-barrier-restore-spec_bar-macro.patch @@ -0,0 +1,47 @@ +From b148ef1e5148e6d5f4014efcc9aa71f66176b639 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 10:57:34 +0100 +Subject: arm64: barrier: Restore spec_bar() macro + +From: Mark Rutland + +[ Upstream commit ebfc726eae3f31bdb5fae1bbd74ef235d71046ca ] + +Upcoming errata workarounds will need to use SB from C code. Restore the +spec_bar() macro so that we can use SB. + +This is effectively a revert of commit: + + 4f30ba1cce36d413 ("arm64: barrier: Remove spec_bar() macro") + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240508081400.235362-2-mark.rutland@arm.com +Signed-off-by: Will Deacon +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/barrier.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h +index cf2987464c186..1ca947d5c9396 100644 +--- a/arch/arm64/include/asm/barrier.h ++++ b/arch/arm64/include/asm/barrier.h +@@ -40,6 +40,10 @@ + */ + #define dgh() asm volatile("hint #6" : : : "memory") + ++#define spec_bar() asm volatile(ALTERNATIVE("dsb nsh\nisb\n", \ ++ SB_BARRIER_INSN"nop\n", \ ++ ARM64_HAS_SB)) ++ + #ifdef CONFIG_ARM64_PSEUDO_NMI + #define pmr_sync() \ + do { \ +-- +2.43.0 + diff --git a/queue-6.6/arm64-cputype-add-cortex-a720-definitions.patch b/queue-6.6/arm64-cputype-add-cortex-a720-definitions.patch new file mode 100644 index 00000000000..9b80de24387 --- /dev/null +++ b/queue-6.6/arm64-cputype-add-cortex-a720-definitions.patch @@ -0,0 +1,52 @@ +From 95cb456b407776a0357825083ecb4a44242ac0e7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 10:57:39 +0100 +Subject: arm64: cputype: Add Cortex-A720 definitions + +From: Mark Rutland + +[ Upstream commit add332c40328cf06fe35e4b3cde8ec315c4629e5 ] + +Add cputype definitions for Cortex-A720. These will be used for errata +detection in subsequent patches. + +These values can be found in Table A-186 ("MIDR_EL1 bit descriptions") +in issue 0002-05 of the Cortex-A720 TRM, which can be found at: + + https://developer.arm.com/documentation/102530/0002/?lang=en + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-3-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 72fe207403c83..dcbac1ce6c25c 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -88,6 +88,7 @@ + #define ARM_CPU_PART_CORTEX_A78C 0xD4B + #define ARM_CPU_PART_CORTEX_X3 0xD4E + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F ++#define ARM_CPU_PART_CORTEX_A720 0xD81 + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 + +@@ -165,6 +166,7 @@ + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) + #define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) ++#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) +-- +2.43.0 + diff --git a/queue-6.6/arm64-cputype-add-cortex-a725-definitions.patch b/queue-6.6/arm64-cputype-add-cortex-a725-definitions.patch new file mode 100644 index 00000000000..b5d17c3deac --- /dev/null +++ b/queue-6.6/arm64-cputype-add-cortex-a725-definitions.patch @@ -0,0 +1,54 @@ +From d5e957a58f5505d4fec430fb1a2c9e48a890b21e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 10:57:44 +0100 +Subject: arm64: cputype: Add Cortex-A725 definitions + +From: Mark Rutland + +[ Upstream commit 9ef54a384526911095db465e77acc1cb5266b32c ] + +Add cputype definitions for Cortex-A725. These will be used for errata +detection in subsequent patches. + +These values can be found in the Cortex-A725 TRM: + + https://developer.arm.com/documentation/107652/0001/ + +... in table A-247 ("MIDR_EL1 bit descriptions"). + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Reviewed-by: Anshuman Khandual +Link: https://lore.kernel.org/r/20240801101803.1982459-3-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 5dc68ace305e5..5fd7caea44193 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -93,6 +93,7 @@ + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 + #define ARM_CPU_PART_CORTEX_X925 0xD85 ++#define ARM_CPU_PART_CORTEX_A725 0xD87 + + #define APM_CPU_PART_XGENE 0x000 + #define APM_CPU_VAR_POTENZA 0x00 +@@ -173,6 +174,7 @@ + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) + #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) ++#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-6.6/arm64-cputype-add-cortex-x1c-definitions.patch b/queue-6.6/arm64-cputype-add-cortex-x1c-definitions.patch new file mode 100644 index 00000000000..a8f3d48275a --- /dev/null +++ b/queue-6.6/arm64-cputype-add-cortex-x1c-definitions.patch @@ -0,0 +1,54 @@ +From ba5e9bdf4a04253b025b7c62d8f9e1be412ee829 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 10:57:43 +0100 +Subject: arm64: cputype: Add Cortex-X1C definitions + +From: Mark Rutland + +[ Upstream commit 58d245e03c324d083a0ec3b9ab8ebd46ec9848d7 ] + +Add cputype definitions for Cortex-X1C. These will be used for errata +detection in subsequent patches. + +These values can be found in the Cortex-X1C TRM: + + https://developer.arm.com/documentation/101968/0002/ + +... in section B2.107 ("MIDR_EL1, Main ID Register, EL1"). + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Reviewed-by: Anshuman Khandual +Link: https://lore.kernel.org/r/20240801101803.1982459-2-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 1cb0704c6163f..5dc68ace305e5 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -86,6 +86,7 @@ + #define ARM_CPU_PART_CORTEX_X2 0xD48 + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B ++#define ARM_CPU_PART_CORTEX_X1C 0xD4C + #define ARM_CPU_PART_CORTEX_X3 0xD4E + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F + #define ARM_CPU_PART_CORTEX_A720 0xD81 +@@ -165,6 +166,7 @@ + #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) ++#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C) + #define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) +-- +2.43.0 + diff --git a/queue-6.6/arm64-cputype-add-cortex-x3-definitions.patch b/queue-6.6/arm64-cputype-add-cortex-x3-definitions.patch new file mode 100644 index 00000000000..376460a9a87 --- /dev/null +++ b/queue-6.6/arm64-cputype-add-cortex-x3-definitions.patch @@ -0,0 +1,52 @@ +From bfddbe5b0a0d0f21945c939dc9d9e0cd456b2eee Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 10:57:38 +0100 +Subject: arm64: cputype: Add Cortex-X3 definitions + +From: Mark Rutland + +[ Upstream commit be5a6f238700f38b534456608588723fba96c5ab ] + +Add cputype definitions for Cortex-X3. These will be used for errata +detection in subsequent patches. + +These values can be found in Table A-263 ("MIDR_EL1 bit descriptions") +in issue 07 of the Cortex-X3 TRM, which can be found at: + + https://developer.arm.com/documentation/101593/0102/?lang=en + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-2-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 7b32b99023a21..72fe207403c83 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -86,6 +86,7 @@ + #define ARM_CPU_PART_CORTEX_X2 0xD48 + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B ++#define ARM_CPU_PART_CORTEX_X3 0xD4E + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 +@@ -162,6 +163,7 @@ + #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) ++#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) +-- +2.43.0 + diff --git a/queue-6.6/arm64-cputype-add-cortex-x4-definitions.patch b/queue-6.6/arm64-cputype-add-cortex-x4-definitions.patch new file mode 100644 index 00000000000..ef849fd53ca --- /dev/null +++ b/queue-6.6/arm64-cputype-add-cortex-x4-definitions.patch @@ -0,0 +1,53 @@ +From 5ed9024166b35b6b7e1786f7ff2e00c8446e504c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 10:57:35 +0100 +Subject: arm64: cputype: Add Cortex-X4 definitions + +From: Mark Rutland + +[ Upstream commit 02a0a04676fa7796d9cbc9eb5ca120aaa194d2dd ] + +Add cputype definitions for Cortex-X4. These will be used for errata +detection in subsequent patches. + +These values can be found in Table B-249 ("MIDR_EL1 bit descriptions") +in issue 0002-05 of the Cortex-X4 TRM, which can be found at: + + https://developer.arm.com/documentation/102484/0002/?lang=en + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240508081400.235362-3-mark.rutland@arm.com +Signed-off-by: Will Deacon +[ Mark: fix conflict (dealt with upstream via a later merge) ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 936389e9aecbc..b810b1f03746c 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -87,6 +87,7 @@ + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F ++#define ARM_CPU_PART_CORTEX_X4 0xD82 + + #define APM_CPU_PART_XGENE 0x000 + #define APM_CPU_VAR_POTENZA 0x00 +@@ -161,6 +162,7 @@ + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) ++#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-6.6/arm64-cputype-add-cortex-x925-definitions.patch b/queue-6.6/arm64-cputype-add-cortex-x925-definitions.patch new file mode 100644 index 00000000000..76c12b838f4 --- /dev/null +++ b/queue-6.6/arm64-cputype-add-cortex-x925-definitions.patch @@ -0,0 +1,52 @@ +From 24026620e5f79c2bfcbc16be51df347603a62565 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 10:57:40 +0100 +Subject: arm64: cputype: Add Cortex-X925 definitions + +From: Mark Rutland + +[ Upstream commit fd2ff5f0b320f418288e7a1f919f648fbc8a0dfc ] + +Add cputype definitions for Cortex-X925. These will be used for errata +detection in subsequent patches. + +These values can be found in Table A-285 ("MIDR_EL1 bit descriptions") +in issue 0001-05 of the Cortex-X925 TRM, which can be found at: + + https://developer.arm.com/documentation/102807/0001/?lang=en + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-4-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index dcbac1ce6c25c..1cb0704c6163f 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -91,6 +91,7 @@ + #define ARM_CPU_PART_CORTEX_A720 0xD81 + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 ++#define ARM_CPU_PART_CORTEX_X925 0xD85 + + #define APM_CPU_PART_XGENE 0x000 + #define APM_CPU_VAR_POTENZA 0x00 +@@ -169,6 +170,7 @@ + #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) ++#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-6.6/arm64-cputype-add-neoverse-v3-definitions.patch b/queue-6.6/arm64-cputype-add-neoverse-v3-definitions.patch new file mode 100644 index 00000000000..c548862bb90 --- /dev/null +++ b/queue-6.6/arm64-cputype-add-neoverse-v3-definitions.patch @@ -0,0 +1,53 @@ +From 8a661795f98629eaf5b4025c66c02671c5c40b02 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 10:57:36 +0100 +Subject: arm64: cputype: Add Neoverse-V3 definitions + +From: Mark Rutland + +[ Upstream commit 0ce85db6c2141b7ffb95709d76fc55a27ff3cdc1 ] + +Add cputype definitions for Neoverse-V3. These will be used for errata +detection in subsequent patches. + +These values can be found in Table B-249 ("MIDR_EL1 bit descriptions") +in issue 0001-04 of the Neoverse-V3 TRM, which can be found at: + + https://developer.arm.com/documentation/107734/0001/?lang=en + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240508081400.235362-4-mark.rutland@arm.com +Signed-off-by: Will Deacon +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index b810b1f03746c..7b32b99023a21 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -88,6 +88,7 @@ + #define ARM_CPU_PART_CORTEX_A78C 0xD4B + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F + #define ARM_CPU_PART_CORTEX_X4 0xD82 ++#define ARM_CPU_PART_NEOVERSE_V3 0xD84 + + #define APM_CPU_PART_XGENE 0x000 + #define APM_CPU_VAR_POTENZA 0x00 +@@ -163,6 +164,7 @@ + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) ++#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-6.6/arm64-errata-add-workaround-for-arm-errata-3194386-a.patch b/queue-6.6/arm64-errata-add-workaround-for-arm-errata-3194386-a.patch new file mode 100644 index 00000000000..ba91e875582 --- /dev/null +++ b/queue-6.6/arm64-errata-add-workaround-for-arm-errata-3194386-a.patch @@ -0,0 +1,223 @@ +From 2980953173061e8cb9eb72bcbcbcf00024803ae8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 10:57:37 +0100 +Subject: arm64: errata: Add workaround for Arm errata 3194386 and 3312417 + +From: Mark Rutland + +[ Upstream commit 7187bb7d0b5c7dfa18ca82e9e5c75e13861b1d88 ] + +Cortex-X4 and Neoverse-V3 suffer from errata whereby an MSR to the SSBS +special-purpose register does not affect subsequent speculative +instructions, permitting speculative store bypassing for a window of +time. This is described in their Software Developer Errata Notice (SDEN) +documents: + +* Cortex-X4 SDEN v8.0, erratum 3194386: + https://developer.arm.com/documentation/SDEN-2432808/0800/ + +* Neoverse-V3 SDEN v6.0, erratum 3312417: + https://developer.arm.com/documentation/SDEN-2891958/0600/ + +To workaround these errata, it is necessary to place a speculation +barrier (SB) after MSR to the SSBS special-purpose register. This patch +adds the requisite SB after writes to SSBS within the kernel, and hides +the presence of SSBS from EL0 such that userspace software which cares +about SSBS will manipulate this via prctl(PR_GET_SPECULATION_CTRL, ...). + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240508081400.235362-5-mark.rutland@arm.com +Signed-off-by: Will Deacon +[ Mark: fix conflicts, drop unneeded cpucaps.h, fold in user_feature_fixup() ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arch/arm64/silicon-errata.rst | 4 ++ + arch/arm64/Kconfig | 42 +++++++++++++++++++++ + arch/arm64/kernel/cpu_errata.c | 19 ++++++++++ + arch/arm64/kernel/cpufeature.c | 12 ++++++ + arch/arm64/kernel/proton-pack.c | 12 ++++++ + arch/arm64/tools/cpucaps | 1 + + 6 files changed, 90 insertions(+) + +diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst +index 29fd5213eeb2b..f8e49ff9ab0d4 100644 +--- a/Documentation/arch/arm64/silicon-errata.rst ++++ b/Documentation/arch/arm64/silicon-errata.rst +@@ -133,6 +133,8 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1349291 | N/A | +@@ -145,6 +147,8 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3312417 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | MMU-500 | #841119,826419 | N/A | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | MMU-600 | #1076982,1209401| N/A | +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index f9777ce2ccb2d..db5560300df84 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -1068,6 +1068,48 @@ config ARM64_ERRATUM_3117295 + + If unsure, say Y. + ++config ARM64_WORKAROUND_SPECULATIVE_SSBS ++ bool ++ ++config ARM64_ERRATUM_3194386 ++ bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing" ++ select ARM64_WORKAROUND_SPECULATIVE_SSBS ++ default y ++ help ++ This option adds the workaround for ARM Cortex-X4 erratum 3194386. ++ ++ On affected cores "MSR SSBS, #0" instructions may not affect ++ subsequent speculative instructions, which may permit unexepected ++ speculative store bypassing. ++ ++ Work around this problem by placing a speculation barrier after ++ kernel changes to SSBS. The presence of the SSBS special-purpose ++ register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such ++ that userspace will use the PR_SPEC_STORE_BYPASS prctl to change ++ SSBS. ++ ++ If unsure, say Y. ++ ++config ARM64_ERRATUM_3312417 ++ bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing" ++ select ARM64_WORKAROUND_SPECULATIVE_SSBS ++ default y ++ help ++ This option adds the workaround for ARM Neoverse-V3 erratum 3312417. ++ ++ On affected cores "MSR SSBS, #0" instructions may not affect ++ subsequent speculative instructions, which may permit unexepected ++ speculative store bypassing. ++ ++ Work around this problem by placing a speculation barrier after ++ kernel changes to SSBS. The presence of the SSBS special-purpose ++ register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such ++ that userspace will use the PR_SPEC_STORE_BYPASS prctl to change ++ SSBS. ++ ++ If unsure, say Y. ++ ++ + config CAVIUM_ERRATUM_22375 + bool "Cavium erratum 22375, 24313" + default y +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 7bba831f62c33..3e1554a58209b 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -448,6 +448,18 @@ static const struct midr_range erratum_spec_unpriv_load_list[] = { + }; + #endif + ++#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS ++static const struct midr_range erratum_spec_ssbs_list[] = { ++#ifdef CONFIG_ARM64_ERRATUM_3194386 ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), ++#endif ++#ifdef CONFIG_ARM64_ERRATUM_3312417 ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), ++#endif ++ {} ++}; ++#endif ++ + const struct arm64_cpu_capabilities arm64_errata[] = { + #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE + { +@@ -746,6 +758,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { + .cpu_enable = cpu_clear_bf16_from_user_emulation, + }, + #endif ++#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS ++ { ++ .desc = "ARM errata 3194386, 3312417", ++ .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, ++ ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list), ++ }, ++#endif + #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD + { + .desc = "ARM errata 2966298, 3117295", +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 444a73c2e6385..7e96604559004 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -2190,6 +2190,17 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) + } + #endif /* CONFIG_ARM64_MTE */ + ++static void user_feature_fixup(void) ++{ ++ if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { ++ struct arm64_ftr_reg *regp; ++ ++ regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); ++ if (regp) ++ regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; ++ } ++} ++ + static void elf_hwcap_fixup(void) + { + #ifdef CONFIG_ARM64_ERRATUM_1742098 +@@ -3345,6 +3356,7 @@ void __init setup_cpu_features(void) + u32 cwg; + + setup_system_capabilities(); ++ user_feature_fixup(); + setup_elf_hwcaps(arm64_elf_hwcaps); + + if (system_supports_32bit_el0()) { +diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c +index 05f40c4e18fda..e662c4d2856b6 100644 +--- a/arch/arm64/kernel/proton-pack.c ++++ b/arch/arm64/kernel/proton-pack.c +@@ -558,6 +558,18 @@ static enum mitigation_state spectre_v4_enable_hw_mitigation(void) + + /* SCTLR_EL1.DSSBS was initialised to 0 during boot */ + set_pstate_ssbs(0); ++ ++ /* ++ * SSBS is self-synchronizing and is intended to affect subsequent ++ * speculative instructions, but some CPUs can speculate with a stale ++ * value of SSBS. ++ * ++ * Mitigate this with an unconditional speculation barrier, as CPUs ++ * could mis-speculate branches and bypass a conditional barrier. ++ */ ++ if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS)) ++ spec_bar(); ++ + return SPECTRE_MITIGATED; + } + +diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps +index 5511bee15603a..c251ef3caae56 100644 +--- a/arch/arm64/tools/cpucaps ++++ b/arch/arm64/tools/cpucaps +@@ -99,4 +99,5 @@ WORKAROUND_NVIDIA_CARMEL_CNP + WORKAROUND_QCOM_FALKOR_E1003 + WORKAROUND_REPEAT_TLBI + WORKAROUND_SPECULATIVE_AT ++WORKAROUND_SPECULATIVE_SSBS + WORKAROUND_SPECULATIVE_UNPRIV_LOAD +-- +2.43.0 + diff --git a/queue-6.6/arm64-errata-expand-speculative-ssbs-workaround-agai.patch b/queue-6.6/arm64-errata-expand-speculative-ssbs-workaround-agai.patch new file mode 100644 index 00000000000..8ee753485f7 --- /dev/null +++ b/queue-6.6/arm64-errata-expand-speculative-ssbs-workaround-agai.patch @@ -0,0 +1,219 @@ +From 18a48c332f950e1f0097bc1dbc030e0da21434fc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 10:57:45 +0100 +Subject: arm64: errata: Expand speculative SSBS workaround (again) + +From: Mark Rutland + +[ Upstream commit b0672bbe133ebb6f7be21fce1d742d52f25bcdc7 ] + +A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS +special-purpose register does not affect subsequent speculative +instructions, permitting speculative store bypassing for a window of +time. + +We worked around this for a number of CPUs in commits: + +* 7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") +* 75b3c43eab594bfb ("arm64: errata: Expand speculative SSBS workaround") + +Since then, similar errata have been published for a number of other Arm +Ltd CPUs, for which the same mitigation is sufficient. This is described +in their respective Software Developer Errata Notice (SDEN) documents: + +* Cortex-A76 (MP052) SDEN v31.0, erratum 3324349 + https://developer.arm.com/documentation/SDEN-885749/3100/ + +* Cortex-A77 (MP074) SDEN v19.0, erratum 3324348 + https://developer.arm.com/documentation/SDEN-1152370/1900/ + +* Cortex-A78 (MP102) SDEN v21.0, erratum 3324344 + https://developer.arm.com/documentation/SDEN-1401784/2100/ + +* Cortex-A78C (MP138) SDEN v16.0, erratum 3324346 + https://developer.arm.com/documentation/SDEN-1707916/1600/ + +* Cortex-A78C (MP154) SDEN v10.0, erratum 3324347 + https://developer.arm.com/documentation/SDEN-2004089/1000/ + +* Cortex-A725 (MP190) SDEN v5.0, erratum 3456106 + https://developer.arm.com/documentation/SDEN-2832921/0500/ + +* Cortex-X1 (MP077) SDEN v21.0, erratum 3324344 + https://developer.arm.com/documentation/SDEN-1401782/2100/ + +* Cortex-X1C (MP136) SDEN v16.0, erratum 3324346 + https://developer.arm.com/documentation/SDEN-1707914/1600/ + +* Neoverse-N1 (MP050) SDEN v32.0, erratum 3324349 + https://developer.arm.com/documentation/SDEN-885747/3200/ + +* Neoverse-V1 (MP076) SDEN v19.0, erratum 3324341 + https://developer.arm.com/documentation/SDEN-1401781/1900/ + +Note that due to the manner in which Arm develops IP and tracks errata, +some CPUs share a common erratum number and some CPUs have multiple +erratum numbers for the same HW issue. + +On parts without SB, it is necessary to use ISB for the workaround. The +spec_bar() macro used in the mitigation will expand to a "DSB SY; ISB" +sequence in this case, which is sufficient on all affected parts. + +Enable the existing mitigation by adding the relevant MIDRs to +erratum_spec_ssbs_list. The list is sorted alphanumerically (involving +moving Neoverse-V3 after Neoverse-V2) so that this is easy to audit and +potentially extend again in future. The Kconfig text is also updated to +clarify the set of affected parts and the mitigation. + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Reviewed-by: Anshuman Khandual +Acked-by: Will Deacon +Link: https://lore.kernel.org/r/20240801101803.1982459-4-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: fix conflicts in silicon-errata.rst ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arch/arm64/silicon-errata.rst | 18 +++++++++++++++++ + arch/arm64/Kconfig | 22 +++++++++++++++------ + arch/arm64/kernel/cpu_errata.c | 11 ++++++++++- + 3 files changed, 44 insertions(+), 7 deletions(-) + +diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst +index 0bab767f6887c..357d6cb98161f 100644 +--- a/Documentation/arch/arm64/silicon-errata.rst ++++ b/Documentation/arch/arm64/silicon-errata.rst +@@ -119,8 +119,16 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A76 | #3324349 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A77 | #3324348 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A78 | #3324344 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A78C | #3324346,3324347| ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 | +@@ -133,6 +141,12 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X1C | #3324346 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 | +@@ -151,6 +165,8 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Neoverse-N1 | #3324349 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 | +@@ -159,6 +175,8 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index e80812a4002bb..9e0c1ac3d13ee 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -1069,18 +1069,28 @@ config ARM64_ERRATUM_3117295 + If unsure, say Y. + + config ARM64_ERRATUM_3194386 +- bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" ++ bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" + default y + help + This option adds the workaround for the following errata: + ++ * ARM Cortex-A76 erratum 3324349 ++ * ARM Cortex-A77 erratum 3324348 ++ * ARM Cortex-A78 erratum 3324344 ++ * ARM Cortex-A78C erratum 3324346 ++ * ARM Cortex-A78C erratum 3324347 + * ARM Cortex-A710 erratam 3324338 + * ARM Cortex-A720 erratum 3456091 ++ * ARM Cortex-A725 erratum 3456106 ++ * ARM Cortex-X1 erratum 3324344 ++ * ARM Cortex-X1C erratum 3324346 + * ARM Cortex-X2 erratum 3324338 + * ARM Cortex-X3 erratum 3324335 + * ARM Cortex-X4 erratum 3194386 + * ARM Cortex-X925 erratum 3324334 ++ * ARM Neoverse-N1 erratum 3324349 + * ARM Neoverse N2 erratum 3324339 ++ * ARM Neoverse-V1 erratum 3324341 + * ARM Neoverse V2 erratum 3324336 + * ARM Neoverse-V3 erratum 3312417 + +@@ -1088,11 +1098,11 @@ config ARM64_ERRATUM_3194386 + subsequent speculative instructions, which may permit unexepected + speculative store bypassing. + +- Work around this problem by placing a speculation barrier after +- kernel changes to SSBS. The presence of the SSBS special-purpose +- register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such +- that userspace will use the PR_SPEC_STORE_BYPASS prctl to change +- SSBS. ++ Work around this problem by placing a Speculation Barrier (SB) or ++ Instruction Synchronization Barrier (ISB) after kernel changes to ++ SSBS. The presence of the SSBS special-purpose register is hidden ++ from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace ++ will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. + + If unsure, say Y. + +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index bfe324854e3b5..57b1d6a68256b 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -450,15 +450,24 @@ static const struct midr_range erratum_spec_unpriv_load_list[] = { + + #ifdef CONFIG_ARM64_ERRATUM_3194386 + static const struct midr_range erratum_spec_ssbs_list[] = { ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), +- MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), + {} + }; + #endif +-- +2.43.0 + diff --git a/queue-6.6/arm64-errata-expand-speculative-ssbs-workaround.patch b/queue-6.6/arm64-errata-expand-speculative-ssbs-workaround.patch new file mode 100644 index 00000000000..2036d7d6851 --- /dev/null +++ b/queue-6.6/arm64-errata-expand-speculative-ssbs-workaround.patch @@ -0,0 +1,173 @@ +From 3512e8a49ca53de1565d2036b49a458a9cba95e9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 10:57:42 +0100 +Subject: arm64: errata: Expand speculative SSBS workaround + +From: Mark Rutland + +[ Upstream commit 75b3c43eab594bfbd8184ec8ee1a6b820950819a ] + +A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS +special-purpose register does not affect subsequent speculative +instructions, permitting speculative store bypassing for a window of +time. + +We worked around this for Cortex-X4 and Neoverse-V3, in commit: + + 7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") + +... as per their Software Developer Errata Notice (SDEN) documents: + +* Cortex-X4 SDEN v8.0, erratum 3194386: + https://developer.arm.com/documentation/SDEN-2432808/0800/ + +* Neoverse-V3 SDEN v6.0, erratum 3312417: + https://developer.arm.com/documentation/SDEN-2891958/0600/ + +Since then, similar errata have been published for a number of other Arm Ltd +CPUs, for which the mitigation is the same. This is described in their +respective SDEN documents: + +* Cortex-A710 SDEN v19.0, errataum 3324338 + https://developer.arm.com/documentation/SDEN-1775101/1900/?lang=en + +* Cortex-A720 SDEN v11.0, erratum 3456091 + https://developer.arm.com/documentation/SDEN-2439421/1100/?lang=en + +* Cortex-X2 SDEN v19.0, erratum 3324338 + https://developer.arm.com/documentation/SDEN-1775100/1900/?lang=en + +* Cortex-X3 SDEN v14.0, erratum 3324335 + https://developer.arm.com/documentation/SDEN-2055130/1400/?lang=en + +* Cortex-X925 SDEN v8.0, erratum 3324334 + https://developer.arm.com/documentation/109108/800/?lang=en + +* Neoverse-N2 SDEN v17.0, erratum 3324339 + https://developer.arm.com/documentation/SDEN-1982442/1700/?lang=en + +* Neoverse-V2 SDEN v9.0, erratum 3324336 + https://developer.arm.com/documentation/SDEN-2332927/900/?lang=en + +Note that due to shared design lineage, some CPUs share the same erratum +number. + +Add these to the existing mitigation under CONFIG_ARM64_ERRATUM_3194386. +As listing all of the erratum IDs in the runtime description would be +unwieldy, this is reduced to: + + "SSBS not fully self-synchronizing" + +... matching the description of the errata in all of the SDENs. + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-6-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: fix conflicts in silicon-errata.rst ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arch/arm64/silicon-errata.rst | 14 ++++++++++++++ + arch/arm64/Kconfig | 9 ++++++++- + arch/arm64/kernel/cpu_errata.c | 9 ++++++++- + 3 files changed, 30 insertions(+), 2 deletions(-) + +diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst +index e7fc5e1664265..0bab767f6887c 100644 +--- a/Documentation/arch/arm64/silicon-errata.rst ++++ b/Documentation/arch/arm64/silicon-errata.rst +@@ -127,14 +127,24 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A710 | #3324338 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X2 | #3324338 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X3 | #3324335 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X925 | #3324334 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1349291 | N/A | +@@ -147,6 +157,10 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | MMU-500 | #841119,826419 | N/A | +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index d9d84f716228b..e80812a4002bb 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -1069,12 +1069,19 @@ config ARM64_ERRATUM_3117295 + If unsure, say Y. + + config ARM64_ERRATUM_3194386 +- bool "Cortex-X4/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" ++ bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" + default y + help + This option adds the workaround for the following errata: + ++ * ARM Cortex-A710 erratam 3324338 ++ * ARM Cortex-A720 erratum 3456091 ++ * ARM Cortex-X2 erratum 3324338 ++ * ARM Cortex-X3 erratum 3324335 + * ARM Cortex-X4 erratum 3194386 ++ * ARM Cortex-X925 erratum 3324334 ++ * ARM Neoverse N2 erratum 3324339 ++ * ARM Neoverse V2 erratum 3324336 + * ARM Neoverse-V3 erratum 3312417 + + On affected cores "MSR SSBS, #0" instructions may not affect +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 36d3f894f8637..bfe324854e3b5 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -450,8 +450,15 @@ static const struct midr_range erratum_spec_unpriv_load_list[] = { + + #ifdef CONFIG_ARM64_ERRATUM_3194386 + static const struct midr_range erratum_spec_ssbs_list[] = { ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), + {} + }; + #endif +@@ -756,7 +763,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { + #endif + #ifdef CONFIG_ARM64_ERRATUM_3194386 + { +- .desc = "ARM errata 3194386, 3312417", ++ .desc = "SSBS not fully self-synchronizing", + .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, + ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list), + }, +-- +2.43.0 + diff --git a/queue-6.6/arm64-errata-unify-speculative-ssbs-errata-logic.patch b/queue-6.6/arm64-errata-unify-speculative-ssbs-errata-logic.patch new file mode 100644 index 00000000000..5ebf3f595c4 --- /dev/null +++ b/queue-6.6/arm64-errata-unify-speculative-ssbs-errata-logic.patch @@ -0,0 +1,149 @@ +From d3a6784bc577c4429dd2bbcc3383c1e11a10caad Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 10:57:41 +0100 +Subject: arm64: errata: Unify speculative SSBS errata logic + +From: Mark Rutland + +[ Upstream commit ec768766608092087dfb5c1fc45a16a6f524dee2 ] + +Cortex-X4 erratum 3194386 and Neoverse-V3 erratum 3312417 are identical, +with duplicate Kconfig text and some unsightly ifdeffery. While we try +to share code behind CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS, having +separate options results in a fair amount of boilerplate code, and this +will only get worse as we expand the set of affected CPUs. + +To reduce this boilerplate, unify the two behind a common Kconfig +option. This removes the duplicate text and Kconfig logic, and removes +the need for the intermediate ARM64_WORKAROUND_SPECULATIVE_SSBS option. +The set of affected CPUs is described as a list so that this can easily +be extended. + +I've used ARM64_ERRATUM_3194386 (matching the Neoverse-V3 erratum ID) as +the common option, matching the way we use ARM64_ERRATUM_1319367 to +cover Cortex-A57 erratum 1319537 and Cortex-A72 erratum 1319367. + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-5-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: fix conflicts, drop unneeded cpucaps.h ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arch/arm64/silicon-errata.rst | 2 +- + arch/arm64/Kconfig | 29 +++------------------ + arch/arm64/kernel/cpu_errata.c | 8 ++---- + arch/arm64/kernel/proton-pack.c | 2 +- + 4 files changed, 8 insertions(+), 33 deletions(-) + +diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst +index f8e49ff9ab0d4..e7fc5e1664265 100644 +--- a/Documentation/arch/arm64/silicon-errata.rst ++++ b/Documentation/arch/arm64/silicon-errata.rst +@@ -147,7 +147,7 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 | + +----------------+-----------------+-----------------+-----------------------------+ +-| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3312417 | ++| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | MMU-500 | #841119,826419 | N/A | + +----------------+-----------------+-----------------+-----------------------------+ +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index db5560300df84..d9d84f716228b 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -1068,34 +1068,14 @@ config ARM64_ERRATUM_3117295 + + If unsure, say Y. + +-config ARM64_WORKAROUND_SPECULATIVE_SSBS +- bool +- + config ARM64_ERRATUM_3194386 +- bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing" +- select ARM64_WORKAROUND_SPECULATIVE_SSBS ++ bool "Cortex-X4/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" + default y + help +- This option adds the workaround for ARM Cortex-X4 erratum 3194386. ++ This option adds the workaround for the following errata: + +- On affected cores "MSR SSBS, #0" instructions may not affect +- subsequent speculative instructions, which may permit unexepected +- speculative store bypassing. +- +- Work around this problem by placing a speculation barrier after +- kernel changes to SSBS. The presence of the SSBS special-purpose +- register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such +- that userspace will use the PR_SPEC_STORE_BYPASS prctl to change +- SSBS. +- +- If unsure, say Y. +- +-config ARM64_ERRATUM_3312417 +- bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing" +- select ARM64_WORKAROUND_SPECULATIVE_SSBS +- default y +- help +- This option adds the workaround for ARM Neoverse-V3 erratum 3312417. ++ * ARM Cortex-X4 erratum 3194386 ++ * ARM Neoverse-V3 erratum 3312417 + + On affected cores "MSR SSBS, #0" instructions may not affect + subsequent speculative instructions, which may permit unexepected +@@ -1109,7 +1089,6 @@ config ARM64_ERRATUM_3312417 + + If unsure, say Y. + +- + config CAVIUM_ERRATUM_22375 + bool "Cavium erratum 22375, 24313" + default y +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 3e1554a58209b..36d3f894f8637 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -448,14 +448,10 @@ static const struct midr_range erratum_spec_unpriv_load_list[] = { + }; + #endif + +-#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS +-static const struct midr_range erratum_spec_ssbs_list[] = { + #ifdef CONFIG_ARM64_ERRATUM_3194386 ++static const struct midr_range erratum_spec_ssbs_list[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), +-#endif +-#ifdef CONFIG_ARM64_ERRATUM_3312417 + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), +-#endif + {} + }; + #endif +@@ -758,7 +754,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { + .cpu_enable = cpu_clear_bf16_from_user_emulation, + }, + #endif +-#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS ++#ifdef CONFIG_ARM64_ERRATUM_3194386 + { + .desc = "ARM errata 3194386, 3312417", + .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, +diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c +index e662c4d2856b6..57503dc4b22fa 100644 +--- a/arch/arm64/kernel/proton-pack.c ++++ b/arch/arm64/kernel/proton-pack.c +@@ -567,7 +567,7 @@ static enum mitigation_state spectre_v4_enable_hw_mitigation(void) + * Mitigate this with an unconditional speculation barrier, as CPUs + * could mis-speculate branches and bypass a conditional barrier. + */ +- if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS)) ++ if (IS_ENABLED(CONFIG_ARM64_ERRATUM_3194386)) + spec_bar(); + + return SPECTRE_MITIGATED; +-- +2.43.0 + diff --git a/queue-6.6/asoc-codecs-wcd938x-sdw-correct-soundwire-ports-mask.patch b/queue-6.6/asoc-codecs-wcd938x-sdw-correct-soundwire-ports-mask.patch new file mode 100644 index 00000000000..cebf188ccaa --- /dev/null +++ b/queue-6.6/asoc-codecs-wcd938x-sdw-correct-soundwire-ports-mask.patch @@ -0,0 +1,51 @@ +From 7dc73a90500055c028a2b74b20e073fa3a8ca6f3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Jul 2024 16:10:42 +0200 +Subject: ASoC: codecs: wcd938x-sdw: Correct Soundwire ports mask + +From: Krzysztof Kozlowski + +[ Upstream commit 3f6fb03dae9c7dfba7670858d29e03c8faaa89fe ] + +Device has up to WCD938X_MAX_SWR_PORTS number of ports and the array +assigned to prop.src_dpn_prop and prop.sink_dpn_prop has +0..WCD938X_MAX_SWR_PORTS-1 elements. On the other hand, GENMASK(high, +low) creates an inclusive mask between , so we need the mask +from 0 up to WCD938X_MAX_SWR_PORTS-1. + +Theoretically, too wide mask could cause an out of bounds read in +sdw_get_slave_dpn_prop() in stream.c, however only in the case of buggy +driver, e.g. adding incorrect number of ports via +sdw_stream_add_slave(). + +Fixes: 16572522aece ("ASoC: codecs: wcd938x-sdw: add SoundWire driver") +Signed-off-by: Krzysztof Kozlowski +Link: https://patch.msgid.link/20240726-asoc-wcd-wsa-swr-ports-genmask-v1-2-d4d7a8b56f05@linaro.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/wcd938x-sdw.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/codecs/wcd938x-sdw.c b/sound/soc/codecs/wcd938x-sdw.c +index a1f04010da95f..132c1d24f8f6e 100644 +--- a/sound/soc/codecs/wcd938x-sdw.c ++++ b/sound/soc/codecs/wcd938x-sdw.c +@@ -1252,12 +1252,12 @@ static int wcd9380_probe(struct sdw_slave *pdev, + pdev->prop.lane_control_support = true; + pdev->prop.simple_clk_stop_capable = true; + if (wcd->is_tx) { +- pdev->prop.source_ports = GENMASK(WCD938X_MAX_SWR_PORTS, 0); ++ pdev->prop.source_ports = GENMASK(WCD938X_MAX_SWR_PORTS - 1, 0); + pdev->prop.src_dpn_prop = wcd938x_dpn_prop; + wcd->ch_info = &wcd938x_sdw_tx_ch_info[0]; + pdev->prop.wake_capable = true; + } else { +- pdev->prop.sink_ports = GENMASK(WCD938X_MAX_SWR_PORTS, 0); ++ pdev->prop.sink_ports = GENMASK(WCD938X_MAX_SWR_PORTS - 1, 0); + pdev->prop.sink_dpn_prop = wcd938x_dpn_prop; + wcd->ch_info = &wcd938x_sdw_rx_ch_info[0]; + } +-- +2.43.0 + diff --git a/queue-6.6/asoc-codecs-wsa881x-correct-soundwire-ports-mask.patch b/queue-6.6/asoc-codecs-wsa881x-correct-soundwire-ports-mask.patch new file mode 100644 index 00000000000..ac3b82e1186 --- /dev/null +++ b/queue-6.6/asoc-codecs-wsa881x-correct-soundwire-ports-mask.patch @@ -0,0 +1,44 @@ +From a6759b38a3fe5ee8f6a91943314932de39c7a29b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Jul 2024 16:10:44 +0200 +Subject: ASoC: codecs: wsa881x: Correct Soundwire ports mask + +From: Krzysztof Kozlowski + +[ Upstream commit eb11c3bb64ad0a05aeacdb01039863aa2aa3614b ] + +Device has up to WSA881X_MAX_SWR_PORTS number of ports and the array +assigned to prop.sink_dpn_prop has 0..WSA881X_MAX_SWR_PORTS-1 elements. +On the other hand, GENMASK(high, low) creates an inclusive mask between +, so we need the mask from 0 up to WSA881X_MAX_SWR_PORTS-1. + +Theoretically, too wide mask could cause an out of bounds read in +sdw_get_slave_dpn_prop() in stream.c, however only in the case of buggy +driver, e.g. adding incorrect number of ports via +sdw_stream_add_slave(). + +Fixes: a0aab9e1404a ("ASoC: codecs: add wsa881x amplifier support") +Signed-off-by: Krzysztof Kozlowski +Link: https://patch.msgid.link/20240726-asoc-wcd-wsa-swr-ports-genmask-v1-4-d4d7a8b56f05@linaro.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/wsa881x.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/codecs/wsa881x.c b/sound/soc/codecs/wsa881x.c +index 1253695bebd86..53b828f681020 100644 +--- a/sound/soc/codecs/wsa881x.c ++++ b/sound/soc/codecs/wsa881x.c +@@ -1152,7 +1152,7 @@ static int wsa881x_probe(struct sdw_slave *pdev, + wsa881x->sconfig.frame_rate = 48000; + wsa881x->sconfig.direction = SDW_DATA_DIR_RX; + wsa881x->sconfig.type = SDW_STREAM_PDM; +- pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS, 0); ++ pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS - 1, 0); + pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop; + pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; + pdev->prop.clk_stop_mode1 = true; +-- +2.43.0 + diff --git a/queue-6.6/asoc-codecs-wsa883x-correct-soundwire-ports-mask.patch b/queue-6.6/asoc-codecs-wsa883x-correct-soundwire-ports-mask.patch new file mode 100644 index 00000000000..44895a506b1 --- /dev/null +++ b/queue-6.6/asoc-codecs-wsa883x-correct-soundwire-ports-mask.patch @@ -0,0 +1,44 @@ +From 4219bb777119c4eda0ff03993ca50cd001cd3550 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Jul 2024 16:10:45 +0200 +Subject: ASoC: codecs: wsa883x: Correct Soundwire ports mask + +From: Krzysztof Kozlowski + +[ Upstream commit 6801ac36f25690e14955f7f9eace1eaa29edbdd0 ] + +Device has up to WSA883X_MAX_SWR_PORTS number of ports and the array +assigned to prop.sink_dpn_prop has 0..WSA883X_MAX_SWR_PORTS-1 elements. +On the other hand, GENMASK(high, low) creates an inclusive mask between +, so we need the mask from 0 up to WSA883X_MAX_SWR_PORTS-1. + +Theoretically, too wide mask could cause an out of bounds read in +sdw_get_slave_dpn_prop() in stream.c, however only in the case of buggy +driver, e.g. adding incorrect number of ports via +sdw_stream_add_slave(). + +Fixes: 43b8c7dc85a1 ("ASoC: codecs: add wsa883x amplifier support") +Signed-off-by: Krzysztof Kozlowski +Link: https://patch.msgid.link/20240726-asoc-wcd-wsa-swr-ports-genmask-v1-5-d4d7a8b56f05@linaro.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/wsa883x.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/codecs/wsa883x.c b/sound/soc/codecs/wsa883x.c +index 5443a5c4100c0..2169d93989841 100644 +--- a/sound/soc/codecs/wsa883x.c ++++ b/sound/soc/codecs/wsa883x.c +@@ -1407,7 +1407,7 @@ static int wsa883x_probe(struct sdw_slave *pdev, + WSA883X_MAX_SWR_PORTS)) + dev_dbg(dev, "Static Port mapping not specified\n"); + +- pdev->prop.sink_ports = GENMASK(WSA883X_MAX_SWR_PORTS, 0); ++ pdev->prop.sink_ports = GENMASK(WSA883X_MAX_SWR_PORTS - 1, 0); + pdev->prop.simple_clk_stop_capable = true; + pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop; + pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; +-- +2.43.0 + diff --git a/queue-6.6/asoc-codecs-wsa883x-parse-port-mapping-information.patch b/queue-6.6/asoc-codecs-wsa883x-parse-port-mapping-information.patch new file mode 100644 index 00000000000..7f7b49e6dc2 --- /dev/null +++ b/queue-6.6/asoc-codecs-wsa883x-parse-port-mapping-information.patch @@ -0,0 +1,46 @@ +From d5b5f137df5976c59d323be7b7747fe283ea5524 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 27 Jun 2024 15:44:39 +0100 +Subject: ASoC: codecs: wsa883x: parse port-mapping information + +From: Srinivas Kandagatla + +[ Upstream commit 1cf3295bd108abbd7f128071ae9775fd18394ca9 ] + +Add support to parse static master port map information from device tree. + +Reviewed-by: Krzysztof Kozlowski +Tested-by: Krzysztof Kozlowski +Tested-by: Neil Armstrong # on SM8650-HDK +Signed-off-by: Srinivas Kandagatla +Reviewed-by: Dmitry Baryshkov +Link: https://patch.msgid.link/20240626-port-map-v2-2-6cc1c5608cdd@linaro.org +Signed-off-by: Mark Brown +Stable-dep-of: 6801ac36f256 ("ASoC: codecs: wsa883x: Correct Soundwire ports mask") +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/wsa883x.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/sound/soc/codecs/wsa883x.c b/sound/soc/codecs/wsa883x.c +index a2e86ef7d18f5..5443a5c4100c0 100644 +--- a/sound/soc/codecs/wsa883x.c ++++ b/sound/soc/codecs/wsa883x.c +@@ -1399,6 +1399,14 @@ static int wsa883x_probe(struct sdw_slave *pdev, + wsa883x->sconfig.direction = SDW_DATA_DIR_RX; + wsa883x->sconfig.type = SDW_STREAM_PDM; + ++ /** ++ * Port map index starts with 0, however the data port for this codec ++ * are from index 1 ++ */ ++ if (of_property_read_u32_array(dev->of_node, "qcom,port-mapping", &pdev->m_port_map[1], ++ WSA883X_MAX_SWR_PORTS)) ++ dev_dbg(dev, "Static Port mapping not specified\n"); ++ + pdev->prop.sink_ports = GENMASK(WSA883X_MAX_SWR_PORTS, 0); + pdev->prop.simple_clk_stop_capable = true; + pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop; +-- +2.43.0 + diff --git a/queue-6.6/asoc-codecs-wsa884x-correct-soundwire-ports-mask.patch b/queue-6.6/asoc-codecs-wsa884x-correct-soundwire-ports-mask.patch new file mode 100644 index 00000000000..8883f530177 --- /dev/null +++ b/queue-6.6/asoc-codecs-wsa884x-correct-soundwire-ports-mask.patch @@ -0,0 +1,44 @@ +From 3f02af61b366821448eafd3cd155dbb9f5447ac3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Jul 2024 16:10:46 +0200 +Subject: ASoC: codecs: wsa884x: Correct Soundwire ports mask + +From: Krzysztof Kozlowski + +[ Upstream commit dcb6631d05152930e2ea70fd2abfd811b0e970b5 ] + +Device has up to WSA884X_MAX_SWR_PORTS number of ports and the array +assigned to prop.sink_dpn_prop has 0..WSA884X_MAX_SWR_PORTS-1 elements. +On the other hand, GENMASK(high, low) creates an inclusive mask between +, so we need the mask from 0 up to WSA884X_MAX_SWR_PORTS-1. + +Theoretically, too wide mask could cause an out of bounds read in +sdw_get_slave_dpn_prop() in stream.c, however only in the case of buggy +driver, e.g. adding incorrect number of ports via +sdw_stream_add_slave(). + +Fixes: aa21a7d4f68a ("ASoC: codecs: wsa884x: Add WSA884x family of speakers") +Signed-off-by: Krzysztof Kozlowski +Link: https://patch.msgid.link/20240726-asoc-wcd-wsa-swr-ports-genmask-v1-6-d4d7a8b56f05@linaro.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/wsa884x.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/codecs/wsa884x.c b/sound/soc/codecs/wsa884x.c +index ed8110511a5b1..1cd52fab7b40d 100644 +--- a/sound/soc/codecs/wsa884x.c ++++ b/sound/soc/codecs/wsa884x.c +@@ -1866,7 +1866,7 @@ static int wsa884x_probe(struct sdw_slave *pdev, + WSA884X_MAX_SWR_PORTS)) + dev_dbg(dev, "Static Port mapping not specified\n"); + +- pdev->prop.sink_ports = GENMASK(WSA884X_MAX_SWR_PORTS, 0); ++ pdev->prop.sink_ports = GENMASK(WSA884X_MAX_SWR_PORTS - 1, 0); + pdev->prop.simple_clk_stop_capable = true; + pdev->prop.sink_dpn_prop = wsa884x_sink_dpn_prop; + pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; +-- +2.43.0 + diff --git a/queue-6.6/asoc-codecs-wsa884x-parse-port-mapping-information.patch b/queue-6.6/asoc-codecs-wsa884x-parse-port-mapping-information.patch new file mode 100644 index 00000000000..e1ba5b36fc7 --- /dev/null +++ b/queue-6.6/asoc-codecs-wsa884x-parse-port-mapping-information.patch @@ -0,0 +1,49 @@ +From 4ec5a5110b6b0e8e4ffaee55f52ad35841666205 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 27 Jun 2024 15:44:41 +0100 +Subject: ASoC: codecs: wsa884x: parse port-mapping information + +From: Srinivas Kandagatla + +[ Upstream commit e1bc5c324bcca3acdbe817ccbf9aa7992d89479d ] + +Add support to parse static master port map information from device tree. +This is required for correct port mapping between soundwire device and +master ports. + +Reviewed-by: Krzysztof Kozlowski +Tested-by: Krzysztof Kozlowski +Reviewed-by: Neil Armstrong +Tested-by: Neil Armstrong # on SM8650-HDK +Signed-off-by: Srinivas Kandagatla +Reviewed-by: Dmitry Baryshkov +Link: https://patch.msgid.link/20240626-port-map-v2-4-6cc1c5608cdd@linaro.org +Signed-off-by: Mark Brown +Stable-dep-of: dcb6631d0515 ("ASoC: codecs: wsa884x: Correct Soundwire ports mask") +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/wsa884x.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/sound/soc/codecs/wsa884x.c b/sound/soc/codecs/wsa884x.c +index 993d76b18b536..ed8110511a5b1 100644 +--- a/sound/soc/codecs/wsa884x.c ++++ b/sound/soc/codecs/wsa884x.c +@@ -1858,6 +1858,14 @@ static int wsa884x_probe(struct sdw_slave *pdev, + wsa884x->sconfig.direction = SDW_DATA_DIR_RX; + wsa884x->sconfig.type = SDW_STREAM_PDM; + ++ /** ++ * Port map index starts with 0, however the data port for this codec ++ * are from index 1 ++ */ ++ if (of_property_read_u32_array(dev->of_node, "qcom,port-mapping", &pdev->m_port_map[1], ++ WSA884X_MAX_SWR_PORTS)) ++ dev_dbg(dev, "Static Port mapping not specified\n"); ++ + pdev->prop.sink_ports = GENMASK(WSA884X_MAX_SWR_PORTS, 0); + pdev->prop.simple_clk_stop_capable = true; + pdev->prop.sink_dpn_prop = wsa884x_sink_dpn_prop; +-- +2.43.0 + diff --git a/queue-6.6/asoc-meson-axg-fifo-fix-irq-scheduling-issue-with-pr.patch b/queue-6.6/asoc-meson-axg-fifo-fix-irq-scheduling-issue-with-pr.patch new file mode 100644 index 00000000000..b14225baf2f --- /dev/null +++ b/queue-6.6/asoc-meson-axg-fifo-fix-irq-scheduling-issue-with-pr.patch @@ -0,0 +1,86 @@ +From b7ae8c2d8813ef90f88eea5bb8ff608d6d640a39 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 7 Aug 2024 18:27:03 +0200 +Subject: ASoC: meson: axg-fifo: fix irq scheduling issue with PREEMPT_RT + +From: Jerome Brunet + +[ Upstream commit 5003d0ce5c7da3a02c0aff771f516f99731e7390 ] + +With PREEMPT_RT enabled a spinlock_t becomes a sleeping lock. + +This is usually not a problem with spinlocks used in IRQ context since +IRQ handlers get threaded. However, if IRQF_ONESHOT is set, the primary +handler won't be force-threaded and runs always in hardirq context. This is +a problem because spinlock_t requires a preemptible context on PREEMPT_RT. + +In this particular instance, regmap mmio uses spinlock_t to protect the +register access and IRQF_ONESHOT is set on the IRQ. In this case, it is +actually better to do everything in threaded handler and it solves the +problem with PREEMPT_RT. + +Reported-by: Arseniy Krasnov +Closes: https://lore.kernel.org/linux-amlogic/20240729131652.3012327-1-avkrasnov@salutedevices.com +Suggested-by: Sebastian Andrzej Siewior +Fixes: b11d26660dff ("ASoC: meson: axg-fifo: use threaded irq to check periods") +Signed-off-by: Jerome Brunet +Reviewed-by: Sebastian Andrzej Siewior +Link: https://patch.msgid.link/20240807162705.4024136-1-jbrunet@baylibre.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/meson/axg-fifo.c | 26 ++++++++++---------------- + 1 file changed, 10 insertions(+), 16 deletions(-) + +diff --git a/sound/soc/meson/axg-fifo.c b/sound/soc/meson/axg-fifo.c +index 94b169a5493b5..5218e40aeb1bb 100644 +--- a/sound/soc/meson/axg-fifo.c ++++ b/sound/soc/meson/axg-fifo.c +@@ -207,25 +207,18 @@ static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id) + status = FIELD_GET(STATUS1_INT_STS, status); + axg_fifo_ack_irq(fifo, status); + +- /* Use the thread to call period elapsed on nonatomic links */ +- if (status & FIFO_INT_COUNT_REPEAT) +- return IRQ_WAKE_THREAD; ++ if (status & ~FIFO_INT_COUNT_REPEAT) ++ dev_dbg(axg_fifo_dev(ss), "unexpected irq - STS 0x%02x\n", ++ status); + +- dev_dbg(axg_fifo_dev(ss), "unexpected irq - STS 0x%02x\n", +- status); ++ if (status & FIFO_INT_COUNT_REPEAT) { ++ snd_pcm_period_elapsed(ss); ++ return IRQ_HANDLED; ++ } + + return IRQ_NONE; + } + +-static irqreturn_t axg_fifo_pcm_irq_block_thread(int irq, void *dev_id) +-{ +- struct snd_pcm_substream *ss = dev_id; +- +- snd_pcm_period_elapsed(ss); +- +- return IRQ_HANDLED; +-} +- + int axg_fifo_pcm_open(struct snd_soc_component *component, + struct snd_pcm_substream *ss) + { +@@ -251,8 +244,9 @@ int axg_fifo_pcm_open(struct snd_soc_component *component, + if (ret) + return ret; + +- ret = request_threaded_irq(fifo->irq, axg_fifo_pcm_irq_block, +- axg_fifo_pcm_irq_block_thread, ++ /* Use the threaded irq handler only with non-atomic links */ ++ ret = request_threaded_irq(fifo->irq, NULL, ++ axg_fifo_pcm_irq_block, + IRQF_ONESHOT, dev_name(dev), ss); + if (ret) + return ret; +-- +2.43.0 + diff --git a/queue-6.6/asoc-sof-remove-libraries-from-topology-lookups.patch b/queue-6.6/asoc-sof-remove-libraries-from-topology-lookups.patch new file mode 100644 index 00000000000..0416fe7665b --- /dev/null +++ b/queue-6.6/asoc-sof-remove-libraries-from-topology-lookups.patch @@ -0,0 +1,42 @@ +From 52ee66a850d4ca773c9f7f5c719f8c0027ecea1c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 31 Jul 2024 14:21:44 -0700 +Subject: ASoC: SOF: Remove libraries from topology lookups + +From: Curtis Malainey + +[ Upstream commit 7354eb7f1558466e92e926802d36e69e42938ea9 ] + +Default firmware shipped in open source are not licensed for 3P +libraries, therefore topologies should not reference them. + +If a OS wants to use 3P (that they have licensed) then they should use +the appropriate topology override mechanisms. + +Fixes: 8a7d5d85ed2161 ("ASoC: SOF: mediatek: mt8195: Add devicetree support to select topologies") +Signed-off-by: Curtis Malainey +Cc: Wojciech Macek +Reviewed-by: AngeloGioacchino Del Regno +Link: https://patch.msgid.link/20240731212153.921327-1-cujomalainey@chromium.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/sof/mediatek/mt8195/mt8195.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/sof/mediatek/mt8195/mt8195.c b/sound/soc/sof/mediatek/mt8195/mt8195.c +index 7d6a568556ea4..b5b4ea854da4b 100644 +--- a/sound/soc/sof/mediatek/mt8195/mt8195.c ++++ b/sound/soc/sof/mediatek/mt8195/mt8195.c +@@ -624,7 +624,7 @@ static struct snd_sof_dsp_ops sof_mt8195_ops = { + static struct snd_sof_of_mach sof_mt8195_machs[] = { + { + .compatible = "google,tomato", +- .sof_tplg_filename = "sof-mt8195-mt6359-rt1019-rt5682-dts.tplg" ++ .sof_tplg_filename = "sof-mt8195-mt6359-rt1019-rt5682.tplg" + }, { + .compatible = "mediatek,mt8195", + .sof_tplg_filename = "sof-mt8195.tplg" +-- +2.43.0 + diff --git a/queue-6.6/asoc-sti-add-missing-probe-entry-for-player-and-read.patch b/queue-6.6/asoc-sti-add-missing-probe-entry-for-player-and-read.patch new file mode 100644 index 00000000000..3d1076f7b02 --- /dev/null +++ b/queue-6.6/asoc-sti-add-missing-probe-entry-for-player-and-read.patch @@ -0,0 +1,85 @@ +From f17555de4ebd9a1125ca0a07b555fad5166a71e5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 27 Jul 2024 15:40:15 +0200 +Subject: ASoC: sti: add missing probe entry for player and reader + +From: Jerome Audu + +[ Upstream commit 6b99068d5ea0aa295f15f30afc98db74d056ec7b ] + +This patch addresses a regression in the ASoC STI drivers that was +introduced in Linux version 6.6.y. The issue originated from a series of +patches (see https://lore.kernel.org/all/87wmy5b0wt.wl-kuninori.morimoto.gx@renesas.com/) +that unintentionally omitted necessary probe functions for the player +and reader components. + +Probe function in `sound/soc/sti/sti_uniperif.c:415` is being replaced +by another probe function located at `sound/soc/sti/sti_uniperif.c:453`, +which should instead be derived from the player and reader components. +This patch correctly reinserts the missing probe entries, +restoring the intended functionality. + +Fixes: 9f625f5e6cf9 ("ASoC: sti: merge DAI call back functions into ops") +Signed-off-by: Jerome Audu +Link: https://patch.msgid.link/20240727-sti-audio-fix-v2-1-208bde546c3f@free.fr +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/sti/sti_uniperif.c | 2 +- + sound/soc/sti/uniperif.h | 1 + + sound/soc/sti/uniperif_player.c | 1 + + sound/soc/sti/uniperif_reader.c | 1 + + 4 files changed, 4 insertions(+), 1 deletion(-) + +diff --git a/sound/soc/sti/sti_uniperif.c b/sound/soc/sti/sti_uniperif.c +index 2c21a86421e66..cc9a8122b9bc2 100644 +--- a/sound/soc/sti/sti_uniperif.c ++++ b/sound/soc/sti/sti_uniperif.c +@@ -352,7 +352,7 @@ static int sti_uniperiph_resume(struct snd_soc_component *component) + return ret; + } + +-static int sti_uniperiph_dai_probe(struct snd_soc_dai *dai) ++int sti_uniperiph_dai_probe(struct snd_soc_dai *dai) + { + struct sti_uniperiph_data *priv = snd_soc_dai_get_drvdata(dai); + struct sti_uniperiph_dai *dai_data = &priv->dai_data; +diff --git a/sound/soc/sti/uniperif.h b/sound/soc/sti/uniperif.h +index 2a5de328501c1..74e51f0ff85c8 100644 +--- a/sound/soc/sti/uniperif.h ++++ b/sound/soc/sti/uniperif.h +@@ -1380,6 +1380,7 @@ int uni_reader_init(struct platform_device *pdev, + struct uniperif *reader); + + /* common */ ++int sti_uniperiph_dai_probe(struct snd_soc_dai *dai); + int sti_uniperiph_dai_set_fmt(struct snd_soc_dai *dai, + unsigned int fmt); + +diff --git a/sound/soc/sti/uniperif_player.c b/sound/soc/sti/uniperif_player.c +index dd9013c476649..6d1ce030963c6 100644 +--- a/sound/soc/sti/uniperif_player.c ++++ b/sound/soc/sti/uniperif_player.c +@@ -1038,6 +1038,7 @@ static const struct snd_soc_dai_ops uni_player_dai_ops = { + .startup = uni_player_startup, + .shutdown = uni_player_shutdown, + .prepare = uni_player_prepare, ++ .probe = sti_uniperiph_dai_probe, + .trigger = uni_player_trigger, + .hw_params = sti_uniperiph_dai_hw_params, + .set_fmt = sti_uniperiph_dai_set_fmt, +diff --git a/sound/soc/sti/uniperif_reader.c b/sound/soc/sti/uniperif_reader.c +index 065c5f0d1f5f0..05ea2b794eb92 100644 +--- a/sound/soc/sti/uniperif_reader.c ++++ b/sound/soc/sti/uniperif_reader.c +@@ -401,6 +401,7 @@ static const struct snd_soc_dai_ops uni_reader_dai_ops = { + .startup = uni_reader_startup, + .shutdown = uni_reader_shutdown, + .prepare = uni_reader_prepare, ++ .probe = sti_uniperiph_dai_probe, + .trigger = uni_reader_trigger, + .hw_params = sti_uniperiph_dai_hw_params, + .set_fmt = sti_uniperiph_dai_set_fmt, +-- +2.43.0 + diff --git a/queue-6.6/bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch b/queue-6.6/bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch new file mode 100644 index 00000000000..d8dbb16b637 --- /dev/null +++ b/queue-6.6/bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch @@ -0,0 +1,39 @@ +From 0d8d9d41caad632dd794bac09a656f177a2d0f76 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 5 Aug 2024 14:01:21 +0900 +Subject: bpf: kprobe: remove unused declaring of bpf_kprobe_override + +From: Menglong Dong + +[ Upstream commit 0e8b53979ac86eddb3fd76264025a70071a25574 ] + +After the commit 66665ad2f102 ("tracing/kprobe: bpf: Compare instruction +pointer with original one"), "bpf_kprobe_override" is not used anywhere +anymore, and we can remove it now. + +Link: https://lore.kernel.org/all/20240710085939.11520-1-dongml2@chinatelecom.cn/ + +Fixes: 66665ad2f102 ("tracing/kprobe: bpf: Compare instruction pointer with original one") +Signed-off-by: Menglong Dong +Acked-by: Jiri Olsa +Signed-off-by: Masami Hiramatsu (Google) +Signed-off-by: Sasha Levin +--- + include/linux/trace_events.h | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h +index 696f8dc4aa53c..cb8bd759e8005 100644 +--- a/include/linux/trace_events.h ++++ b/include/linux/trace_events.h +@@ -869,7 +869,6 @@ do { \ + struct perf_event; + + DECLARE_PER_CPU(struct pt_regs, perf_trace_regs); +-DECLARE_PER_CPU(int, bpf_kprobe_override); + + extern int perf_trace_init(struct perf_event *event); + extern void perf_trace_destroy(struct perf_event *event); +-- +2.43.0 + diff --git a/queue-6.6/cifs-cifs_inval_name_dfs_link_error-correct-the-chec.patch b/queue-6.6/cifs-cifs_inval_name_dfs_link_error-correct-the-chec.patch new file mode 100644 index 00000000000..0a4f2ee2e97 --- /dev/null +++ b/queue-6.6/cifs-cifs_inval_name_dfs_link_error-correct-the-chec.patch @@ -0,0 +1,60 @@ +From ae4259e37a6624c6cc6bb11063fb484c36388534 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Aug 2024 18:47:48 +0300 +Subject: cifs: cifs_inval_name_dfs_link_error: correct the check for fullpath + +From: Gleb Korobeynikov + +[ Upstream commit 36bb22a08a69d9984a8399c07310d18b115eae20 ] + +Replace the always-true check tcon->origin_fullpath with +check of server->leaf_fullpath + +See https://bugzilla.kernel.org/show_bug.cgi?id=219083 + +The check of the new @tcon will always be true during mounting, +since @tcon->origin_fullpath will only be set after the tree is +connected to the latest common resource, as well as checking if +the prefix paths from it are fully accessible. + +Fixes: 3ae872de4107 ("smb: client: fix shared DFS root mounts with different prefixes") +Reviewed-by: Paulo Alcantara (Red Hat) +Signed-off-by: Gleb Korobeynikov +Signed-off-by: Steve French +Signed-off-by: Sasha Levin +--- + fs/smb/client/misc.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +diff --git a/fs/smb/client/misc.c b/fs/smb/client/misc.c +index 07c468ddb88a8..65d4b72b4d51a 100644 +--- a/fs/smb/client/misc.c ++++ b/fs/smb/client/misc.c +@@ -1288,6 +1288,7 @@ int cifs_inval_name_dfs_link_error(const unsigned int xid, + const char *full_path, + bool *islink) + { ++ struct TCP_Server_Info *server = tcon->ses->server; + struct cifs_ses *ses = tcon->ses; + size_t len; + char *path; +@@ -1304,12 +1305,12 @@ int cifs_inval_name_dfs_link_error(const unsigned int xid, + !is_tcon_dfs(tcon)) + return 0; + +- spin_lock(&tcon->tc_lock); +- if (!tcon->origin_fullpath) { +- spin_unlock(&tcon->tc_lock); ++ spin_lock(&server->srv_lock); ++ if (!server->leaf_fullpath) { ++ spin_unlock(&server->srv_lock); + return 0; + } +- spin_unlock(&tcon->tc_lock); ++ spin_unlock(&server->srv_lock); + + /* + * Slow path - tcon is DFS and @full_path has prefix path, so attempt +-- +2.43.0 + diff --git a/queue-6.6/i2c-qcom-geni-add-missing-clk_disable_unprepare-in-g.patch b/queue-6.6/i2c-qcom-geni-add-missing-clk_disable_unprepare-in-g.patch new file mode 100644 index 00000000000..a3563a29bbc --- /dev/null +++ b/queue-6.6/i2c-qcom-geni-add-missing-clk_disable_unprepare-in-g.patch @@ -0,0 +1,41 @@ +From d74f24420f50d00166a0a8161f96ee0f12820278 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 3 Aug 2024 14:10:41 +0800 +Subject: i2c: qcom-geni: Add missing clk_disable_unprepare in + geni_i2c_runtime_resume + +From: Gaosheng Cui + +[ Upstream commit b93d16bee557302d4e588375ececd833cc048acc ] + +Add the missing clk_disable_unprepare() before return in +geni_i2c_runtime_resume(). + +Fixes: 14d02fbadb5d ("i2c: qcom-geni: add desc struct to prepare support for I2C Master Hub variant") +Signed-off-by: Gaosheng Cui +Reviewed-by: Vladimir Zapolskiy +Signed-off-by: Andi Shyti +Signed-off-by: Sasha Levin +--- + drivers/i2c/busses/i2c-qcom-geni.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c +index 5cc32a465f12e..5ed61cecd8d0e 100644 +--- a/drivers/i2c/busses/i2c-qcom-geni.c ++++ b/drivers/i2c/busses/i2c-qcom-geni.c +@@ -991,8 +991,10 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) + return ret; + + ret = geni_se_resources_on(&gi2c->se); +- if (ret) ++ if (ret) { ++ clk_disable_unprepare(gi2c->core_clk); + return ret; ++ } + + enable_irq(gi2c->irq); + gi2c->suspended = 0; +-- +2.43.0 + diff --git a/queue-6.6/i2c-qcom-geni-add-missing-geni_icc_disable-in-geni_i.patch b/queue-6.6/i2c-qcom-geni-add-missing-geni_icc_disable-in-geni_i.patch new file mode 100644 index 00000000000..bbaca5cf8b5 --- /dev/null +++ b/queue-6.6/i2c-qcom-geni-add-missing-geni_icc_disable-in-geni_i.patch @@ -0,0 +1,37 @@ +From 0a1f02955022fdfad3c512950328cb6cff517f75 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 6 Aug 2024 20:53:31 +0800 +Subject: i2c: qcom-geni: Add missing geni_icc_disable in + geni_i2c_runtime_resume + +From: Gaosheng Cui + +[ Upstream commit 9ba48db9f77ce0001dbb882476fa46e092feb695 ] + +Add the missing geni_icc_disable() before return in +geni_i2c_runtime_resume(). + +Fixes: bf225ed357c6 ("i2c: i2c-qcom-geni: Add interconnect support") +Signed-off-by: Gaosheng Cui +Reviewed-by: Vladimir Zapolskiy +Signed-off-by: Andi Shyti +Signed-off-by: Sasha Levin +--- + drivers/i2c/busses/i2c-qcom-geni.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c +index 5ed61cecd8d0e..b17411e97be68 100644 +--- a/drivers/i2c/busses/i2c-qcom-geni.c ++++ b/drivers/i2c/busses/i2c-qcom-geni.c +@@ -993,6 +993,7 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) + ret = geni_se_resources_on(&gi2c->se); + if (ret) { + clk_disable_unprepare(gi2c->core_clk); ++ geni_icc_disable(&gi2c->se); + return ret; + } + +-- +2.43.0 + diff --git a/queue-6.6/i2c-smbus-improve-handling-of-stuck-alerts.patch b/queue-6.6/i2c-smbus-improve-handling-of-stuck-alerts.patch new file mode 100644 index 00000000000..af19cf2ff90 --- /dev/null +++ b/queue-6.6/i2c-smbus-improve-handling-of-stuck-alerts.patch @@ -0,0 +1,122 @@ +From 99a1bf26a38962b05e988a4516e9a7d1b47b6e5c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 10 Jan 2022 09:28:56 -0800 +Subject: i2c: smbus: Improve handling of stuck alerts + +From: Guenter Roeck + +[ Upstream commit 37c526f00bc1c4f847fc800085f8f009d2e11be6 ] + +The following messages were observed while testing alert functionality +on systems with multiple I2C devices on a single bus if alert was active +on more than one chip. + +smbus_alert 3-000c: SMBALERT# from dev 0x0c, flag 0 +smbus_alert 3-000c: no driver alert()! + +and: + +smbus_alert 3-000c: SMBALERT# from dev 0x28, flag 0 + +Once it starts, this message repeats forever at high rate. There is no +device at any of the reported addresses. + +Analysis shows that this is seen if multiple devices have the alert pin +active. Apparently some devices do not support SMBus arbitration correctly. +They keep sending address bits after detecting an address collision and +handle the collision not at all or too late. +Specifically, address 0x0c is seen with ADT7461A at address 0x4c and +ADM1021 at address 0x18 if alert is active on both chips. Address 0x28 is +seen with ADT7483 at address 0x2a and ADT7461 at address 0x4c if alert is +active on both chips. + +Once the system is in bad state (alert is set by more than one chip), +it often only recovers by power cycling. + +To reduce the impact of this problem, abort the endless loop in +smbus_alert() if the same address is read more than once and not +handled by a driver. + +Fixes: b5527a7766f0 ("i2c: Add SMBus alert support") +Signed-off-by: Guenter Roeck +[wsa: it also fixed an interrupt storm in one of my experiments] +Tested-by: Wolfram Sang +[wsa: rebased, moved a comment as well, improved the 'invalid' value] +Signed-off-by: Wolfram Sang +Signed-off-by: Sasha Levin +--- + drivers/i2c/i2c-smbus.c | 32 +++++++++++++++++++++++++------- + 1 file changed, 25 insertions(+), 7 deletions(-) + +diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c +index 138c3f5e0093a..6097fa6b5b4b3 100644 +--- a/drivers/i2c/i2c-smbus.c ++++ b/drivers/i2c/i2c-smbus.c +@@ -34,6 +34,7 @@ static int smbus_do_alert(struct device *dev, void *addrp) + struct i2c_client *client = i2c_verify_client(dev); + struct alert_data *data = addrp; + struct i2c_driver *driver; ++ int ret; + + if (!client || client->addr != data->addr) + return 0; +@@ -47,16 +48,21 @@ static int smbus_do_alert(struct device *dev, void *addrp) + device_lock(dev); + if (client->dev.driver) { + driver = to_i2c_driver(client->dev.driver); +- if (driver->alert) ++ if (driver->alert) { ++ /* Stop iterating after we find the device */ + driver->alert(client, data->type, data->data); +- else ++ ret = -EBUSY; ++ } else { + dev_warn(&client->dev, "no driver alert()!\n"); +- } else ++ ret = -EOPNOTSUPP; ++ } ++ } else { + dev_dbg(&client->dev, "alert with no driver\n"); ++ ret = -ENODEV; ++ } + device_unlock(dev); + +- /* Stop iterating after we find the device */ +- return -EBUSY; ++ return ret; + } + + /* +@@ -67,6 +73,7 @@ static irqreturn_t smbus_alert(int irq, void *d) + { + struct i2c_smbus_alert *alert = d; + struct i2c_client *ara; ++ unsigned short prev_addr = I2C_CLIENT_END; /* Not a valid address */ + + ara = alert->ara; + +@@ -94,8 +101,19 @@ static irqreturn_t smbus_alert(int irq, void *d) + data.addr, data.data); + + /* Notify driver for the device which issued the alert */ +- device_for_each_child(&ara->adapter->dev, &data, +- smbus_do_alert); ++ status = device_for_each_child(&ara->adapter->dev, &data, ++ smbus_do_alert); ++ /* ++ * If we read the same address more than once, and the alert ++ * was not handled by a driver, it won't do any good to repeat ++ * the loop because it will never terminate. ++ * Bail out in this case. ++ * Note: This assumes that a driver with alert handler handles ++ * the alert properly and clears it if necessary. ++ */ ++ if (data.addr == prev_addr && status != -EBUSY) ++ break; ++ prev_addr = data.addr; + } + + return IRQ_HANDLED; +-- +2.43.0 + diff --git a/queue-6.6/i2c-smbus-send-alert-notifications-to-all-devices-if.patch b/queue-6.6/i2c-smbus-send-alert-notifications-to-all-devices-if.patch new file mode 100644 index 00000000000..19522455b28 --- /dev/null +++ b/queue-6.6/i2c-smbus-send-alert-notifications-to-all-devices-if.patch @@ -0,0 +1,106 @@ +From 468f5b69fa509dc33a84c55e07586516128b728a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Jul 2024 07:19:41 -0700 +Subject: i2c: smbus: Send alert notifications to all devices if source not + found + +From: Guenter Roeck + +[ Upstream commit f6c29f710c1ff2590109f83be3e212b86c01e0f3 ] + +If a SMBus alert is received and the originating device is not found, +the reason may be that the address reported on the SMBus alert address +is corrupted, for example because multiple devices asserted alert and +do not correctly implement SMBus arbitration. + +If this happens, call alert handlers on all devices connected to the +given I2C bus, in the hope that this cleans up the situation. + +This change reliably fixed the problem on a system with multiple devices +on a single bus. Example log where the device on address 0x18 (ADM1021) +and on address 0x4c (ADT7461A) both had the alert line asserted: + +smbus_alert 3-000c: SMBALERT# from dev 0x0c, flag 0 +smbus_alert 3-000c: no driver alert()! +smbus_alert 3-000c: SMBALERT# from dev 0x0c, flag 0 +smbus_alert 3-000c: no driver alert()! +lm90 3-0018: temp1 out of range, please check! +lm90 3-0018: Disabling ALERT# +lm90 3-0029: Everything OK +lm90 3-002a: Everything OK +lm90 3-004c: temp1 out of range, please check! +lm90 3-004c: temp2 out of range, please check! +lm90 3-004c: Disabling ALERT# + +Fixes: b5527a7766f0 ("i2c: Add SMBus alert support") +Signed-off-by: Guenter Roeck +[wsa: fixed a typo in the commit message] +Signed-off-by: Wolfram Sang +Signed-off-by: Sasha Levin +--- + drivers/i2c/i2c-smbus.c | 38 +++++++++++++++++++++++++++++++++++--- + 1 file changed, 35 insertions(+), 3 deletions(-) + +diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c +index 6097fa6b5b4b3..6520e09743912 100644 +--- a/drivers/i2c/i2c-smbus.c ++++ b/drivers/i2c/i2c-smbus.c +@@ -65,6 +65,32 @@ static int smbus_do_alert(struct device *dev, void *addrp) + return ret; + } + ++/* Same as above, but call back all drivers with alert handler */ ++ ++static int smbus_do_alert_force(struct device *dev, void *addrp) ++{ ++ struct i2c_client *client = i2c_verify_client(dev); ++ struct alert_data *data = addrp; ++ struct i2c_driver *driver; ++ ++ if (!client || (client->flags & I2C_CLIENT_TEN)) ++ return 0; ++ ++ /* ++ * Drivers should either disable alerts, or provide at least ++ * a minimal handler. Lock so the driver won't change. ++ */ ++ device_lock(dev); ++ if (client->dev.driver) { ++ driver = to_i2c_driver(client->dev.driver); ++ if (driver->alert) ++ driver->alert(client, data->type, data->data); ++ } ++ device_unlock(dev); ++ ++ return 0; ++} ++ + /* + * The alert IRQ handler needs to hand work off to a task which can issue + * SMBus calls, because those sleeping calls can't be made in IRQ context. +@@ -106,13 +132,19 @@ static irqreturn_t smbus_alert(int irq, void *d) + /* + * If we read the same address more than once, and the alert + * was not handled by a driver, it won't do any good to repeat +- * the loop because it will never terminate. +- * Bail out in this case. ++ * the loop because it will never terminate. Try again, this ++ * time calling the alert handlers of all devices connected to ++ * the bus, and abort the loop afterwards. If this helps, we ++ * are all set. If it doesn't, there is nothing else we can do, ++ * so we might as well abort the loop. + * Note: This assumes that a driver with alert handler handles + * the alert properly and clears it if necessary. + */ +- if (data.addr == prev_addr && status != -EBUSY) ++ if (data.addr == prev_addr && status != -EBUSY) { ++ device_for_each_child(&ara->adapter->dev, &data, ++ smbus_do_alert_force); + break; ++ } + prev_addr = data.addr; + } + +-- +2.43.0 + diff --git a/queue-6.6/kprobes-fix-to-check-symbol-prefixes-correctly.patch b/queue-6.6/kprobes-fix-to-check-symbol-prefixes-correctly.patch new file mode 100644 index 00000000000..3fd14b72c93 --- /dev/null +++ b/queue-6.6/kprobes-fix-to-check-symbol-prefixes-correctly.patch @@ -0,0 +1,40 @@ +From b55c0127dbc40c5b52a5bc76909e79aef4f0db66 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Aug 2024 22:53:15 +0900 +Subject: kprobes: Fix to check symbol prefixes correctly + +From: Masami Hiramatsu (Google) + +[ Upstream commit 8c8acb8f26cbde665b233dd1b9bbcbb9b86822dc ] + +Since str_has_prefix() takes the prefix as the 2nd argument and the string +as the first, is_cfi_preamble_symbol() always fails to check the prefix. +Fix the function parameter order so that it correctly check the prefix. + +Link: https://lore.kernel.org/all/172260679559.362040.7360872132937227206.stgit@devnote2/ + +Fixes: de02f2ac5d8c ("kprobes: Prohibit probing on CFI preamble symbol") +Signed-off-by: Masami Hiramatsu (Google) +Signed-off-by: Sasha Levin +--- + kernel/kprobes.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/kernel/kprobes.c b/kernel/kprobes.c +index add63428c0b40..c10954bd84448 100644 +--- a/kernel/kprobes.c ++++ b/kernel/kprobes.c +@@ -1558,8 +1558,8 @@ static bool is_cfi_preamble_symbol(unsigned long addr) + if (lookup_symbol_name(addr, symbuf)) + return false; + +- return str_has_prefix("__cfi_", symbuf) || +- str_has_prefix("__pfx_", symbuf); ++ return str_has_prefix(symbuf, "__cfi_") || ++ str_has_prefix(symbuf, "__pfx_"); + } + + static int check_kprobe_address_safe(struct kprobe *p, +-- +2.43.0 + diff --git a/queue-6.6/module-make-waiting-for-a-concurrent-module-loader-i.patch b/queue-6.6/module-make-waiting-for-a-concurrent-module-loader-i.patch new file mode 100644 index 00000000000..d5d9b3235d6 --- /dev/null +++ b/queue-6.6/module-make-waiting-for-a-concurrent-module-loader-i.patch @@ -0,0 +1,108 @@ +From ac1c80c3a16e43b878cbcbffb2631f23a863e1b3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 08:33:28 -0700 +Subject: module: make waiting for a concurrent module loader interruptible + +From: Linus Torvalds + +[ Upstream commit 2124d84db293ba164059077944e6b429ba530495 ] + +The recursive aes-arm-bs module load situation reported by Russell King +is getting fixed in the crypto layer, but this in the meantime fixes the +"recursive load hangs forever" by just making the waiting for the first +module load be interruptible. + +This should now match the old behavior before commit 9b9879fc0327 +("modules: catch concurrent module loads, treat them as idempotent"), +which used the different "wait for module to be ready" code in +module_patient_check_exists(). + +End result: a recursive module load will still block, but now a signal +will interrupt it and fail the second module load, at which point the +first module will successfully complete loading. + +Fixes: 9b9879fc0327 ("modules: catch concurrent module loads, treat them as idempotent") +Cc: Russell King +Cc: Herbert Xu +Signed-off-by: Linus Torvalds +Signed-off-by: Sasha Levin +--- + kernel/module/main.c | 40 +++++++++++++++++++++++++--------------- + 1 file changed, 25 insertions(+), 15 deletions(-) + +diff --git a/kernel/module/main.c b/kernel/module/main.c +index f3076654eee12..b00e31721a73e 100644 +--- a/kernel/module/main.c ++++ b/kernel/module/main.c +@@ -3081,7 +3081,7 @@ static bool idempotent(struct idempotent *u, const void *cookie) + struct idempotent *existing; + bool first; + +- u->ret = 0; ++ u->ret = -EINTR; + u->cookie = cookie; + init_completion(&u->complete); + +@@ -3117,7 +3117,7 @@ static int idempotent_complete(struct idempotent *u, int ret) + hlist_for_each_entry_safe(pos, next, head, entry) { + if (pos->cookie != cookie) + continue; +- hlist_del(&pos->entry); ++ hlist_del_init(&pos->entry); + pos->ret = ret; + complete(&pos->complete); + } +@@ -3125,6 +3125,28 @@ static int idempotent_complete(struct idempotent *u, int ret) + return ret; + } + ++/* ++ * Wait for the idempotent worker. ++ * ++ * If we get interrupted, we need to remove ourselves from the ++ * the idempotent list, and the completion may still come in. ++ * ++ * The 'idem_lock' protects against the race, and 'idem.ret' was ++ * initialized to -EINTR and is thus always the right return ++ * value even if the idempotent work then completes between ++ * the wait_for_completion and the cleanup. ++ */ ++static int idempotent_wait_for_completion(struct idempotent *u) ++{ ++ if (wait_for_completion_interruptible(&u->complete)) { ++ spin_lock(&idem_lock); ++ if (!hlist_unhashed(&u->entry)) ++ hlist_del(&u->entry); ++ spin_unlock(&idem_lock); ++ } ++ return u->ret; ++} ++ + static int init_module_from_file(struct file *f, const char __user * uargs, int flags) + { + struct load_info info = { }; +@@ -3168,20 +3190,8 @@ static int idempotent_init_module(struct file *f, const char __user * uargs, int + + /* + * Somebody else won the race and is loading the module. +- * +- * We have to wait for it forever, since our 'idem' is +- * on the stack and the list entry stays there until +- * completed (but we could fix it under the idem_lock) +- * +- * It's also unclear what a real timeout might be, +- * but we could maybe at least make this killable +- * and remove the idem entry in that case? + */ +- for (;;) { +- if (wait_for_completion_timeout(&idem.complete, 10*HZ)) +- return idem.ret; +- pr_warn_once("module '%pD' taking a long time to load", f); +- } ++ return idempotent_wait_for_completion(&idem); + } + + SYSCALL_DEFINE3(finit_module, int, fd, const char __user *, uargs, int, flags) +-- +2.43.0 + diff --git a/queue-6.6/module-warn-about-excessively-long-module-waits.patch b/queue-6.6/module-warn-about-excessively-long-module-waits.patch new file mode 100644 index 00000000000..50bab63ae5f --- /dev/null +++ b/queue-6.6/module-warn-about-excessively-long-module-waits.patch @@ -0,0 +1,108 @@ +From 6988d7a4f21cea8a3e8898035401aeb9a9c5649d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Aug 2024 12:29:40 -0700 +Subject: module: warn about excessively long module waits + +From: Linus Torvalds + +[ Upstream commit cb5b81bc9a448f8db817566f60f92e2ea788ea0f ] + +Russell King reported that the arm cbc(aes) crypto module hangs when +loaded, and Herbert Xu bisected it to commit 9b9879fc0327 ("modules: +catch concurrent module loads, treat them as idempotent"), and noted: + + "So what's happening here is that the first modprobe tries to load a + fallback CBC implementation, in doing so it triggers a load of the + exact same module due to module aliases. + + IOW we're loading aes-arm-bs which provides cbc(aes). However, this + needs a fallback of cbc(aes) to operate, which is made out of the + generic cbc module + any implementation of aes, or ecb(aes). The + latter happens to also be provided by aes-arm-cb so that's why it + tries to load the same module again" + +So loading the aes-arm-bs module ends up wanting to recursively load +itself, and the recursive load then ends up waiting for the original +module load to complete. + +This is a regression, in that it used to be that we just tried to load +the module multiple times, and then as we went on to install it the +second time we would instead just error out because the module name +already existed. + +That is actually also exactly what the original "catch concurrent loads" +patch did in commit 9828ed3f695a ("module: error out early on concurrent +load of the same module file"), but it turns out that it ends up being +racy, in that erroring out before the module has been fully initialized +will cause failures in dependent module loading. + +See commit ac2263b588df (which was the revert of that "error out early") +commit for details about why erroring out before the module has been +initialized is actually fundamentally racy. + +Now, for the actual recursive module load (as opposed to just +concurrently loading the same module twice), the race is not an issue. + +At the same time it's hard for the kernel to see that this is recursion, +because the module load is always done from a usermode helper, so the +recursion is not some simple callchain within the kernel. + +End result: this is not the real fix, but this at least adds a warning +for the situation (admittedly much too late for all the debugging pain +that Russell and Herbert went through) and if we can come to a +resolution on how to detect the recursion properly, this re-organizes +the code to make that easier. + +Link: https://lore.kernel.org/all/ZrFHLqvFqhzykuYw@shell.armlinux.org.uk/ +Reported-by: Russell King +Debugged-by: Herbert Xu +Signed-off-by: Linus Torvalds +Stable-dep-of: 2124d84db293 ("module: make waiting for a concurrent module loader interruptible") +Signed-off-by: Sasha Levin +--- + kernel/module/main.c | 27 ++++++++++++++++++++------- + 1 file changed, 20 insertions(+), 7 deletions(-) + +diff --git a/kernel/module/main.c b/kernel/module/main.c +index 34d9e718c2c7d..f3076654eee12 100644 +--- a/kernel/module/main.c ++++ b/kernel/module/main.c +@@ -3160,15 +3160,28 @@ static int idempotent_init_module(struct file *f, const char __user * uargs, int + if (!f || !(f->f_mode & FMODE_READ)) + return -EBADF; + +- /* See if somebody else is doing the operation? */ +- if (idempotent(&idem, file_inode(f))) { +- wait_for_completion(&idem.complete); +- return idem.ret; ++ /* Are we the winners of the race and get to do this? */ ++ if (!idempotent(&idem, file_inode(f))) { ++ int ret = init_module_from_file(f, uargs, flags); ++ return idempotent_complete(&idem, ret); + } + +- /* Otherwise, we'll do it and complete others */ +- return idempotent_complete(&idem, +- init_module_from_file(f, uargs, flags)); ++ /* ++ * Somebody else won the race and is loading the module. ++ * ++ * We have to wait for it forever, since our 'idem' is ++ * on the stack and the list entry stays there until ++ * completed (but we could fix it under the idem_lock) ++ * ++ * It's also unclear what a real timeout might be, ++ * but we could maybe at least make this killable ++ * and remove the idem entry in that case? ++ */ ++ for (;;) { ++ if (wait_for_completion_timeout(&idem.complete, 10*HZ)) ++ return idem.ret; ++ pr_warn_once("module '%pD' taking a long time to load", f); ++ } + } + + SYSCALL_DEFINE3(finit_module, int, fd, const char __user *, uargs, int, flags) +-- +2.43.0 + diff --git a/queue-6.6/series b/queue-6.6/series index 151f3edcc30..84962805bcd 100644 --- a/queue-6.6/series +++ b/queue-6.6/series @@ -71,3 +71,37 @@ irqchip-meson-gpio-convert-meson_gpio_irq_controller-lock-to-raw_spinlock_t.patc irqchip-loongarch-cpu-fix-return-value-of-lpic_gsi_to_irq.patch sched-cputime-fix-mul_u64_u64_div_u64-precision-for-cputime.patch net-drop-bad-gso-csum_start-and-offset-in-virtio_net_hdr.patch +arm64-add-neoverse-v2-part.patch +arm64-barrier-restore-spec_bar-macro.patch +arm64-cputype-add-cortex-x4-definitions.patch +arm64-cputype-add-neoverse-v3-definitions.patch +arm64-errata-add-workaround-for-arm-errata-3194386-a.patch +arm64-cputype-add-cortex-x3-definitions.patch +arm64-cputype-add-cortex-a720-definitions.patch +arm64-cputype-add-cortex-x925-definitions.patch +arm64-errata-unify-speculative-ssbs-errata-logic.patch +arm64-errata-expand-speculative-ssbs-workaround.patch +arm64-cputype-add-cortex-x1c-definitions.patch +arm64-cputype-add-cortex-a725-definitions.patch +arm64-errata-expand-speculative-ssbs-workaround-agai.patch +i2c-smbus-improve-handling-of-stuck-alerts.patch +asoc-codecs-wcd938x-sdw-correct-soundwire-ports-mask.patch +asoc-codecs-wsa881x-correct-soundwire-ports-mask.patch +asoc-codecs-wsa883x-parse-port-mapping-information.patch +asoc-codecs-wsa883x-correct-soundwire-ports-mask.patch +asoc-codecs-wsa884x-parse-port-mapping-information.patch +asoc-codecs-wsa884x-correct-soundwire-ports-mask.patch +asoc-sti-add-missing-probe-entry-for-player-and-read.patch +spi-spidev-add-missing-spi_device_id-for-bh2228fv.patch +asoc-sof-remove-libraries-from-topology-lookups.patch +i2c-smbus-send-alert-notifications-to-all-devices-if.patch +bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch +kprobes-fix-to-check-symbol-prefixes-correctly.patch +i2c-qcom-geni-add-missing-clk_disable_unprepare-in-g.patch +i2c-qcom-geni-add-missing-geni_icc_disable-in-geni_i.patch +spi-spi-fsl-lpspi-fix-scldiv-calculation.patch +alsa-usb-audio-re-add-scratchamp-quirk-entries.patch +asoc-meson-axg-fifo-fix-irq-scheduling-issue-with-pr.patch +cifs-cifs_inval_name_dfs_link_error-correct-the-chec.patch +module-warn-about-excessively-long-module-waits.patch +module-make-waiting-for-a-concurrent-module-loader-i.patch diff --git a/queue-6.6/spi-spi-fsl-lpspi-fix-scldiv-calculation.patch b/queue-6.6/spi-spi-fsl-lpspi-fix-scldiv-calculation.patch new file mode 100644 index 00000000000..33da3294b2f --- /dev/null +++ b/queue-6.6/spi-spi-fsl-lpspi-fix-scldiv-calculation.patch @@ -0,0 +1,57 @@ +From adfc9e20a1fbd6c5157d847d2a7fb26ee1ff2a67 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 4 Aug 2024 13:36:11 +0200 +Subject: spi: spi-fsl-lpspi: Fix scldiv calculation + +From: Stefan Wahren + +[ Upstream commit 730bbfaf7d4890bd99e637db7767dc68cfeb24e7 ] + +The effective SPI clock frequency should never exceed speed_hz +otherwise this might result in undefined behavior of the SPI device. + +Currently the scldiv calculation could violate this constraint. +For the example parameters perclk_rate = 24 MHz and speed_hz = 7 MHz, +the function fsl_lpspi_set_bitrate will determine perscale = 0 and +scldiv = 1, which is a effective SPI clock of 8 MHz. + +So fix this by rounding up the quotient of perclk_rate and speed_hz. +While this never change within the loop, we can pull this out. + +Fixes: 5314987de5e5 ("spi: imx: add lpspi bus driver") +Signed-off-by: Stefan Wahren +Link: https://patch.msgid.link/20240804113611.83613-1-wahrenst@gmx.net +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-fsl-lpspi.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c +index 079035db7dd85..3c0f7dc9614d1 100644 +--- a/drivers/spi/spi-fsl-lpspi.c ++++ b/drivers/spi/spi-fsl-lpspi.c +@@ -296,7 +296,7 @@ static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi) + static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) + { + struct lpspi_config config = fsl_lpspi->config; +- unsigned int perclk_rate, scldiv; ++ unsigned int perclk_rate, scldiv, div; + u8 prescale; + + perclk_rate = clk_get_rate(fsl_lpspi->clk_per); +@@ -313,8 +313,10 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) + return -EINVAL; + } + ++ div = DIV_ROUND_UP(perclk_rate, config.speed_hz); ++ + for (prescale = 0; prescale < 8; prescale++) { +- scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2; ++ scldiv = div / (1 << prescale) - 2; + if (scldiv < 256) { + fsl_lpspi->config.prescale = prescale; + break; +-- +2.43.0 + diff --git a/queue-6.6/spi-spidev-add-missing-spi_device_id-for-bh2228fv.patch b/queue-6.6/spi-spidev-add-missing-spi_device_id-for-bh2228fv.patch new file mode 100644 index 00000000000..353d520a52f --- /dev/null +++ b/queue-6.6/spi-spidev-add-missing-spi_device_id-for-bh2228fv.patch @@ -0,0 +1,42 @@ +From 684d23ba99eda69ee099bee257aa9ce3b106a321 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Jul 2024 15:35:47 +0200 +Subject: spi: spidev: Add missing spi_device_id for bh2228fv + +From: Geert Uytterhoeven + +[ Upstream commit e4c4638b6a10427d30e29d22351c375886025f47 ] + +When the of_device_id entry for "rohm,bh2228fv" was added, the +corresponding spi_device_id was forgotten, causing a warning message +during boot-up: + + SPI driver spidev has no spi_device_id for rohm,bh2228fv + +Fix module autoloading and shut up the warning by adding the missing +entry. + +Fixes: fc28d1c1fe3b3e2f ("spi: spidev: add correct compatible for Rohm BH2228FV") +Signed-off-by: Geert Uytterhoeven +Link: https://patch.msgid.link/cb571d4128f41175f31319cd9febc829417ea167.1722346539.git.geert+renesas@glider.be +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spidev.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c +index 1a8dd10012448..b97206d47ec6d 100644 +--- a/drivers/spi/spidev.c ++++ b/drivers/spi/spidev.c +@@ -704,6 +704,7 @@ static const struct file_operations spidev_fops = { + static struct class *spidev_class; + + static const struct spi_device_id spidev_spi_ids[] = { ++ { .name = "bh2228fv" }, + { .name = "dh2228fv" }, + { .name = "ltc2488" }, + { .name = "sx1301" }, +-- +2.43.0 +