From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 3 Apr 2013 10:34:19 +0000 (+0200)
Subject: zynq: Support fpga command for all zynq families
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=20a6cdd301941b97961c9c5425b5fbb771321aac;p=thirdparty%2Fu-boot.git

zynq: Support fpga command for all zynq families

Detect zynq idcode and based on that setup fpga device
which is connected to it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 80ca25d94a2..e5f710d4e25 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -33,6 +33,9 @@
 #define SLCR_NAND_L2_SEL		0x10
 #define SLCR_NAND_L2_SEL_MASK		0x1F
 
+#define SLCR_IDCODE_MASK	0x1F000
+#define SLCR_IDCODE_SHIFT	12
+
 /*
  * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
  *
@@ -200,6 +203,12 @@ u32 zynq_slcr_get_boot_mode(void)
 	return readl(&slcr_base->boot_mode);
 }
 
+u32 zynq_slcr_get_idcode(void)
+{
+	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
+							SLCR_IDCODE_SHIFT;
+}
+
 /*
  * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
  *
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index 0e8f71740db..3fd980ae294 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -46,7 +46,9 @@ struct slcr_regs {
 	u32 boot_mode; /* 0x25c */
 	u32 reserved4[116];
 	u32 trust_zone; /* 0x430 */ /* FIXME */
-	u32 reserved5[115];
+	u32 reserved5_1[63];
+	u32 pss_idcode; /* 0x530 */
+	u32 reserved5_2[51];
 	u32 ddr_urgent; /* 0x600 */
 	u32 reserved6[6];
 	u32 ddr_urgent_sel; /* 0x61c */
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index fd2ecc5ee0f..411589eb525 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -30,6 +30,7 @@ extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
 extern void zynq_slcr_devcfg_disable(void);
 extern void zynq_slcr_devcfg_enable(void);
 extern u32 zynq_slcr_get_boot_mode(void);
+extern u32 zynq_slcr_get_idcode(void);
 extern int zynq_slcr_get_mio_pin_status(const char *periph);
 
 #endif /* _SYS_PROTO_H_ */
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index f259f2fcdbb..3bb90f51479 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -39,11 +39,38 @@ DECLARE_GLOBAL_DATA_PTR;
 #define JTAG_MODE		0x00000000
 
 #ifdef CONFIG_FPGA
-Xilinx_desc fpga = XILINX_XC7Z020_DESC(0);
+Xilinx_desc fpga;
+
+/* It can be done differently */
+Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
+Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
 #endif
 
 int board_init(void)
 {
+#ifdef CONFIG_FPGA
+	u32 idcode;
+
+	idcode = zynq_slcr_get_idcode();
+
+	switch (idcode) {
+	case XILINX_ZYNQ_7010:
+		fpga = fpga010;
+		break;
+	case XILINX_ZYNQ_7020:
+		fpga = fpga020;
+		break;
+	case XILINX_ZYNQ_7030:
+		fpga = fpga030;
+		break;
+	case XILINX_ZYNQ_7045:
+		fpga = fpga045;
+		break;
+	}
+#endif
+
 	/* temporary hack to clear pending irqs before Linux as it
 	 * will hang Linux
 	 */
diff --git a/include/zynqpl.h b/include/zynqpl.h
index eb87ba727ab..c9629e149e3 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -31,13 +31,30 @@ extern int zynq_load(Xilinx_desc *desc, const void *image, size_t size);
 extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
 extern int zynq_info(Xilinx_desc *desc);
 
+#define XILINX_ZYNQ_7010	0x2
+#define XILINX_ZYNQ_7020	0x7
+#define XILINX_ZYNQ_7030	0xc
+#define XILINX_ZYNQ_7045	0x11
+
 /* Device Image Sizes
  *********************************************************************/
+#define XILINX_XC7Z010_SIZE	16669920/8
 #define XILINX_XC7Z020_SIZE	32364512/8
+#define XILINX_XC7Z030_SIZE	47839328/8
+#define XILINX_XC7Z045_SIZE	106571232/8
 
 /* Descriptor Macros
  *********************************************************************/
+#define XILINX_XC7Z010_DESC(cookie) \
+{ Xilinx_Zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie }
+
 #define XILINX_XC7Z020_DESC(cookie) \
 { Xilinx_Zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie }
 
+#define XILINX_XC7Z030_DESC(cookie) \
+{ Xilinx_Zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie }
+
+#define XILINX_XC7Z045_DESC(cookie) \
+{ Xilinx_Zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie }
+
 #endif /* _ZYNQPL_H_ */