From: Xin Wang Date: Wed, 25 Feb 2026 02:20:14 +0000 (-0800) Subject: drm/xe: restrict multi-lrc to VCS/VECS engines X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=223b2f51ba6bbf70dbebdb69b93b66b074289e04;p=thirdparty%2Fkernel%2Flinux.git drm/xe: restrict multi-lrc to VCS/VECS engines Tighten uapi validation to restrict multi-lrc support to VIDEO_DECODE and VIDEO_ENHANCE engines only. This check should have been in place from the start, as the driver typically avoids allowing uapi cases that we have no userspace consumer for. Additionally, the GuC firmware on ModSched platforms no longer supports multi-lrc on non-media engines. V4: - use a unified mask for all platforms since engine instance count is an independent runtime check (Matt Roper, Matthew Brost) V3: - store a multi-lrc enable class mask in xe->info and populate from xe_device_desc in xe_pci.c (Matthew Brost) V2: - correct the typo (Shuicheng) - move the check earlier to avoid VM lookup (Shuicheng, Matt Roper) - remove the graphics version check (Matt Roper) - input more details in the commit info (Matt Roper) Cc: Shuicheng Lin Cc: Matt Roper Cc: Matthew Brost Signed-off-by: Xin Wang Reviewed-by: Shuicheng Lin Reviewed-by: Matt Roper Link: https://patch.msgid.link/20260225022014.45394-1-x.wang@intel.com Signed-off-by: Matt Roper --- diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index 8f3ef836541e7..caa8f34a6744a 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -138,6 +138,8 @@ struct xe_device { u8 tile_count; /** @info.max_gt_per_tile: Number of GT IDs allocated to each tile */ u8 max_gt_per_tile; + /** @info.multi_lrc_mask: bitmask of engine classes which support multi-lrc */ + u8 multi_lrc_mask; /** @info.gt_count: Total number of GTs for entire device */ u8 gt_count; /** @info.vm_max_level: Max VM level */ diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c index 66d0e10ee2c4a..5abb29454d1ff 100644 --- a/drivers/gpu/drm/xe/xe_exec_queue.c +++ b/drivers/gpu/drm/xe/xe_exec_queue.c @@ -1184,6 +1184,11 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data, if (XE_IOCTL_DBG(xe, !hwe)) return -EINVAL; + /* multi-lrc is only supported on select engine classes */ + if (XE_IOCTL_DBG(xe, args->width > 1 && + !(xe->info.multi_lrc_mask & BIT(hwe->class)))) + return -EOPNOTSUPP; + vm = xe_vm_lookup(xef, args->vm_id); if (XE_IOCTL_DBG(xe, !vm)) return -ENOENT; diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 56a768f2cfca3..b48e84549888a 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -184,6 +184,10 @@ static const struct xe_ip media_ips[] = { { 3503, "Xe3p_HPM", &media_xelpmp }, }; +#define MULTI_LRC_MASK \ + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) | \ + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE) + static const struct xe_device_desc tgl_desc = { .pre_gmdid_graphics_ip = &graphics_ip_xelp, .pre_gmdid_media_ip = &media_ip_xem, @@ -194,6 +198,7 @@ static const struct xe_device_desc tgl_desc = { .has_llc = true, .has_sriov = true, .max_gt_per_tile = 1, + MULTI_LRC_MASK, .require_force_probe = true, .va_bits = 48, .vm_max_level = 3, @@ -208,6 +213,7 @@ static const struct xe_device_desc rkl_desc = { .has_display = true, .has_llc = true, .max_gt_per_tile = 1, + MULTI_LRC_MASK, .require_force_probe = true, .va_bits = 48, .vm_max_level = 3, @@ -225,6 +231,7 @@ static const struct xe_device_desc adl_s_desc = { .has_llc = true, .has_sriov = true, .max_gt_per_tile = 1, + MULTI_LRC_MASK, .require_force_probe = true, .subplatforms = (const struct xe_subplatform_desc[]) { { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, @@ -246,6 +253,7 @@ static const struct xe_device_desc adl_p_desc = { .has_llc = true, .has_sriov = true, .max_gt_per_tile = 1, + MULTI_LRC_MASK, .require_force_probe = true, .subplatforms = (const struct xe_subplatform_desc[]) { { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, @@ -265,6 +273,7 @@ static const struct xe_device_desc adl_n_desc = { .has_llc = true, .has_sriov = true, .max_gt_per_tile = 1, + MULTI_LRC_MASK, .require_force_probe = true, .va_bits = 48, .vm_max_level = 3, @@ -283,6 +292,7 @@ static const struct xe_device_desc dg1_desc = { .has_gsc_nvm = 1, .has_heci_gscfi = 1, .max_gt_per_tile = 1, + MULTI_LRC_MASK, .require_force_probe = true, .va_bits = 48, .vm_max_level = 3, @@ -313,6 +323,7 @@ static const struct xe_device_desc ats_m_desc = { .pre_gmdid_media_ip = &media_ip_xehpm, .dma_mask_size = 46, .max_gt_per_tile = 1, + MULTI_LRC_MASK, .require_force_probe = true, DG2_FEATURES, @@ -325,6 +336,7 @@ static const struct xe_device_desc dg2_desc = { .pre_gmdid_media_ip = &media_ip_xehpm, .dma_mask_size = 46, .max_gt_per_tile = 1, + MULTI_LRC_MASK, .require_force_probe = true, DG2_FEATURES, @@ -343,6 +355,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = { .has_heci_gscfi = 1, .max_gt_per_tile = 1, .max_remote_tiles = 1, + MULTI_LRC_MASK, .require_force_probe = true, .va_bits = 57, .vm_max_level = 4, @@ -358,6 +371,7 @@ static const struct xe_device_desc mtl_desc = { .has_display = true, .has_pxp = true, .max_gt_per_tile = 2, + MULTI_LRC_MASK, .va_bits = 48, .vm_max_level = 3, }; @@ -369,6 +383,7 @@ static const struct xe_device_desc lnl_desc = { .has_flat_ccs = 1, .has_pxp = true, .max_gt_per_tile = 2, + MULTI_LRC_MASK, .needs_scratch = true, .va_bits = 48, .vm_max_level = 4, @@ -393,6 +408,7 @@ static const struct xe_device_desc bmg_desc = { .has_soc_remapper_telem = true, .has_sriov = true, .max_gt_per_tile = 2, + MULTI_LRC_MASK, .needs_scratch = true, .subplatforms = (const struct xe_subplatform_desc[]) { { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids }, @@ -411,6 +427,7 @@ static const struct xe_device_desc ptl_desc = { .has_pre_prod_wa = 1, .has_pxp = true, .max_gt_per_tile = 2, + MULTI_LRC_MASK, .needs_scratch = true, .needs_shared_vf_gt_wq = true, .va_bits = 48, @@ -424,6 +441,7 @@ static const struct xe_device_desc nvls_desc = { .has_flat_ccs = 1, .has_pre_prod_wa = 1, .max_gt_per_tile = 2, + MULTI_LRC_MASK, .require_force_probe = true, .va_bits = 48, .vm_max_level = 4, @@ -445,6 +463,7 @@ static const struct xe_device_desc cri_desc = { .has_soc_remapper_telem = true, .has_sriov = true, .max_gt_per_tile = 2, + MULTI_LRC_MASK, .require_force_probe = true, .va_bits = 57, .vm_max_level = 4, @@ -459,6 +478,7 @@ static const struct xe_device_desc nvlp_desc = { .has_page_reclaim_hw_assist = true, .has_pre_prod_wa = true, .max_gt_per_tile = 2, + MULTI_LRC_MASK, .require_force_probe = true, .va_bits = 48, .vm_max_level = 4, @@ -745,6 +765,7 @@ static int xe_info_init_early(struct xe_device *xe, xe->info.skip_pcode = desc->skip_pcode; xe->info.needs_scratch = desc->needs_scratch; xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq; + xe->info.multi_lrc_mask = desc->multi_lrc_mask; xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && xe_modparam.probe_display && diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h index 470d31a1f0d6f..47e8a1552c2bf 100644 --- a/drivers/gpu/drm/xe/xe_pci_types.h +++ b/drivers/gpu/drm/xe/xe_pci_types.h @@ -30,6 +30,7 @@ struct xe_device_desc { u8 dma_mask_size; u8 max_remote_tiles:2; u8 max_gt_per_tile:2; + u8 multi_lrc_mask; u8 va_bits; u8 vm_max_level; u8 vram_flags;