From: Greg Kroah-Hartman Date: Fri, 26 May 2023 18:39:23 +0000 (+0100) Subject: 5.15-stable patches X-Git-Tag: review~79 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=23516b2fcba6c0b9358f841268b1fe98f8c6e1c8;p=thirdparty%2Fkernel%2Fstable-queue.git 5.15-stable patches added patches: ocfs2-switch-to-security_inode_init_security.patch spi-fsl-cpm-use-16-bit-mode-for-large-transfers-with-even-size.patch spi-fsl-spi-re-organise-transfer-bits_per_word-adaptation.patch --- diff --git a/queue-5.15/ocfs2-switch-to-security_inode_init_security.patch b/queue-5.15/ocfs2-switch-to-security_inode_init_security.patch new file mode 100644 index 00000000000..ed9aed5519b --- /dev/null +++ b/queue-5.15/ocfs2-switch-to-security_inode_init_security.patch @@ -0,0 +1,118 @@ +From de3004c874e740304cc4f4a83d6200acb511bbda Mon Sep 17 00:00:00 2001 +From: Roberto Sassu +Date: Tue, 14 Mar 2023 09:17:16 +0100 +Subject: ocfs2: Switch to security_inode_init_security() + +From: Roberto Sassu + +commit de3004c874e740304cc4f4a83d6200acb511bbda upstream. + +In preparation for removing security_old_inode_init_security(), switch to +security_inode_init_security(). + +Extend the existing ocfs2_initxattrs() to take the +ocfs2_security_xattr_info structure from fs_info, and populate the +name/value/len triple with the first xattr provided by LSMs. + +As fs_info was not used before, ocfs2_initxattrs() can now handle the case +of replicating the behavior of security_old_inode_init_security(), i.e. +just obtaining the xattr, in addition to setting all xattrs provided by +LSMs. + +Supporting multiple xattrs is not currently supported where +security_old_inode_init_security() was called (mknod, symlink), as it +requires non-trivial changes that can be done at a later time. Like for +reiserfs, even if EVM is invoked, it will not provide an xattr (if it is +not the first to set it, its xattr will be discarded; if it is the first, +it does not have xattrs to calculate the HMAC on). + +Finally, since security_inode_init_security(), unlike +security_old_inode_init_security(), returns zero instead of -EOPNOTSUPP if +no xattrs were provided by LSMs or if inodes are private, additionally +check in ocfs2_init_security_get() if the xattr name is set. + +If not, act as if security_old_inode_init_security() returned -EOPNOTSUPP, +and set si->enable to zero to notify to the functions following +ocfs2_init_security_get() that no xattrs are available. + +Signed-off-by: Roberto Sassu +Reviewed-by: Casey Schaufler +Acked-by: Joseph Qi +Reviewed-by: Mimi Zohar +Signed-off-by: Paul Moore +Signed-off-by: Greg Kroah-Hartman +--- + fs/ocfs2/namei.c | 2 ++ + fs/ocfs2/xattr.c | 30 ++++++++++++++++++++++++++---- + 2 files changed, 28 insertions(+), 4 deletions(-) + +--- a/fs/ocfs2/namei.c ++++ b/fs/ocfs2/namei.c +@@ -242,6 +242,7 @@ static int ocfs2_mknod(struct user_names + int want_meta = 0; + int xattr_credits = 0; + struct ocfs2_security_xattr_info si = { ++ .name = NULL, + .enable = 1, + }; + int did_quota_inode = 0; +@@ -1805,6 +1806,7 @@ static int ocfs2_symlink(struct user_nam + int want_clusters = 0; + int xattr_credits = 0; + struct ocfs2_security_xattr_info si = { ++ .name = NULL, + .enable = 1, + }; + int did_quota = 0, did_quota_inode = 0; +--- a/fs/ocfs2/xattr.c ++++ b/fs/ocfs2/xattr.c +@@ -7259,9 +7259,21 @@ static int ocfs2_xattr_security_set(cons + static int ocfs2_initxattrs(struct inode *inode, const struct xattr *xattr_array, + void *fs_info) + { ++ struct ocfs2_security_xattr_info *si = fs_info; + const struct xattr *xattr; + int err = 0; + ++ if (si) { ++ si->value = kmemdup(xattr_array->value, xattr_array->value_len, ++ GFP_KERNEL); ++ if (!si->value) ++ return -ENOMEM; ++ ++ si->name = xattr_array->name; ++ si->value_len = xattr_array->value_len; ++ return 0; ++ } ++ + for (xattr = xattr_array; xattr->name != NULL; xattr++) { + err = ocfs2_xattr_set(inode, OCFS2_XATTR_INDEX_SECURITY, + xattr->name, xattr->value, +@@ -7277,13 +7289,23 @@ int ocfs2_init_security_get(struct inode + const struct qstr *qstr, + struct ocfs2_security_xattr_info *si) + { ++ int ret; ++ + /* check whether ocfs2 support feature xattr */ + if (!ocfs2_supports_xattr(OCFS2_SB(dir->i_sb))) + return -EOPNOTSUPP; +- if (si) +- return security_old_inode_init_security(inode, dir, qstr, +- &si->name, &si->value, +- &si->value_len); ++ if (si) { ++ ret = security_inode_init_security(inode, dir, qstr, ++ &ocfs2_initxattrs, si); ++ /* ++ * security_inode_init_security() does not return -EOPNOTSUPP, ++ * we have to check the xattr ourselves. ++ */ ++ if (!ret && !si->name) ++ si->enable = 0; ++ ++ return ret; ++ } + + return security_inode_init_security(inode, dir, qstr, + &ocfs2_initxattrs, NULL); diff --git a/queue-5.15/series b/queue-5.15/series index 479615587be..608688dc9b2 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -4,3 +4,6 @@ dt-bindings-ata-ahci-ceva-convert-to-yaml.patch dt-bindings-ata-ahci-ceva-cover-all-4-iommus-entries.patch watchdog-sp5100_tco-immediately-trigger-upon-starting.patch arm-dts-stm32-fix-av96-board-sai2-pin-muxing-on-stm32mp15.patch +spi-fsl-spi-re-organise-transfer-bits_per_word-adaptation.patch +spi-fsl-cpm-use-16-bit-mode-for-large-transfers-with-even-size.patch +ocfs2-switch-to-security_inode_init_security.patch diff --git a/queue-5.15/spi-fsl-cpm-use-16-bit-mode-for-large-transfers-with-even-size.patch b/queue-5.15/spi-fsl-cpm-use-16-bit-mode-for-large-transfers-with-even-size.patch new file mode 100644 index 00000000000..5ef6d577a89 --- /dev/null +++ b/queue-5.15/spi-fsl-cpm-use-16-bit-mode-for-large-transfers-with-even-size.patch @@ -0,0 +1,97 @@ +From christophe.leroy@csgroup.eu Mon May 15 15:07:59 2023 +From: Christophe Leroy +Date: Mon, 15 May 2023 16:07:17 +0200 +Subject:[For 5.15/5.10/5.4] spi: fsl-cpm: Use 16 bit mode for large transfers with even size +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Mark Brown +Message-ID: <3a1b8774ad7004acb594fbf220f98488dbaa2896.1684156552.git.christophe.leroy@csgroup.eu> + +From: Christophe Leroy + +(cherry picked from upstream fc96ec826bced75cc6b9c07a4ac44bbf651337ab) + +On CPM, the RISC core is a lot more efficiant when doing transfers +in 16-bits chunks than in 8-bits chunks, but unfortunately the +words need to be byte swapped as seen in a previous commit. + +So, for large tranfers with an even size, allocate a temporary tx +buffer and byte-swap data before and after transfer. + +This change allows setting higher speed for transfer. For instance +on an MPC 8xx (CPM1 comms RISC processor), the documentation tells +that transfer in byte mode at 1 kbit/s uses 0.200% of CPM load +at 25 MHz while a word transfer at the same speed uses 0.032% +of CPM load. This means the speed can be 6 times higher in +word mode for the same CPM load. + +For the time being, only do it on CPM1 as there must be a +trade-off between the CPM load reduction and the CPU load required +to byte swap the data. + +Signed-off-by: Christophe Leroy +Link: https://lore.kernel.org/r/f2e981f20f92dd28983c3949702a09248c23845c.1680371809.git.christophe.leroy@csgroup.eu +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman +--- + drivers/spi/spi-fsl-cpm.c | 23 +++++++++++++++++++++++ + drivers/spi/spi-fsl-spi.c | 3 +++ + 2 files changed, 26 insertions(+) + +--- a/drivers/spi/spi-fsl-cpm.c ++++ b/drivers/spi/spi-fsl-cpm.c +@@ -21,6 +21,7 @@ + #include + #include + #include ++#include + + #include "spi-fsl-cpm.h" + #include "spi-fsl-lib.h" +@@ -120,6 +121,21 @@ int fsl_spi_cpm_bufs(struct mpc8xxx_spi + mspi->rx_dma = mspi->dma_dummy_rx; + mspi->map_rx_dma = 0; + } ++ if (t->bits_per_word == 16 && t->tx_buf) { ++ const u16 *src = t->tx_buf; ++ u16 *dst; ++ int i; ++ ++ dst = kmalloc(t->len, GFP_KERNEL); ++ if (!dst) ++ return -ENOMEM; ++ ++ for (i = 0; i < t->len >> 1; i++) ++ dst[i] = cpu_to_le16p(src + i); ++ ++ mspi->tx = dst; ++ mspi->map_tx_dma = 1; ++ } + + if (mspi->map_tx_dma) { + void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */ +@@ -173,6 +189,13 @@ void fsl_spi_cpm_bufs_complete(struct mp + if (mspi->map_rx_dma) + dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE); + mspi->xfer_in_progress = NULL; ++ ++ if (t->bits_per_word == 16 && t->rx_buf) { ++ int i; ++ ++ for (i = 0; i < t->len; i += 2) ++ le16_to_cpus(t->rx_buf + i); ++ } + } + EXPORT_SYMBOL_GPL(fsl_spi_cpm_bufs_complete); + +--- a/drivers/spi/spi-fsl-spi.c ++++ b/drivers/spi/spi-fsl-spi.c +@@ -368,6 +368,9 @@ static int fsl_spi_do_one_msg(struct spi + return -EINVAL; + if (t->bits_per_word == 16 || t->bits_per_word == 32) + t->bits_per_word = 8; /* pretend its 8 bits */ ++ if (t->bits_per_word == 8 && t->len >= 256 && ++ (mpc8xxx_spi->flags & SPI_CPM1)) ++ t->bits_per_word = 16; + } + } + diff --git a/queue-5.15/spi-fsl-spi-re-organise-transfer-bits_per_word-adaptation.patch b/queue-5.15/spi-fsl-spi-re-organise-transfer-bits_per_word-adaptation.patch new file mode 100644 index 00000000000..d99c1aa791e --- /dev/null +++ b/queue-5.15/spi-fsl-spi-re-organise-transfer-bits_per_word-adaptation.patch @@ -0,0 +1,118 @@ +From christophe.leroy@csgroup.eu Mon May 15 15:08:03 2023 +From: Christophe Leroy +Date: Mon, 15 May 2023 16:07:16 +0200 +Subject:[For 5.15/5.10/5.4] spi: fsl-spi: Re-organise transfer bits_per_word adaptation +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Mark Brown +Message-ID: <1e4bfb4850ba849c316f48a0ab0d7123da0e2f54.1684156552.git.christophe.leroy@csgroup.eu> + +From: Christophe Leroy + +(backported from upstream 8a5299a1278eadf1e08a598a5345c376206f171e) + +For different reasons, fsl-spi driver performs bits_per_word +modifications for different reasons: +- On CPU mode, to minimise amount of interrupts +- On CPM/QE mode to work around controller byte order + +For CPU mode that's done in fsl_spi_prepare_message() while +for CPM mode that's done in fsl_spi_setup_transfer(). + +Reunify all of it in fsl_spi_prepare_message(), and catch +impossible cases early through master's bits_per_word_mask +instead of returning EINVAL later. + +Signed-off-by: Christophe Leroy +Link: https://lore.kernel.org/r/0ce96fe96e8b07cba0613e4097cfd94d09b8919a.1680371809.git.christophe.leroy@csgroup.eu +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman +--- + drivers/spi/spi-fsl-spi.c | 50 +++++++++++++++++++++------------------------- + 1 file changed, 23 insertions(+), 27 deletions(-) + +--- a/drivers/spi/spi-fsl-spi.c ++++ b/drivers/spi/spi-fsl-spi.c +@@ -203,26 +203,6 @@ static int mspi_apply_cpu_mode_quirks(st + return bits_per_word; + } + +-static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, +- struct spi_device *spi, +- int bits_per_word) +-{ +- /* CPM/QE uses Little Endian for words > 8 +- * so transform 16 and 32 bits words into 8 bits +- * Unfortnatly that doesn't work for LSB so +- * reject these for now */ +- /* Note: 32 bits word, LSB works iff +- * tfcr/rfcr is set to CPMFCR_GBL */ +- if (spi->mode & SPI_LSB_FIRST && +- bits_per_word > 8) +- return -EINVAL; +- if (bits_per_word <= 8) +- return bits_per_word; +- if (bits_per_word == 16 || bits_per_word == 32) +- return 8; /* pretend its 8 bits */ +- return -EINVAL; +-} +- + static int fsl_spi_setup_transfer(struct spi_device *spi, + struct spi_transfer *t) + { +@@ -250,9 +230,6 @@ static int fsl_spi_setup_transfer(struct + bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, + mpc8xxx_spi, + bits_per_word); +- else +- bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, +- bits_per_word); + + if (bits_per_word < 0) + return bits_per_word; +@@ -370,14 +347,27 @@ static int fsl_spi_do_one_msg(struct spi + * In CPU mode, optimize large byte transfers to use larger + * bits_per_word values to reduce number of interrupts taken. + */ +- if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { +- list_for_each_entry(t, &m->transfers, transfer_list) { ++ list_for_each_entry(t, &m->transfers, transfer_list) { ++ if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { + if (t->len < 256 || t->bits_per_word != 8) + continue; + if ((t->len & 3) == 0) + t->bits_per_word = 32; + else if ((t->len & 1) == 0) + t->bits_per_word = 16; ++ } else { ++ /* ++ * CPM/QE uses Little Endian for words > 8 ++ * so transform 16 and 32 bits words into 8 bits ++ * Unfortnatly that doesn't work for LSB so ++ * reject these for now ++ * Note: 32 bits word, LSB works iff ++ * tfcr/rfcr is set to CPMFCR_GBL ++ */ ++ if (m->spi->mode & SPI_LSB_FIRST && t->bits_per_word > 8) ++ return -EINVAL; ++ if (t->bits_per_word == 16 || t->bits_per_word == 32) ++ t->bits_per_word = 8; /* pretend its 8 bits */ + } + } + +@@ -635,8 +625,14 @@ static struct spi_master *fsl_spi_probe( + if (mpc8xxx_spi->type == TYPE_GRLIB) + fsl_spi_grlib_probe(dev); + +- master->bits_per_word_mask = +- (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) & ++ if (mpc8xxx_spi->flags & SPI_CPM_MODE) ++ master->bits_per_word_mask = ++ (SPI_BPW_RANGE_MASK(4, 8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(32)); ++ else ++ master->bits_per_word_mask = ++ (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)); ++ ++ master->bits_per_word_mask &= + SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word); + + if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)