From: Greg Kroah-Hartman Date: Sat, 10 Apr 2021 13:51:15 +0000 (+0200) Subject: 5.4-stable patches X-Git-Tag: v4.19.187~70 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=249301d75d91458de08d860f936b7008f0661e26;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: arm-dts-turris-omnia-configure-led-intn-pin-as-interrupt-pin.patch drm-i915-fix-invalid-access-to-acpi-_dsm-objects.patch fs-direct-io-fix-missing-sdio-boundary.patch gcov-re-fix-clang-11-support.patch ia64-fix-user_stack_pointer-for-ptrace.patch nds32-flush_dcache_page-use-page_mapping_file-to-avoid-races-with-swapoff.patch net-dsa-lantiq_gswip-configure-all-remaining-gswip_mii_cfg-bits.patch net-dsa-lantiq_gswip-don-t-use-phy-auto-polling.patch net-dsa-lantiq_gswip-let-gswip-automatically-set-the-xmii-clock.patch net-ipv6-check-for-validity-before-dereferencing-cfg-fc_nlinfo.nlh.patch ocfs2-fix-deadlock-between-setattr-and-dio_end_io_write.patch parisc-avoid-a-warning-on-u8-cast-for-cmpxchg-on-u8-pointers.patch parisc-parisc-agp-requires-sba-iommu-driver.patch --- diff --git a/queue-5.4/arm-dts-turris-omnia-configure-led-intn-pin-as-interrupt-pin.patch b/queue-5.4/arm-dts-turris-omnia-configure-led-intn-pin-as-interrupt-pin.patch new file mode 100644 index 00000000000..a255360694f --- /dev/null +++ b/queue-5.4/arm-dts-turris-omnia-configure-led-intn-pin-as-interrupt-pin.patch @@ -0,0 +1,56 @@ +From a26c56ae67fa9fbb45a8a232dcd7ebaa7af16086 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Beh=C3=BAn?= +Date: Sun, 21 Feb 2021 00:11:44 +0100 +Subject: ARM: dts: turris-omnia: configure LED[2]/INTn pin as interrupt pin +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Marek Behún + +commit a26c56ae67fa9fbb45a8a232dcd7ebaa7af16086 upstream. + +Use the `marvell,reg-init` DT property to configure the LED[2]/INTn pin +of the Marvell 88E1514 ethernet PHY on Turris Omnia into interrupt mode. + +Without this the pin is by default in LED[2] mode, and the Marvell PHY +driver configures LED[2] into "On - Link, Blink - Activity" mode. + +This fixes the issue where the pca9538 GPIO/interrupt controller (which +can't mask interrupts in HW) received too many interrupts and after a +time started ignoring the interrupt with error message: + IRQ 71: nobody cared + +There is a work in progress to have the Marvell PHY driver support +parsing PHY LED nodes from OF and registering the LEDs as Linux LED +class devices. Once this is done the PHY driver can also automatically +set the pin into INTn mode if it does not find LED[2] in OF. + +Until then, though, we fix this via `marvell,reg-init` DT property. + +Signed-off-by: Marek Behún +Reported-by: Rui Salvaterra +Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia") +Cc: Uwe Kleine-König +Cc: linux-arm-kernel@lists.infradead.org +Cc: Andrew Lunn +Cc: Gregory CLEMENT +Cc: +Tested-by: Rui Salvaterra +Reviewed-by: Andrew Lunn +Signed-off-by: Gregory CLEMENT +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm/boot/dts/armada-385-turris-omnia.dts | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts ++++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts +@@ -236,6 +236,7 @@ + status = "okay"; + compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22"; + reg = <1>; ++ marvell,reg-init = <3 18 0 0x4985>; + + /* irq is connected to &pcawan pin 7 */ + }; diff --git a/queue-5.4/drm-i915-fix-invalid-access-to-acpi-_dsm-objects.patch b/queue-5.4/drm-i915-fix-invalid-access-to-acpi-_dsm-objects.patch new file mode 100644 index 00000000000..eb0c713f562 --- /dev/null +++ b/queue-5.4/drm-i915-fix-invalid-access-to-acpi-_dsm-objects.patch @@ -0,0 +1,71 @@ +From b6a37a93c9ac3900987c79b726d0bb3699d8db4e Mon Sep 17 00:00:00 2001 +From: Takashi Iwai +Date: Fri, 2 Apr 2021 10:23:17 +0200 +Subject: drm/i915: Fix invalid access to ACPI _DSM objects +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Takashi Iwai + +commit b6a37a93c9ac3900987c79b726d0bb3699d8db4e upstream. + +intel_dsm_platform_mux_info() tries to parse the ACPI package data +from _DSM for the debug information, but it assumes the fixed format +without checking what values are stored in the elements actually. +When an unexpected value is returned from BIOS, it may lead to GPF or +NULL dereference, as reported recently. + +Add the checks of the contents in the returned values and skip the +values for invalid cases. + +v1->v2: Check the info contents before dereferencing, too + +BugLink: http://bugzilla.opensuse.org/show_bug.cgi?id=1184074 +Cc: +Signed-off-by: Takashi Iwai +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20210402082317.871-1-tiwai@suse.de +(cherry picked from commit 337d7a1621c7f02af867229990ac67c97da1b53a) +Signed-off-by: Rodrigo Vivi +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_acpi.c | 22 ++++++++++++++++++++-- + 1 file changed, 20 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/display/intel_acpi.c ++++ b/drivers/gpu/drm/i915/display/intel_acpi.c +@@ -83,13 +83,31 @@ static void intel_dsm_platform_mux_info( + return; + } + ++ if (!pkg->package.count) { ++ DRM_DEBUG_DRIVER("no connection in _DSM\n"); ++ return; ++ } ++ + connector_count = &pkg->package.elements[0]; + DRM_DEBUG_DRIVER("MUX info connectors: %lld\n", + (unsigned long long)connector_count->integer.value); + for (i = 1; i < pkg->package.count; i++) { + union acpi_object *obj = &pkg->package.elements[i]; +- union acpi_object *connector_id = &obj->package.elements[0]; +- union acpi_object *info = &obj->package.elements[1]; ++ union acpi_object *connector_id; ++ union acpi_object *info; ++ ++ if (obj->type != ACPI_TYPE_PACKAGE || obj->package.count < 2) { ++ DRM_DEBUG_DRIVER("Invalid object for MUX #%d\n", i); ++ continue; ++ } ++ ++ connector_id = &obj->package.elements[0]; ++ info = &obj->package.elements[1]; ++ if (info->type != ACPI_TYPE_BUFFER || info->buffer.length < 4) { ++ DRM_DEBUG_DRIVER("Invalid info for MUX obj #%d\n", i); ++ continue; ++ } ++ + DRM_DEBUG_DRIVER("Connector id: 0x%016llx\n", + (unsigned long long)connector_id->integer.value); + DRM_DEBUG_DRIVER(" port id: %s\n", diff --git a/queue-5.4/fs-direct-io-fix-missing-sdio-boundary.patch b/queue-5.4/fs-direct-io-fix-missing-sdio-boundary.patch new file mode 100644 index 00000000000..38a153154da --- /dev/null +++ b/queue-5.4/fs-direct-io-fix-missing-sdio-boundary.patch @@ -0,0 +1,58 @@ +From df41872b68601059dd4a84858952dcae58acd331 Mon Sep 17 00:00:00 2001 +From: Jack Qiu +Date: Fri, 9 Apr 2021 13:27:35 -0700 +Subject: fs: direct-io: fix missing sdio->boundary + +From: Jack Qiu + +commit df41872b68601059dd4a84858952dcae58acd331 upstream. + +I encountered a hung task issue, but not a performance one. I run DIO +on a device (need lba continuous, for example open channel ssd), maybe +hungtask in below case: + + DIO: Checkpoint: + get addr A(at boundary), merge into BIO, + no submit because boundary missing + flush dirty data(get addr A+1), wait IO(A+1) + writeback timeout, because DIO(A) didn't submit + get addr A+2 fail, because checkpoint is doing + +dio_send_cur_page() may clear sdio->boundary, so prevent it from missing +a boundary. + +Link: https://lkml.kernel.org/r/20210322042253.38312-1-jack.qiu@huawei.com +Fixes: b1058b981272 ("direct-io: submit bio after boundary buffer is added to it") +Signed-off-by: Jack Qiu +Reviewed-by: Jan Kara +Cc: +Signed-off-by: Andrew Morton +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman +--- + fs/direct-io.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/fs/direct-io.c ++++ b/fs/direct-io.c +@@ -848,6 +848,7 @@ submit_page_section(struct dio *dio, str + struct buffer_head *map_bh) + { + int ret = 0; ++ int boundary = sdio->boundary; /* dio_send_cur_page may clear it */ + + if (dio->op == REQ_OP_WRITE) { + /* +@@ -886,10 +887,10 @@ submit_page_section(struct dio *dio, str + sdio->cur_page_fs_offset = sdio->block_in_file << sdio->blkbits; + out: + /* +- * If sdio->boundary then we want to schedule the IO now to ++ * If boundary then we want to schedule the IO now to + * avoid metadata seeks. + */ +- if (sdio->boundary) { ++ if (boundary) { + ret = dio_send_cur_page(dio, sdio, map_bh); + if (sdio->bio) + dio_bio_submit(dio, sdio); diff --git a/queue-5.4/gcov-re-fix-clang-11-support.patch b/queue-5.4/gcov-re-fix-clang-11-support.patch new file mode 100644 index 00000000000..e499e688daf --- /dev/null +++ b/queue-5.4/gcov-re-fix-clang-11-support.patch @@ -0,0 +1,121 @@ +From 9562fd132985ea9185388a112e50f2a51557827d Mon Sep 17 00:00:00 2001 +From: Nick Desaulniers +Date: Fri, 9 Apr 2021 13:27:26 -0700 +Subject: gcov: re-fix clang-11+ support + +From: Nick Desaulniers + +commit 9562fd132985ea9185388a112e50f2a51557827d upstream. + +LLVM changed the expected function signature for llvm_gcda_emit_function() +in the clang-11 release. Users of clang-11 or newer may have noticed +their kernels producing invalid coverage information: + + $ llvm-cov gcov -a -c -u -f -b .gcda -- gcno=.gcno + 1 : checksum mismatch, \ + (, ) != (, ) + 2 Invalid .gcda File! + ... + +Fix up the function signatures so calling this function interprets its +parameters correctly and computes the correct cfg checksum. In +particular, in clang-11, the additional checksum is no longer optional. + +Link: https://reviews.llvm.org/rG25544ce2df0daa4304c07e64b9c8b0f7df60c11d +Link: https://lkml.kernel.org/r/20210408184631.1156669-1-ndesaulniers@google.com +Reported-by: Prasad Sodagudi +Tested-by: Prasad Sodagudi +Signed-off-by: Nick Desaulniers +Reviewed-by: Nathan Chancellor +Cc: [5.4+] +Signed-off-by: Greg Kroah-Hartman + +Signed-off-by: Andrew Morton +Signed-off-by: Linus Torvalds +--- + kernel/gcov/clang.c | 29 +++++++++++++++++++---------- + 1 file changed, 19 insertions(+), 10 deletions(-) + +--- a/kernel/gcov/clang.c ++++ b/kernel/gcov/clang.c +@@ -70,7 +70,9 @@ struct gcov_fn_info { + + u32 ident; + u32 checksum; ++#if CONFIG_CLANG_VERSION < 110000 + u8 use_extra_checksum; ++#endif + u32 cfg_checksum; + + u32 num_counters; +@@ -145,10 +147,8 @@ void llvm_gcda_emit_function(u32 ident, + + list_add_tail(&info->head, ¤t_info->functions); + } +-EXPORT_SYMBOL(llvm_gcda_emit_function); + #else +-void llvm_gcda_emit_function(u32 ident, u32 func_checksum, +- u8 use_extra_checksum, u32 cfg_checksum) ++void llvm_gcda_emit_function(u32 ident, u32 func_checksum, u32 cfg_checksum) + { + struct gcov_fn_info *info = kzalloc(sizeof(*info), GFP_KERNEL); + +@@ -158,12 +158,11 @@ void llvm_gcda_emit_function(u32 ident, + INIT_LIST_HEAD(&info->head); + info->ident = ident; + info->checksum = func_checksum; +- info->use_extra_checksum = use_extra_checksum; + info->cfg_checksum = cfg_checksum; + list_add_tail(&info->head, ¤t_info->functions); + } +-EXPORT_SYMBOL(llvm_gcda_emit_function); + #endif ++EXPORT_SYMBOL(llvm_gcda_emit_function); + + void llvm_gcda_emit_arcs(u32 num_counters, u64 *counters) + { +@@ -293,11 +292,16 @@ int gcov_info_is_compatible(struct gcov_ + !list_is_last(&fn_ptr2->head, &info2->functions)) { + if (fn_ptr1->checksum != fn_ptr2->checksum) + return false; ++#if CONFIG_CLANG_VERSION < 110000 + if (fn_ptr1->use_extra_checksum != fn_ptr2->use_extra_checksum) + return false; + if (fn_ptr1->use_extra_checksum && + fn_ptr1->cfg_checksum != fn_ptr2->cfg_checksum) + return false; ++#else ++ if (fn_ptr1->cfg_checksum != fn_ptr2->cfg_checksum) ++ return false; ++#endif + fn_ptr1 = list_next_entry(fn_ptr1, head); + fn_ptr2 = list_next_entry(fn_ptr2, head); + } +@@ -529,17 +533,22 @@ static size_t convert_to_gcda(char *buff + + list_for_each_entry(fi_ptr, &info->functions, head) { + u32 i; +- u32 len = 2; +- +- if (fi_ptr->use_extra_checksum) +- len++; + + pos += store_gcov_u32(buffer, pos, GCOV_TAG_FUNCTION); +- pos += store_gcov_u32(buffer, pos, len); ++#if CONFIG_CLANG_VERSION < 110000 ++ pos += store_gcov_u32(buffer, pos, ++ fi_ptr->use_extra_checksum ? 3 : 2); ++#else ++ pos += store_gcov_u32(buffer, pos, 3); ++#endif + pos += store_gcov_u32(buffer, pos, fi_ptr->ident); + pos += store_gcov_u32(buffer, pos, fi_ptr->checksum); ++#if CONFIG_CLANG_VERSION < 110000 + if (fi_ptr->use_extra_checksum) + pos += store_gcov_u32(buffer, pos, fi_ptr->cfg_checksum); ++#else ++ pos += store_gcov_u32(buffer, pos, fi_ptr->cfg_checksum); ++#endif + + pos += store_gcov_u32(buffer, pos, GCOV_TAG_COUNTER_BASE); + pos += store_gcov_u32(buffer, pos, fi_ptr->num_counters * 2); diff --git a/queue-5.4/ia64-fix-user_stack_pointer-for-ptrace.patch b/queue-5.4/ia64-fix-user_stack_pointer-for-ptrace.patch new file mode 100644 index 00000000000..47e88538e3e --- /dev/null +++ b/queue-5.4/ia64-fix-user_stack_pointer-for-ptrace.patch @@ -0,0 +1,71 @@ +From 7ad1e366167837daeb93d0bacb57dee820b0b898 Mon Sep 17 00:00:00 2001 +From: Sergei Trofimovich +Date: Fri, 9 Apr 2021 13:27:32 -0700 +Subject: ia64: fix user_stack_pointer() for ptrace() + +From: Sergei Trofimovich + +commit 7ad1e366167837daeb93d0bacb57dee820b0b898 upstream. + +ia64 has two stacks: + + - memory stack (or stack), pointed at by by r12 + + - register backing store (register stack), pointed at by + ar.bsp/ar.bspstore with complications around dirty + register frame on CPU. + +In [1] Dmitry noticed that PTRACE_GET_SYSCALL_INFO returns the register +stack instead memory stack. + +The bug comes from the fact that user_stack_pointer() and +current_user_stack_pointer() don't return the same register: + + ulong user_stack_pointer(struct pt_regs *regs) { return regs->ar_bspstore; } + #define current_user_stack_pointer() (current_pt_regs()->r12) + +The change gets both back in sync. + +I think ptrace(PTRACE_GET_SYSCALL_INFO) is the only affected user by +this bug on ia64. + +The change fixes 'rt_sigreturn.gen.test' strace test where it was +observed initially. + +Link: https://bugs.gentoo.org/769614 [1] +Link: https://lkml.kernel.org/r/20210331084447.2561532-1-slyfox@gentoo.org +Signed-off-by: Sergei Trofimovich +Reported-by: Dmitry V. Levin +Cc: Oleg Nesterov +Cc: +Signed-off-by: Andrew Morton +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman +--- + arch/ia64/include/asm/ptrace.h | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +--- a/arch/ia64/include/asm/ptrace.h ++++ b/arch/ia64/include/asm/ptrace.h +@@ -54,8 +54,7 @@ + + static inline unsigned long user_stack_pointer(struct pt_regs *regs) + { +- /* FIXME: should this be bspstore + nr_dirty regs? */ +- return regs->ar_bspstore; ++ return regs->r12; + } + + static inline int is_syscall_success(struct pt_regs *regs) +@@ -79,11 +78,6 @@ static inline long regs_return_value(str + unsigned long __ip = instruction_pointer(regs); \ + (__ip & ~3UL) + ((__ip & 3UL) << 2); \ + }) +-/* +- * Why not default? Because user_stack_pointer() on ia64 gives register +- * stack backing store instead... +- */ +-#define current_user_stack_pointer() (current_pt_regs()->r12) + + /* given a pointer to a task_struct, return the user's pt_regs */ + # define task_pt_regs(t) (((struct pt_regs *) ((char *) (t) + IA64_STK_OFFSET)) - 1) diff --git a/queue-5.4/nds32-flush_dcache_page-use-page_mapping_file-to-avoid-races-with-swapoff.patch b/queue-5.4/nds32-flush_dcache_page-use-page_mapping_file-to-avoid-races-with-swapoff.patch new file mode 100644 index 00000000000..9e21412c361 --- /dev/null +++ b/queue-5.4/nds32-flush_dcache_page-use-page_mapping_file-to-avoid-races-with-swapoff.patch @@ -0,0 +1,47 @@ +From a3a8833dffb7e7329c2586b8bfc531adb503f123 Mon Sep 17 00:00:00 2001 +From: Mike Rapoport +Date: Fri, 9 Apr 2021 13:27:23 -0700 +Subject: nds32: flush_dcache_page: use page_mapping_file to avoid races with swapoff + +From: Mike Rapoport + +commit a3a8833dffb7e7329c2586b8bfc531adb503f123 upstream. + +Commit cb9f753a3731 ("mm: fix races between swapoff and flush dcache") +updated flush_dcache_page implementations on several architectures to +use page_mapping_file() in order to avoid races between page_mapping() +and swapoff(). + +This update missed arch/nds32 and there is a possibility of a race +there. + +Replace page_mapping() with page_mapping_file() in nds32 implementation +of flush_dcache_page(). + +Link: https://lkml.kernel.org/r/20210330175126.26500-1-rppt@kernel.org +Fixes: cb9f753a3731 ("mm: fix races between swapoff and flush dcache") +Signed-off-by: Mike Rapoport +Reviewed-by: Matthew Wilcox (Oracle) +Acked-by: Greentime Hu +Cc: Huang Ying +Cc: Nick Hu +Cc: Vincent Chen +Cc: +Signed-off-by: Andrew Morton +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman +--- + arch/nds32/mm/cacheflush.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/nds32/mm/cacheflush.c ++++ b/arch/nds32/mm/cacheflush.c +@@ -239,7 +239,7 @@ void flush_dcache_page(struct page *page + { + struct address_space *mapping; + +- mapping = page_mapping(page); ++ mapping = page_mapping_file(page); + if (mapping && !mapping_mapped(mapping)) + set_bit(PG_dcache_dirty, &page->flags); + else { diff --git a/queue-5.4/net-dsa-lantiq_gswip-configure-all-remaining-gswip_mii_cfg-bits.patch b/queue-5.4/net-dsa-lantiq_gswip-configure-all-remaining-gswip_mii_cfg-bits.patch new file mode 100644 index 00000000000..fda26aa4f3e --- /dev/null +++ b/queue-5.4/net-dsa-lantiq_gswip-configure-all-remaining-gswip_mii_cfg-bits.patch @@ -0,0 +1,93 @@ +From 4b5923249b8fa427943b50b8f35265176472be38 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Thu, 8 Apr 2021 20:38:28 +0200 +Subject: net: dsa: lantiq_gswip: Configure all remaining GSWIP_MII_CFG bits + +From: Martin Blumenstingl + +commit 4b5923249b8fa427943b50b8f35265176472be38 upstream. + +There are a few more bits in the GSWIP_MII_CFG register for which we +did rely on the boot-loader (or the hardware defaults) to set them up +properly. + +For some external RMII PHYs we need to select the GSWIP_MII_CFG_RMII_CLK +bit and also we should un-set it for non-RMII PHYs. The +GSWIP_MII_CFG_RMII_CLK bit is ignored for other PHY connection modes. + +The GSWIP IP also supports in-band auto-negotiation for RGMII PHYs when +the GSWIP_MII_CFG_RGMII_IBS bit is set. Clear this bit always as there's +no known hardware which uses this (so it is not tested yet). + +Clear the xMII isolation bit when set at initialization time if it was +previously set by the bootloader. Not doing so could lead to no traffic +(neither RX nor TX) on a port with this bit set. + +While here, also add the GSWIP_MII_CFG_RESET bit. We don't need to +manage it because this bit is self-clearning when set. We still add it +here to get a better overview of the GSWIP_MII_CFG register. + +Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") +Cc: stable@vger.kernel.org +Suggested-by: Hauke Mehrtens +Acked-by: Hauke Mehrtens +Signed-off-by: Martin Blumenstingl +Reviewed-by: Florian Fainelli +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman +--- + drivers/net/dsa/lantiq_gswip.c | 19 ++++++++++++++++--- + 1 file changed, 16 insertions(+), 3 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -93,8 +93,12 @@ + + /* GSWIP MII Registers */ + #define GSWIP_MII_CFGp(p) (0x2 * (p)) ++#define GSWIP_MII_CFG_RESET BIT(15) + #define GSWIP_MII_CFG_EN BIT(14) ++#define GSWIP_MII_CFG_ISOLATE BIT(13) + #define GSWIP_MII_CFG_LDCLKDIS BIT(12) ++#define GSWIP_MII_CFG_RGMII_IBS BIT(8) ++#define GSWIP_MII_CFG_RMII_CLK BIT(7) + #define GSWIP_MII_CFG_MODE_MIIP 0x0 + #define GSWIP_MII_CFG_MODE_MIIM 0x1 + #define GSWIP_MII_CFG_MODE_RMIIP 0x2 +@@ -817,9 +821,11 @@ static int gswip_setup(struct dsa_switch + /* Configure the MDIO Clock 2.5 MHz */ + gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); + +- /* Disable the xMII link */ ++ /* Disable the xMII interface and clear it's isolation bit */ + for (i = 0; i < priv->hw_info->max_ports; i++) +- gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, i); ++ gswip_mii_mask_cfg(priv, ++ GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE, ++ 0, i); + + /* enable special tag insertion on cpu port */ + gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, +@@ -1594,6 +1600,9 @@ static void gswip_phylink_mac_config(str + break; + case PHY_INTERFACE_MODE_RMII: + miicfg |= GSWIP_MII_CFG_MODE_RMIIM; ++ ++ /* Configure the RMII clock as output: */ ++ miicfg |= GSWIP_MII_CFG_RMII_CLK; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: +@@ -1606,7 +1615,11 @@ static void gswip_phylink_mac_config(str + "Unsupported interface: %d\n", state->interface); + return; + } +- gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_MODE_MASK, miicfg, port); ++ ++ gswip_mii_mask_cfg(priv, ++ GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK | ++ GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS, ++ miicfg, port); + + switch (state->interface) { + case PHY_INTERFACE_MODE_RGMII_ID: diff --git a/queue-5.4/net-dsa-lantiq_gswip-don-t-use-phy-auto-polling.patch b/queue-5.4/net-dsa-lantiq_gswip-don-t-use-phy-auto-polling.patch new file mode 100644 index 00000000000..06d4c3eecdb --- /dev/null +++ b/queue-5.4/net-dsa-lantiq_gswip-don-t-use-phy-auto-polling.patch @@ -0,0 +1,317 @@ +From 3e9005be87777afc902b9f5497495898202d335d Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Thu, 8 Apr 2021 20:38:27 +0200 +Subject: net: dsa: lantiq_gswip: Don't use PHY auto polling + +From: Martin Blumenstingl + +commit 3e9005be87777afc902b9f5497495898202d335d upstream. + +PHY auto polling on the GSWIP hardware can be used so link changes +(speed, link up/down, etc.) can be detected automatically. Internally +GSWIP reads the PHY's registers for this functionality. Based on this +automatic detection GSWIP can also automatically re-configure it's port +settings. Unfortunately this auto polling (and configuration) mechanism +seems to cause various issues observed by different people on different +devices: +- FritzBox 7360v2: the two Gbit/s ports (connected to the two internal + PHY11G instances) are working fine but the two Fast Ethernet ports + (using an AR8030 RMII PHY) are completely dead (neither RX nor TX are + received). It turns out that the AR8030 PHY sets the BMSR_ESTATEN bit + as well as the ESTATUS_1000_TFULL and ESTATUS_1000_XFULL bits. This + makes the PHY auto polling state machine (rightfully?) think that the + established link speed (when the other side is Gbit/s capable) is + 1Gbit/s. +- None of the Ethernet ports on the Zyxel P-2812HNU-F1 (two are + connected to the internal PHY11G GPHYs while the other three are + external RGMII PHYs) are working. Neither RX nor TX traffic was + observed. It is not clear which part of the PHY auto polling state- + machine caused this. +- FritzBox 7412 (only one LAN port which is connected to one of the + internal GPHYs running in PHY22F / Fast Ethernet mode) was seeing + random disconnects (link down events could be seen). Sometimes all + traffic would stop after such disconnect. It is not clear which part + of the PHY auto polling state-machine cauased this. +- TP-Link TD-W9980 (two ports are connected to the internal GPHYs + running in PHY11G / Gbit/s mode, the other two are external RGMII + PHYs) was affected by similar issues as the FritzBox 7412 just without + the "link down" events + +Switch to software based configuration instead of PHY auto polling (and +letting the GSWIP hardware configure the ports automatically) for the +following link parameters: +- link up/down +- link speed +- full/half duplex +- flow control (RX / TX pause) + +After a big round of manual testing by various people (who helped test +this on OpenWrt) it turns out that this fixes all reported issues. + +Additionally it can be considered more future proof because any +"quirk" which is implemented for a PHY on the driver side can now be +used with the GSWIP hardware as well because Linux is in control of the +link parameters. + +As a nice side-effect this also solves a problem where fixed-links were +not supported previously because we were relying on the PHY auto polling +mechanism, which cannot work for fixed-links as there's no PHY from +where it can read the registers. Configuring the link settings on the +GSWIP ports means that we now use the settings from device-tree also for +ports with fixed-links. + +Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") +Fixes: 3e6fdeb28f4c33 ("net: dsa: lantiq_gswip: Let GSWIP automatically set the xMII clock") +Cc: stable@vger.kernel.org +Acked-by: Hauke Mehrtens +Reviewed-by: Andrew Lunn +Signed-off-by: Martin Blumenstingl +Reviewed-by: Florian Fainelli +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman +--- + drivers/net/dsa/lantiq_gswip.c | 185 +++++++++++++++++++++++++++++++++++------ + 1 file changed, 159 insertions(+), 26 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -190,6 +190,23 @@ + #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA)) + + #define GSWIP_MAC_FLEN 0x8C5 ++#define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC)) ++#define GSWIP_MAC_CTRL_0_PADEN BIT(8) ++#define GSWIP_MAC_CTRL_0_FCS_EN BIT(7) ++#define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070 ++#define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000 ++#define GSWIP_MAC_CTRL_0_FCON_RX 0x0010 ++#define GSWIP_MAC_CTRL_0_FCON_TX 0x0020 ++#define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030 ++#define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040 ++#define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C ++#define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000 ++#define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004 ++#define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C ++#define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003 ++#define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000 ++#define GSWIP_MAC_CTRL_0_GMII_MII 0x0001 ++#define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002 + #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) + #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ + +@@ -653,16 +670,13 @@ static int gswip_port_enable(struct dsa_ + GSWIP_SDMA_PCTRLp(port)); + + if (!dsa_is_cpu_port(ds, port)) { +- u32 macconf = GSWIP_MDIO_PHY_LINK_AUTO | +- GSWIP_MDIO_PHY_SPEED_AUTO | +- GSWIP_MDIO_PHY_FDUP_AUTO | +- GSWIP_MDIO_PHY_FCONTX_AUTO | +- GSWIP_MDIO_PHY_FCONRX_AUTO | +- (phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK); +- +- gswip_mdio_w(priv, macconf, GSWIP_MDIO_PHYp(port)); +- /* Activate MDIO auto polling */ +- gswip_mdio_mask(priv, 0, BIT(port), GSWIP_MDIO_MDC_CFG0); ++ u32 mdio_phy = 0; ++ ++ if (phydev) ++ mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; ++ ++ gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy, ++ GSWIP_MDIO_PHYp(port)); + } + + return 0; +@@ -675,14 +689,6 @@ static void gswip_port_disable(struct ds + if (!dsa_is_user_port(ds, port)) + return; + +- if (!dsa_is_cpu_port(ds, port)) { +- gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_DOWN, +- GSWIP_MDIO_PHY_LINK_MASK, +- GSWIP_MDIO_PHYp(port)); +- /* Deactivate MDIO auto polling */ +- gswip_mdio_mask(priv, BIT(port), 0, GSWIP_MDIO_MDC_CFG0); +- } +- + gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, + GSWIP_FDMA_PCTRLp(port)); + gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, +@@ -790,20 +796,31 @@ static int gswip_setup(struct dsa_switch + gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2); + gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3); + +- /* disable PHY auto polling */ ++ /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an ++ * interoperability problem with this auto polling mechanism because ++ * their status registers think that the link is in a different state ++ * than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set ++ * as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the ++ * auto polling state machine consider the link being negotiated with ++ * 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads ++ * to the switch port being completely dead (RX and TX are both not ++ * working). ++ * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F ++ * GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes ++ * it would work fine for a few minutes to hours and then stop, on ++ * other device it would no traffic could be sent or received at all. ++ * Testing shows that when PHY auto polling is disabled these problems ++ * go away. ++ */ + gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0); ++ + /* Configure the MDIO Clock 2.5 MHz */ + gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); + +- for (i = 0; i < priv->hw_info->max_ports; i++) { +- /* Disable the xMII link */ ++ /* Disable the xMII link */ ++ for (i = 0; i < priv->hw_info->max_ports; i++) + gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, i); + +- /* Automatically select the xMII interface clock */ +- gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, +- GSWIP_MII_CFG_RATE_AUTO, i); +- } +- + /* enable special tag insertion on cpu port */ + gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, + GSWIP_FDMA_PCTRLp(cpu_port)); +@@ -1452,6 +1469,112 @@ unsupported: + return; + } + ++static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link) ++{ ++ u32 mdio_phy; ++ ++ if (link) ++ mdio_phy = GSWIP_MDIO_PHY_LINK_UP; ++ else ++ mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN; ++ ++ gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy, ++ GSWIP_MDIO_PHYp(port)); ++} ++ ++static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed, ++ phy_interface_t interface) ++{ ++ u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0; ++ ++ switch (speed) { ++ case SPEED_10: ++ mdio_phy = GSWIP_MDIO_PHY_SPEED_M10; ++ ++ if (interface == PHY_INTERFACE_MODE_RMII) ++ mii_cfg = GSWIP_MII_CFG_RATE_M50; ++ else ++ mii_cfg = GSWIP_MII_CFG_RATE_M2P5; ++ ++ mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; ++ break; ++ ++ case SPEED_100: ++ mdio_phy = GSWIP_MDIO_PHY_SPEED_M100; ++ ++ if (interface == PHY_INTERFACE_MODE_RMII) ++ mii_cfg = GSWIP_MII_CFG_RATE_M50; ++ else ++ mii_cfg = GSWIP_MII_CFG_RATE_M25; ++ ++ mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; ++ break; ++ ++ case SPEED_1000: ++ mdio_phy = GSWIP_MDIO_PHY_SPEED_G1; ++ ++ mii_cfg = GSWIP_MII_CFG_RATE_M125; ++ ++ mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII; ++ break; ++ } ++ ++ gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy, ++ GSWIP_MDIO_PHYp(port)); ++ gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port); ++ gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0, ++ GSWIP_MAC_CTRL_0p(port)); ++} ++ ++static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex) ++{ ++ u32 mac_ctrl_0, mdio_phy; ++ ++ if (duplex == DUPLEX_FULL) { ++ mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN; ++ mdio_phy = GSWIP_MDIO_PHY_FDUP_EN; ++ } else { ++ mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS; ++ mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS; ++ } ++ ++ gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0, ++ GSWIP_MAC_CTRL_0p(port)); ++ gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy, ++ GSWIP_MDIO_PHYp(port)); ++} ++ ++static void gswip_port_set_pause(struct gswip_priv *priv, int port, ++ bool tx_pause, bool rx_pause) ++{ ++ u32 mac_ctrl_0, mdio_phy; ++ ++ if (tx_pause && rx_pause) { ++ mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX; ++ mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | ++ GSWIP_MDIO_PHY_FCONRX_EN; ++ } else if (tx_pause) { ++ mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX; ++ mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | ++ GSWIP_MDIO_PHY_FCONRX_DIS; ++ } else if (rx_pause) { ++ mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX; ++ mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | ++ GSWIP_MDIO_PHY_FCONRX_EN; ++ } else { ++ mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE; ++ mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | ++ GSWIP_MDIO_PHY_FCONRX_DIS; ++ } ++ ++ gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK, ++ mac_ctrl_0, GSWIP_MAC_CTRL_0p(port)); ++ gswip_mdio_mask(priv, ++ GSWIP_MDIO_PHY_FCONTX_MASK | ++ GSWIP_MDIO_PHY_FCONRX_MASK, ++ mdio_phy, GSWIP_MDIO_PHYp(port)); ++} ++ + static void gswip_phylink_mac_config(struct dsa_switch *ds, int port, + unsigned int mode, + const struct phylink_link_state *state) +@@ -1508,6 +1631,9 @@ static void gswip_phylink_mac_link_down( + struct gswip_priv *priv = ds->priv; + + gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port); ++ ++ if (!dsa_is_cpu_port(ds, port)) ++ gswip_port_set_link(priv, port, false); + } + + static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port, +@@ -1517,6 +1643,13 @@ static void gswip_phylink_mac_link_up(st + { + struct gswip_priv *priv = ds->priv; + ++ if (!dsa_is_cpu_port(ds, port)) { ++ gswip_port_set_link(priv, port, true); ++ gswip_port_set_speed(priv, port, speed, interface); ++ gswip_port_set_duplex(priv, port, duplex); ++ gswip_port_set_pause(priv, port, tx_pause, rx_pause); ++ } ++ + gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); + } + diff --git a/queue-5.4/net-dsa-lantiq_gswip-let-gswip-automatically-set-the-xmii-clock.patch b/queue-5.4/net-dsa-lantiq_gswip-let-gswip-automatically-set-the-xmii-clock.patch new file mode 100644 index 00000000000..7ac5ad851c4 --- /dev/null +++ b/queue-5.4/net-dsa-lantiq_gswip-let-gswip-automatically-set-the-xmii-clock.patch @@ -0,0 +1,47 @@ +From 3e6fdeb28f4c331acbd27bdb0effc4befd4ef8e8 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Wed, 24 Mar 2021 20:36:04 +0100 +Subject: net: dsa: lantiq_gswip: Let GSWIP automatically set the xMII clock + +From: Martin Blumenstingl + +commit 3e6fdeb28f4c331acbd27bdb0effc4befd4ef8e8 upstream. + +The xMII interface clock depends on the PHY interface (MII, RMII, RGMII) +as well as the current link speed. Explicitly configure the GSWIP to +automatically select the appropriate xMII interface clock. + +This fixes an issue seen by some users where ports using an external +RMII or RGMII PHY were deaf (no RX or TX traffic could be seen). Most +likely this is due to an "invalid" xMII clock being selected either by +the bootloader or hardware-defaults. + +Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") +Signed-off-by: Martin Blumenstingl +Reviewed-by: Florian Fainelli +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman +--- + drivers/net/dsa/lantiq_gswip.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -795,10 +795,15 @@ static int gswip_setup(struct dsa_switch + /* Configure the MDIO Clock 2.5 MHz */ + gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); + +- /* Disable the xMII link */ +- for (i = 0; i < priv->hw_info->max_ports; i++) ++ for (i = 0; i < priv->hw_info->max_ports; i++) { ++ /* Disable the xMII link */ + gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, i); + ++ /* Automatically select the xMII interface clock */ ++ gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, ++ GSWIP_MII_CFG_RATE_AUTO, i); ++ } ++ + /* enable special tag insertion on cpu port */ + gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, + GSWIP_FDMA_PCTRLp(cpu_port)); diff --git a/queue-5.4/net-ipv6-check-for-validity-before-dereferencing-cfg-fc_nlinfo.nlh.patch b/queue-5.4/net-ipv6-check-for-validity-before-dereferencing-cfg-fc_nlinfo.nlh.patch new file mode 100644 index 00000000000..45163f72d26 --- /dev/null +++ b/queue-5.4/net-ipv6-check-for-validity-before-dereferencing-cfg-fc_nlinfo.nlh.patch @@ -0,0 +1,39 @@ +From 864db232dc7036aa2de19749c3d5be0143b24f8f Mon Sep 17 00:00:00 2001 +From: Muhammad Usama Anjum +Date: Fri, 9 Apr 2021 03:01:29 +0500 +Subject: net: ipv6: check for validity before dereferencing cfg->fc_nlinfo.nlh + +From: Muhammad Usama Anjum + +commit 864db232dc7036aa2de19749c3d5be0143b24f8f upstream. + +nlh is being checked for validtity two times when it is dereferenced in +this function. Check for validity again when updating the flags through +nlh pointer to make the dereferencing safe. + +CC: +Addresses-Coverity: ("NULL pointer dereference") +Signed-off-by: Muhammad Usama Anjum +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman +--- + net/ipv6/route.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +--- a/net/ipv6/route.c ++++ b/net/ipv6/route.c +@@ -5183,9 +5183,11 @@ static int ip6_route_multipath_add(struc + * nexthops have been replaced by first new, the rest should + * be added to it. + */ +- cfg->fc_nlinfo.nlh->nlmsg_flags &= ~(NLM_F_EXCL | +- NLM_F_REPLACE); +- cfg->fc_nlinfo.nlh->nlmsg_flags |= NLM_F_CREATE; ++ if (cfg->fc_nlinfo.nlh) { ++ cfg->fc_nlinfo.nlh->nlmsg_flags &= ~(NLM_F_EXCL | ++ NLM_F_REPLACE); ++ cfg->fc_nlinfo.nlh->nlmsg_flags |= NLM_F_CREATE; ++ } + nhn++; + } + diff --git a/queue-5.4/ocfs2-fix-deadlock-between-setattr-and-dio_end_io_write.patch b/queue-5.4/ocfs2-fix-deadlock-between-setattr-and-dio_end_io_write.patch new file mode 100644 index 00000000000..353737b0d8b --- /dev/null +++ b/queue-5.4/ocfs2-fix-deadlock-between-setattr-and-dio_end_io_write.patch @@ -0,0 +1,148 @@ +From 90bd070aae6c4fb5d302f9c4b9c88be60c8197ec Mon Sep 17 00:00:00 2001 +From: Wengang Wang +Date: Fri, 9 Apr 2021 13:27:29 -0700 +Subject: ocfs2: fix deadlock between setattr and dio_end_io_write + +From: Wengang Wang + +commit 90bd070aae6c4fb5d302f9c4b9c88be60c8197ec upstream. + +The following deadlock is detected: + + truncate -> setattr path is waiting for pending direct IO to be done (inode->i_dio_count become zero) with inode->i_rwsem held (down_write). + + PID: 14827 TASK: ffff881686a9af80 CPU: 20 COMMAND: "ora_p005_hrltd9" + #0 __schedule at ffffffff818667cc + #1 schedule at ffffffff81866de6 + #2 inode_dio_wait at ffffffff812a2d04 + #3 ocfs2_setattr at ffffffffc05f322e [ocfs2] + #4 notify_change at ffffffff812a5a09 + #5 do_truncate at ffffffff812808f5 + #6 do_sys_ftruncate.constprop.18 at ffffffff81280cf2 + #7 sys_ftruncate at ffffffff81280d8e + #8 do_syscall_64 at ffffffff81003949 + #9 entry_SYSCALL_64_after_hwframe at ffffffff81a001ad + +dio completion path is going to complete one direct IO (decrement +inode->i_dio_count), but before that it hung at locking inode->i_rwsem: + + #0 __schedule+700 at ffffffff818667cc + #1 schedule+54 at ffffffff81866de6 + #2 rwsem_down_write_failed+536 at ffffffff8186aa28 + #3 call_rwsem_down_write_failed+23 at ffffffff8185a1b7 + #4 down_write+45 at ffffffff81869c9d + #5 ocfs2_dio_end_io_write+180 at ffffffffc05d5444 [ocfs2] + #6 ocfs2_dio_end_io+85 at ffffffffc05d5a85 [ocfs2] + #7 dio_complete+140 at ffffffff812c873c + #8 dio_aio_complete_work+25 at ffffffff812c89f9 + #9 process_one_work+361 at ffffffff810b1889 + #10 worker_thread+77 at ffffffff810b233d + #11 kthread+261 at ffffffff810b7fd5 + #12 ret_from_fork+62 at ffffffff81a0035e + +Thus above forms ABBA deadlock. The same deadlock was mentioned in +upstream commit 28f5a8a7c033 ("ocfs2: should wait dio before inode lock +in ocfs2_setattr()"). It seems that that commit only removed the +cluster lock (the victim of above dead lock) from the ABBA deadlock +party. + +End-user visible effects: Process hang in truncate -> ocfs2_setattr path +and other processes hang at ocfs2_dio_end_io_write path. + +This is to fix the deadlock itself. It removes inode_lock() call from +dio completion path to remove the deadlock and add ip_alloc_sem lock in +setattr path to synchronize the inode modifications. + +[wen.gang.wang@oracle.com: remove the "had_alloc_lock" as suggested] + Link: https://lkml.kernel.org/r/20210402171344.1605-1-wen.gang.wang@oracle.com + +Link: https://lkml.kernel.org/r/20210331203654.3911-1-wen.gang.wang@oracle.com +Signed-off-by: Wengang Wang +Reviewed-by: Joseph Qi +Cc: Mark Fasheh +Cc: Joel Becker +Cc: Junxiao Bi +Cc: Changwei Ge +Cc: Gang He +Cc: Jun Piao +Cc: +Signed-off-by: Andrew Morton +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman +--- + fs/ocfs2/aops.c | 11 +---------- + fs/ocfs2/file.c | 8 ++++++-- + 2 files changed, 7 insertions(+), 12 deletions(-) + +--- a/fs/ocfs2/aops.c ++++ b/fs/ocfs2/aops.c +@@ -2304,7 +2304,7 @@ static int ocfs2_dio_end_io_write(struct + struct ocfs2_alloc_context *meta_ac = NULL; + handle_t *handle = NULL; + loff_t end = offset + bytes; +- int ret = 0, credits = 0, locked = 0; ++ int ret = 0, credits = 0; + + ocfs2_init_dealloc_ctxt(&dealloc); + +@@ -2315,13 +2315,6 @@ static int ocfs2_dio_end_io_write(struct + !dwc->dw_orphaned) + goto out; + +- /* ocfs2_file_write_iter will get i_mutex, so we need not lock if we +- * are in that context. */ +- if (dwc->dw_writer_pid != task_pid_nr(current)) { +- inode_lock(inode); +- locked = 1; +- } +- + ret = ocfs2_inode_lock(inode, &di_bh, 1); + if (ret < 0) { + mlog_errno(ret); +@@ -2402,8 +2395,6 @@ out: + if (meta_ac) + ocfs2_free_alloc_context(meta_ac); + ocfs2_run_deallocs(osb, &dealloc); +- if (locked) +- inode_unlock(inode); + ocfs2_dio_free_write_ctx(inode, dwc); + + return ret; +--- a/fs/ocfs2/file.c ++++ b/fs/ocfs2/file.c +@@ -1244,22 +1244,24 @@ int ocfs2_setattr(struct dentry *dentry, + goto bail_unlock; + } + } ++ down_write(&OCFS2_I(inode)->ip_alloc_sem); + handle = ocfs2_start_trans(osb, OCFS2_INODE_UPDATE_CREDITS + + 2 * ocfs2_quota_trans_credits(sb)); + if (IS_ERR(handle)) { + status = PTR_ERR(handle); + mlog_errno(status); +- goto bail_unlock; ++ goto bail_unlock_alloc; + } + status = __dquot_transfer(inode, transfer_to); + if (status < 0) + goto bail_commit; + } else { ++ down_write(&OCFS2_I(inode)->ip_alloc_sem); + handle = ocfs2_start_trans(osb, OCFS2_INODE_UPDATE_CREDITS); + if (IS_ERR(handle)) { + status = PTR_ERR(handle); + mlog_errno(status); +- goto bail_unlock; ++ goto bail_unlock_alloc; + } + } + +@@ -1272,6 +1274,8 @@ int ocfs2_setattr(struct dentry *dentry, + + bail_commit: + ocfs2_commit_trans(osb, handle); ++bail_unlock_alloc: ++ up_write(&OCFS2_I(inode)->ip_alloc_sem); + bail_unlock: + if (status && inode_locked) { + ocfs2_inode_unlock_tracker(inode, 1, &oh, had_lock); diff --git a/queue-5.4/parisc-avoid-a-warning-on-u8-cast-for-cmpxchg-on-u8-pointers.patch b/queue-5.4/parisc-avoid-a-warning-on-u8-cast-for-cmpxchg-on-u8-pointers.patch new file mode 100644 index 00000000000..2ccd258ff37 --- /dev/null +++ b/queue-5.4/parisc-avoid-a-warning-on-u8-cast-for-cmpxchg-on-u8-pointers.patch @@ -0,0 +1,41 @@ +From 4d752e5af63753ab5140fc282929b98eaa4bd12e Mon Sep 17 00:00:00 2001 +From: Gao Xiang +Date: Tue, 6 Apr 2021 12:59:29 +0800 +Subject: parisc: avoid a warning on u8 cast for cmpxchg on u8 pointers + +From: Gao Xiang + +commit 4d752e5af63753ab5140fc282929b98eaa4bd12e upstream. + +commit b344d6a83d01 ("parisc: add support for cmpxchg on u8 pointers") +can generate a sparse warning ("cast truncates bits from constant +value"), which has been reported several times [1] [2] [3]. + +The original code worked as expected, but anyway, let silence such +sparse warning as what others did [4]. + +[1] https://lore.kernel.org/r/202104061220.nRMBwCXw-lkp@intel.com +[2] https://lore.kernel.org/r/202012291914.T5Agcn99-lkp@intel.com +[3] https://lore.kernel.org/r/202008210829.KVwn7Xeh%25lkp@intel.com +[4] https://lore.kernel.org/r/20210315131512.133720-2-jacopo+renesas@jmondi.org +Cc: Liam Beguin +Cc: Helge Deller +Cc: stable@vger.kernel.org # v5.8+ +Signed-off-by: Gao Xiang +Signed-off-by: Helge Deller +Signed-off-by: Greg Kroah-Hartman +--- + arch/parisc/include/asm/cmpxchg.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/parisc/include/asm/cmpxchg.h ++++ b/arch/parisc/include/asm/cmpxchg.h +@@ -72,7 +72,7 @@ __cmpxchg(volatile void *ptr, unsigned l + #endif + case 4: return __cmpxchg_u32((unsigned int *)ptr, + (unsigned int)old, (unsigned int)new_); +- case 1: return __cmpxchg_u8((u8 *)ptr, (u8)old, (u8)new_); ++ case 1: return __cmpxchg_u8((u8 *)ptr, old & 0xff, new_ & 0xff); + } + __cmpxchg_called_with_bad_pointer(); + return old; diff --git a/queue-5.4/parisc-parisc-agp-requires-sba-iommu-driver.patch b/queue-5.4/parisc-parisc-agp-requires-sba-iommu-driver.patch new file mode 100644 index 00000000000..1694a772a41 --- /dev/null +++ b/queue-5.4/parisc-parisc-agp-requires-sba-iommu-driver.patch @@ -0,0 +1,31 @@ +From 9054284e8846b0105aad43a4e7174ca29fffbc44 Mon Sep 17 00:00:00 2001 +From: Helge Deller +Date: Tue, 6 Apr 2021 11:32:52 +0200 +Subject: parisc: parisc-agp requires SBA IOMMU driver + +From: Helge Deller + +commit 9054284e8846b0105aad43a4e7174ca29fffbc44 upstream. + +Add a dependency to the SBA IOMMU driver to avoid: +ERROR: modpost: "sba_list" [drivers/char/agp/parisc-agp.ko] undefined! + +Reported-by: kernel test robot +Cc: stable@vger.kernel.org +Signed-off-by: Helge Deller +Signed-off-by: Greg Kroah-Hartman +--- + drivers/char/agp/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/char/agp/Kconfig ++++ b/drivers/char/agp/Kconfig +@@ -125,7 +125,7 @@ config AGP_HP_ZX1 + + config AGP_PARISC + tristate "HP Quicksilver AGP support" +- depends on AGP && PARISC && 64BIT ++ depends on AGP && PARISC && 64BIT && IOMMU_SBA + help + This option gives you AGP GART support for the HP Quicksilver + AGP bus adapter on HP PA-RISC machines (Ok, just on the C8000 diff --git a/queue-5.4/series b/queue-5.4/series index 395a0857028..3afd8a4b429 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -7,3 +7,16 @@ nfc-fix-refcount-leak-in-llcp_sock_connect.patch nfc-fix-memory-leak-in-llcp_sock_connect.patch nfc-avoid-endless-loops-caused-by-repeated-llcp_sock_connect.patch xen-evtchn-change-irq_info-lock-to-raw_spinlock_t.patch +net-ipv6-check-for-validity-before-dereferencing-cfg-fc_nlinfo.nlh.patch +net-dsa-lantiq_gswip-let-gswip-automatically-set-the-xmii-clock.patch +net-dsa-lantiq_gswip-don-t-use-phy-auto-polling.patch +net-dsa-lantiq_gswip-configure-all-remaining-gswip_mii_cfg-bits.patch +drm-i915-fix-invalid-access-to-acpi-_dsm-objects.patch +gcov-re-fix-clang-11-support.patch +ia64-fix-user_stack_pointer-for-ptrace.patch +nds32-flush_dcache_page-use-page_mapping_file-to-avoid-races-with-swapoff.patch +ocfs2-fix-deadlock-between-setattr-and-dio_end_io_write.patch +fs-direct-io-fix-missing-sdio-boundary.patch +parisc-parisc-agp-requires-sba-iommu-driver.patch +parisc-avoid-a-warning-on-u8-cast-for-cmpxchg-on-u8-pointers.patch +arm-dts-turris-omnia-configure-led-intn-pin-as-interrupt-pin.patch