From: Devarsh Thakkar Date: Tue, 24 Feb 2026 13:45:57 +0000 (+0530) Subject: arm: mach-k3: common: Clamp RAM end address to board-usable region in spl_enable_cache() X-Git-Tag: v2026.04-rc4~21 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=26048cdb4ce35b4119e82df2aafb1ebf3f611480;p=thirdparty%2Fu-boot.git arm: mach-k3: common: Clamp RAM end address to board-usable region in spl_enable_cache() commit ba20b2443c29 ("arm: mach-k3: common: Reserve video memory from end of the RAM") switched spl_enable_cache() to use gd->ram_top directly but omitted the board_get_usable_ram_top() call that limits RAM configuration and provides updated RAM end address per memory map used by board and impacts subsequent allocations and reservations. For e.g. here it impacts how high the TLB may be placed. On Verdin AM62 (512 MiB), the raw end of RAM (0xA0000000) is inside OP-TEE's region. board_get_usable_ram_top() in verdin-am62.c returns 0x9C000000 to keep relocations below it, but spl_enable_cache() never called it. commit 42b3ee7fa524 ("arm: mach-k3: am62x: Enable memory firewall support") then enforced the OP-TEE firewall, turning the silent corruption into a hard hang. Fix by calling board_get_usable_ram_top() after computing raw ram_top, consistent with setup_dest_addr() in board_f.c. A weak default is provided for boards that do not need to restrict the RAM top. Fixes: ba20b2443c29 ("arm: mach-k3: common: Reserve video memory from end of the RAM") Reported-by: Francesco Dolcini Link: https://lore.kernel.org/all/20260224102121.GB340942@francesco-nb/ Signed-off-by: Devarsh Thakkar Tested-by: Francesco Dolcini # Verdin AM62 512MB --- diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 0a686efa131..2f3df5519c5 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -407,6 +407,11 @@ void k3_fix_rproc_clock(const char *path) path, a_core_frequency / 1000000, speed_grade); } +__weak phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + return gd->ram_top; +} + void spl_enable_cache(void) { #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) @@ -420,6 +425,7 @@ void spl_enable_cache(void) gd->arch.tlb_size = PGTABLE_SIZE; gd->ram_top += get_effective_memsize(); + gd->ram_top = board_get_usable_ram_top(0); gd->relocaddr = gd->ram_top; ret = spl_reserve_video_from_ram_top();