From: uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Mon, 13 Jun 2016 14:38:51 +0000 (+0000)
Subject: 	* config/i386/i386.md (paritydi2): Use ix86_expand_setcc.
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=27ba6a0bce9dc7e309cf7579cb9473622dc912eb;p=thirdparty%2Fgcc.git

	* config/i386/i386.md (paritydi2): Use ix86_expand_setcc.
	(paritysi2): Ditto.
	(isinfxf2): Ditto.
	(isinf<mode>2): Ditto.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@237382 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2d8b42bb365d..0a2af74432d3 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2016-06-13  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (paritydi2): Use ix86_expand_setcc.
+	(paritysi2): Ditto.
+	(isinfxf2): Ditto.
+	(isinf<mode>2): Ditto.
+
 2016-06-13  Uros Bizjak  <ubizjak@gmail.com>
 
 	* ggc-tests.c (test_finalization): Only test need_finalization_p
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 416cdcd91296..868375256281 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -13458,15 +13458,12 @@
   "! TARGET_POPCNT"
 {
   rtx scratch = gen_reg_rtx (QImode);
-  rtx cond;
 
   emit_insn (gen_paritydi2_cmp (NULL_RTX, NULL_RTX,
 				NULL_RTX, operands[1]));
 
-  cond = gen_rtx_fmt_ee (ORDERED, QImode,
-			 gen_rtx_REG (CCmode, FLAGS_REG),
-			 const0_rtx);
-  emit_insn (gen_rtx_SET (scratch, cond));
+  ix86_expand_setcc (scratch, ORDERED,
+		     gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
 
   if (TARGET_64BIT)
     emit_insn (gen_zero_extendqidi2 (operands[0], scratch));
@@ -13486,14 +13483,11 @@
   "! TARGET_POPCNT"
 {
   rtx scratch = gen_reg_rtx (QImode);
-  rtx cond;
 
   emit_insn (gen_paritysi2_cmp (NULL_RTX, NULL_RTX, operands[1]));
 
-  cond = gen_rtx_fmt_ee (ORDERED, QImode,
-			 gen_rtx_REG (CCmode, FLAGS_REG),
-			 const0_rtx);
-  emit_insn (gen_rtx_SET (scratch, cond));
+  ix86_expand_setcc (scratch, ORDERED,
+		     gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
 
   emit_insn (gen_zero_extendqisi2 (operands[0], scratch));
   DONE;
@@ -16159,8 +16153,6 @@
   rtx mask = GEN_INT (0x45);
   rtx val = GEN_INT (0x05);
 
-  rtx cond;
-
   rtx scratch = gen_reg_rtx (HImode);
   rtx res = gen_reg_rtx (QImode);
 
@@ -16168,10 +16160,8 @@
 
   emit_insn (gen_andqi_ext_0 (scratch, scratch, mask));
   emit_insn (gen_cmpqi_ext_3 (scratch, val));
-  cond = gen_rtx_fmt_ee (EQ, QImode,
-			 gen_rtx_REG (CCmode, FLAGS_REG),
-			 const0_rtx);
-  emit_insn (gen_rtx_SET (res, cond));
+  ix86_expand_setcc (res, EQ,
+		     gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
   emit_insn (gen_zero_extendqisi2 (operands[0], res));
   DONE;
 })
@@ -16186,8 +16176,6 @@
   rtx mask = GEN_INT (0x45);
   rtx val = GEN_INT (0x05);
 
-  rtx cond;
-
   rtx scratch = gen_reg_rtx (HImode);
   rtx res = gen_reg_rtx (QImode);
 
@@ -16204,10 +16192,8 @@
 
   emit_insn (gen_andqi_ext_0 (scratch, scratch, mask));
   emit_insn (gen_cmpqi_ext_3 (scratch, val));
-  cond = gen_rtx_fmt_ee (EQ, QImode,
-			 gen_rtx_REG (CCmode, FLAGS_REG),
-			 const0_rtx);
-  emit_insn (gen_rtx_SET (res, cond));
+  ix86_expand_setcc (res, EQ,
+		     gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
   emit_insn (gen_zero_extendqisi2 (operands[0], res));
   DONE;
 })