From: Aurelien Jarno Date: Thu, 26 Mar 2026 18:35:32 +0000 (+0100) Subject: riscv: dts: spacemit: enable QSPI and add SPI NOR on Milk-V Jupiter X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=2829823956f0f590f5c6b4eafed2dab7a96f69b3;p=thirdparty%2Fkernel%2Fstable.git riscv: dts: spacemit: enable QSPI and add SPI NOR on Milk-V Jupiter Add the QSPI controller node for the Milk-V Jupiter board and describe the attached SPI NOR flash (GD25Q64E). The flash supports a frequency up to 133MHz (80 MHz for reads), and the SoC supports a frequency up to 104 MHz. However tests have shown that the flash is not reliably detected above 26.5 MHz, consistent with frequency used in the vendor kernel. Therefore, use this frequency. The m25p,fast-read properties is taken from the vendor kernel, and the GD25Q64E datasheet confirms tha the fast read opcodes are supported. Add a corresponding flash partition layout, matching the layout and the names used in the vendor U-Boot. Signed-off-by: Aurelien Jarno Reviewed-by: Javier Martinez Canillas Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260326183745.1370642-5-aurelien@aurel32.net Signed-off-by: Yixun Lan --- diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index 836311c3f035..bac6438c6753 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -173,7 +173,7 @@ regulator-always-on; }; - buck4 { + buck4_3v3: buck4 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3300000>; regulator-ramp-delay = <5000>; @@ -256,6 +256,47 @@ }; }; +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <26500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + vcc-supply = <&buck4_3v3>; /* QSPI_VCC1833 */ + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootinfo@0 { + reg = <0x0 0x10000>; + }; + private@10000 { + reg = <0x10000 0x10000>; + }; + fsbl@20000 { + reg = <0x20000 0x40000>; + }; + env@60000 { + reg = <0x60000 0x10000>; + }; + opensbi@70000 { + reg = <0x70000 0x30000>; + }; + uboot@a00000 { + reg = <0xa0000 0x760000>; + }; + }; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>;