From: Greg Kroah-Hartman Date: Fri, 3 Oct 2014 00:06:56 +0000 (-0700) Subject: 3.14-stable patches X-Git-Tag: v3.16.4~51 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=291427196de57d9e93a74907c08d8d466622b535;p=thirdparty%2Fkernel%2Fstable-queue.git 3.14-stable patches added patches: arm-8128-1-abort-don-t-clear-the-exclusive-monitors.patch arm-8133-1-use-irq_set_affinity-with-force-false-when-migrating-irqs.patch arm-8148-1-flush-tls-and-thumbee-register-state-during-exec.patch arm-8165-1-alignment-don-t-break-misaligned-neon-load-store.patch arm-8178-1-fix-set_tls-for-config_kuser_helpers.patch arm-dra7-hwmod-add-dra74x-and-dra72x-specific-ocp-interface-lists.patch arm-dts-dra7-evm-fix-spi1-mux-documentation.patch arm-dts-dra7-fix-interrupt-cells-for-gpio.patch spi-dw-pci-fix-bug-when-regs-left-uninitialized.patch spi-omap-mcspi-fix-the-spi-task-hangs-waiting-dma_rx.patch --- diff --git a/queue-3.14/arm-8128-1-abort-don-t-clear-the-exclusive-monitors.patch b/queue-3.14/arm-8128-1-abort-don-t-clear-the-exclusive-monitors.patch new file mode 100644 index 00000000000..903236d1337 --- /dev/null +++ b/queue-3.14/arm-8128-1-abort-don-t-clear-the-exclusive-monitors.patch @@ -0,0 +1,72 @@ +From 85868313177700d20644263a782351262d2aff84 Mon Sep 17 00:00:00 2001 +From: Mark Rutland +Date: Fri, 15 Aug 2014 12:11:49 +0100 +Subject: ARM: 8128/1: abort: don't clear the exclusive monitors + +From: Mark Rutland + +commit 85868313177700d20644263a782351262d2aff84 upstream. + +The ARMv6 and ARMv7 early abort handlers clear the exclusive monitors +upon entry to the kernel, but this is redundant: + + - We clear the monitors on every exception return since commit + 200b812d0084 ("Clear the exclusive monitor when returning from an + exception"), so this is not necessary to ensure the monitors are + cleared before returning from a fault handler. + + - Any dummy STREX will target a temporary scratch area in memory, and + may succeed or fail without corrupting useful data. Its status value + will not be used. + + - Any other STREX in the kernel must be preceded by an LDREX, which + will initialise the monitors consistently and will not depend on the + earlier state of the monitors. + +Therefore we have no reason to care about the initial state of the +exclusive monitors when a data abort is taken, and clearing the monitors +prior to exception return (as we already do) is sufficient. + +This patch removes the redundant clearing of the exclusive monitors from +the early abort handlers. + +Signed-off-by: Mark Rutland +Acked-by: Will Deacon +Signed-off-by: Russell King +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mm/abort-ev6.S | 6 ------ + arch/arm/mm/abort-ev7.S | 6 ------ + 2 files changed, 12 deletions(-) + +--- a/arch/arm/mm/abort-ev6.S ++++ b/arch/arm/mm/abort-ev6.S +@@ -17,12 +17,6 @@ + */ + .align 5 + ENTRY(v6_early_abort) +-#ifdef CONFIG_CPU_V6 +- sub r1, sp, #4 @ Get unused stack location +- strex r0, r1, [r1] @ Clear the exclusive monitor +-#elif defined(CONFIG_CPU_32v6K) +- clrex +-#endif + mrc p15, 0, r1, c5, c0, 0 @ get FSR + mrc p15, 0, r0, c6, c0, 0 @ get FAR + /* +--- a/arch/arm/mm/abort-ev7.S ++++ b/arch/arm/mm/abort-ev7.S +@@ -13,12 +13,6 @@ + */ + .align 5 + ENTRY(v7_early_abort) +- /* +- * The effect of data aborts on on the exclusive access monitor are +- * UNPREDICTABLE. Do a CLREX to clear the state +- */ +- clrex +- + mrc p15, 0, r1, c5, c0, 0 @ get FSR + mrc p15, 0, r0, c6, c0, 0 @ get FAR + diff --git a/queue-3.14/arm-8133-1-use-irq_set_affinity-with-force-false-when-migrating-irqs.patch b/queue-3.14/arm-8133-1-use-irq_set_affinity-with-force-false-when-migrating-irqs.patch new file mode 100644 index 00000000000..895afa8b694 --- /dev/null +++ b/queue-3.14/arm-8133-1-use-irq_set_affinity-with-force-false-when-migrating-irqs.patch @@ -0,0 +1,57 @@ +From a040803a9d6b8c1876d3487a5cb69602ebcbb82c Mon Sep 17 00:00:00 2001 +From: Sudeep Holla +Date: Mon, 1 Sep 2014 17:14:29 +0100 +Subject: ARM: 8133/1: use irq_set_affinity with force=false when migrating irqs + +From: Sudeep Holla + +commit a040803a9d6b8c1876d3487a5cb69602ebcbb82c upstream. + +Since commit 1dbfa187dad ("ARM: irq migration: force migration off CPU +going down") the ARM interrupt migration code on cpu offline calls +irqchip.irq_set_affinity() with the argument force=true. At the point +of this change the argument had no effect because it was not used by +any interrupt chip driver and there was no semantics defined. + +This changed with commit 01f8fa4f01d8 ("genirq: Allow forcing cpu +affinity of interrupts") which made the force argument useful to route +interrupts to not yet online cpus without checking the target cpu +against the cpu online mask. The following commit ffde1de64012 +("irqchip: gic: Support forced affinity setting") implemented this for +the GIC interrupt controller. + +As a consequence the ARM cpu offline irq migration fails if CPU0 is +offlined, because CPU0 is still set in the affinity mask and the +validataion against cpu online mask is skipped to the force argument +being true. The following first_cpu(mask) selection always selects +CPU0 as the target. + +Solve the issue by calling irq_set_affinity() with force=false from +the CPU offline irq migration code so the GIC driver validates the +affinity mask against CPU online mask and therefore removes CPU0 from +the possible target candidates. + +Tested on TC2 hotpluging CPU0 in and out. Without this patch the system +locks up as the IRQs are not migrated away from CPU0. + +Signed-off-by: Sudeep Holla +Acked-by: Thomas Gleixner +Acked-by: Mark Rutland +Signed-off-by: Russell King +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/kernel/irq.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/kernel/irq.c ++++ b/arch/arm/kernel/irq.c +@@ -163,7 +163,7 @@ static bool migrate_one_irq(struct irq_d + c = irq_data_get_irq_chip(d); + if (!c->irq_set_affinity) + pr_debug("IRQ%u: unable to set affinity\n", d->irq); +- else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret) ++ else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret) + cpumask_copy(d->affinity, affinity); + + return ret; diff --git a/queue-3.14/arm-8148-1-flush-tls-and-thumbee-register-state-during-exec.patch b/queue-3.14/arm-8148-1-flush-tls-and-thumbee-register-state-during-exec.patch new file mode 100644 index 00000000000..d4e4aaa59b8 --- /dev/null +++ b/queue-3.14/arm-8148-1-flush-tls-and-thumbee-register-state-during-exec.patch @@ -0,0 +1,171 @@ +From fbfb872f5f417cea48760c535e0ff027c88b507a Mon Sep 17 00:00:00 2001 +From: Nathan Lynch +Date: Thu, 11 Sep 2014 02:49:08 +0100 +Subject: ARM: 8148/1: flush TLS and thumbee register state during exec + +From: Nathan Lynch + +commit fbfb872f5f417cea48760c535e0ff027c88b507a upstream. + +The TPIDRURO and TPIDRURW registers need to be flushed during exec; +otherwise TLS information is potentially leaked. TPIDRURO in +particular needs careful treatment. Since flush_thread basically +needs the same code used to set the TLS in arm_syscall, pull that into +a common set_tls helper in tls.h and use it in both places. + +Similarly, TEEHBR needs to be cleared during exec as well. Clearing +its save slot in thread_info isn't right as there is no guarantee +that a thread switch will occur before the new program runs. Just +setting the register directly is sufficient. + +Signed-off-by: Nathan Lynch +Acked-by: Will Deacon +Signed-off-by: Russell King +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/include/asm/tls.h | 62 +++++++++++++++++++++++++++++++++++++++++++++ + arch/arm/kernel/process.c | 2 + + arch/arm/kernel/thumbee.c | 2 - + arch/arm/kernel/traps.c | 17 ------------ + 4 files changed, 66 insertions(+), 17 deletions(-) + +--- a/arch/arm/include/asm/tls.h ++++ b/arch/arm/include/asm/tls.h +@@ -1,6 +1,9 @@ + #ifndef __ASMARM_TLS_H + #define __ASMARM_TLS_H + ++#include ++#include ++ + #ifdef __ASSEMBLY__ + #include + .macro switch_tls_none, base, tp, tpuser, tmp1, tmp2 +@@ -50,6 +53,47 @@ + #endif + + #ifndef __ASSEMBLY__ ++ ++static inline void set_tls(unsigned long val) ++{ ++ struct thread_info *thread; ++ ++ thread = current_thread_info(); ++ ++ thread->tp_value[0] = val; ++ ++ /* ++ * This code runs with preemption enabled and therefore must ++ * be reentrant with respect to switch_tls. ++ * ++ * We need to ensure ordering between the shadow state and the ++ * hardware state, so that we don't corrupt the hardware state ++ * with a stale shadow state during context switch. ++ * ++ * If we're preempted here, switch_tls will load TPIDRURO from ++ * thread_info upon resuming execution and the following mcr ++ * is merely redundant. ++ */ ++ barrier(); ++ ++ if (!tls_emu) { ++ if (has_tls_reg) { ++ asm("mcr p15, 0, %0, c13, c0, 3" ++ : : "r" (val)); ++ } else { ++ /* ++ * User space must never try to access this ++ * directly. Expect your app to break ++ * eventually if you do so. The user helper ++ * at 0xffff0fe0 must be used instead. (see ++ * entry-armv.S for details) ++ */ ++ *((unsigned int *)0xffff0ff0) = val; ++ } ++ ++ } ++} ++ + static inline unsigned long get_tpuser(void) + { + unsigned long reg = 0; +@@ -59,5 +103,23 @@ static inline unsigned long get_tpuser(v + + return reg; + } ++ ++static inline void set_tpuser(unsigned long val) ++{ ++ /* Since TPIDRURW is fully context-switched (unlike TPIDRURO), ++ * we need not update thread_info. ++ */ ++ if (has_tls_reg && !tls_emu) { ++ asm("mcr p15, 0, %0, c13, c0, 2" ++ : : "r" (val)); ++ } ++} ++ ++static inline void flush_tls(void) ++{ ++ set_tls(0); ++ set_tpuser(0); ++} ++ + #endif + #endif /* __ASMARM_TLS_H */ +--- a/arch/arm/kernel/process.c ++++ b/arch/arm/kernel/process.c +@@ -334,6 +334,8 @@ void flush_thread(void) + memset(&tsk->thread.debug, 0, sizeof(struct debug_info)); + memset(&thread->fpstate, 0, sizeof(union fp_state)); + ++ flush_tls(); ++ + thread_notify(THREAD_NOTIFY_FLUSH, thread); + } + +--- a/arch/arm/kernel/thumbee.c ++++ b/arch/arm/kernel/thumbee.c +@@ -45,7 +45,7 @@ static int thumbee_notifier(struct notif + + switch (cmd) { + case THREAD_NOTIFY_FLUSH: +- thread->thumbee_state = 0; ++ teehbr_write(0); + break; + case THREAD_NOTIFY_SWITCH: + current_thread_info()->thumbee_state = teehbr_read(); +--- a/arch/arm/kernel/traps.c ++++ b/arch/arm/kernel/traps.c +@@ -578,7 +578,6 @@ do_cache_op(unsigned long start, unsigne + #define NR(x) ((__ARM_NR_##x) - __ARM_NR_BASE) + asmlinkage int arm_syscall(int no, struct pt_regs *regs) + { +- struct thread_info *thread = current_thread_info(); + siginfo_t info; + + if ((no >> 16) != (__ARM_NR_BASE>> 16)) +@@ -629,21 +628,7 @@ asmlinkage int arm_syscall(int no, struc + return regs->ARM_r0; + + case NR(set_tls): +- thread->tp_value[0] = regs->ARM_r0; +- if (tls_emu) +- return 0; +- if (has_tls_reg) { +- asm ("mcr p15, 0, %0, c13, c0, 3" +- : : "r" (regs->ARM_r0)); +- } else { +- /* +- * User space must never try to access this directly. +- * Expect your app to break eventually if you do so. +- * The user helper at 0xffff0fe0 must be used instead. +- * (see entry-armv.S for details) +- */ +- *((unsigned int *)0xffff0ff0) = regs->ARM_r0; +- } ++ set_tls(regs->ARM_r0); + return 0; + + #ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG diff --git a/queue-3.14/arm-8165-1-alignment-don-t-break-misaligned-neon-load-store.patch b/queue-3.14/arm-8165-1-alignment-don-t-break-misaligned-neon-load-store.patch new file mode 100644 index 00000000000..8a47965668a --- /dev/null +++ b/queue-3.14/arm-8165-1-alignment-don-t-break-misaligned-neon-load-store.patch @@ -0,0 +1,42 @@ +From 5ca918e5e3f9df4634077c06585c42bc6a8d699a Mon Sep 17 00:00:00 2001 +From: Robin Murphy +Date: Thu, 25 Sep 2014 11:56:19 +0100 +Subject: ARM: 8165/1: alignment: don't break misaligned NEON load/store + +From: Robin Murphy + +commit 5ca918e5e3f9df4634077c06585c42bc6a8d699a upstream. + +The alignment fixup incorrectly decodes faulting ARM VLDn/VSTn +instructions (where the optional alignment hint is given but incorrect) +as LDR/STR, leading to register corruption. Detect these and correctly +treat them as unhandled, so that userspace gets the fault it expects. + +Reported-by: Simon Hosie +Signed-off-by: Robin Murphy +Signed-off-by: Russell King +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mm/alignment.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/arch/arm/mm/alignment.c ++++ b/arch/arm/mm/alignment.c +@@ -40,6 +40,7 @@ + * This code is not portable to processors with late data abort handling. + */ + #define CODING_BITS(i) (i & 0x0e000000) ++#define COND_BITS(i) (i & 0xf0000000) + + #define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */ + #define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */ +@@ -817,6 +818,8 @@ do_alignment(unsigned long addr, unsigne + break; + + case 0x04000000: /* ldr or str immediate */ ++ if (COND_BITS(instr) == 0xf0000000) /* NEON VLDn, VSTn */ ++ goto bad; + offset.un = OFFSET_BITS(instr); + handler = do_alignment_ldrstr; + break; diff --git a/queue-3.14/arm-8178-1-fix-set_tls-for-config_kuser_helpers.patch b/queue-3.14/arm-8178-1-fix-set_tls-for-config_kuser_helpers.patch new file mode 100644 index 00000000000..21e7bfc2986 --- /dev/null +++ b/queue-3.14/arm-8178-1-fix-set_tls-for-config_kuser_helpers.patch @@ -0,0 +1,65 @@ +From 9cc6d9e5daaa147a9a3e31557efcb331989e77be Mon Sep 17 00:00:00 2001 +From: Nathan Lynch +Date: Mon, 29 Sep 2014 19:11:36 +0100 +Subject: ARM: 8178/1: fix set_tls for !CONFIG_KUSER_HELPERS + +From: Nathan Lynch + +commit 9cc6d9e5daaa147a9a3e31557efcb331989e77be upstream. + +Joachim Eastwood reports that commit fbfb872f5f41 "ARM: 8148/1: flush +TLS and thumbee register state during exec" causes a boot-time crash +on a Cortex-M4 nommu system: + +Freeing unused kernel memory: 68K (281e5000 - 281f6000) +Unhandled exception: IPSR = 00000005 LR = fffffff1 +CPU: 0 PID: 1 Comm: swapper Not tainted 3.17.0-rc6-00313-gd2205fa30aa7 #191 +task: 29834000 ti: 29832000 task.ti: 29832000 +PC is at flush_thread+0x2e/0x40 +LR is at flush_thread+0x21/0x40 +pc : [<2800954a>] lr : [<2800953d>] psr: 4100000b +sp : 29833d60 ip : 00000000 fp : 00000001 +r10: 00003cf8 r9 : 29b1f000 r8 : 00000000 +r7 : 29b0bc00 r6 : 29834000 r5 : 29832000 r4 : 29832000 +r3 : ffff0ff0 r2 : 29832000 r1 : 00000000 r0 : 282121f0 +xPSR: 4100000b +CPU: 0 PID: 1 Comm: swapper Not tainted 3.17.0-rc6-00313-gd2205fa30aa7 #191 +[<2800afa5>] (unwind_backtrace) from [<2800a327>] (show_stack+0xb/0xc) +[<2800a327>] (show_stack) from [<2800a963>] (__invalid_entry+0x4b/0x4c) + +The problem is that set_tls is attempting to clear the TLS location in +the kernel-user helper page, which isn't set up on V7M. + +Fix this by guarding the write to the kuser helper page with +a CONFIG_KUSER_HELPERS ifdef. + +Fixes: fbfb872f5f41 ARM: 8148/1: flush TLS and thumbee register state during exec + +Reported-by: Joachim Eastwood +Tested-by: Joachim Eastwood +Signed-off-by: Nathan Lynch +Signed-off-by: Russell King +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/include/asm/tls.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm/include/asm/tls.h ++++ b/arch/arm/include/asm/tls.h +@@ -81,6 +81,7 @@ static inline void set_tls(unsigned long + asm("mcr p15, 0, %0, c13, c0, 3" + : : "r" (val)); + } else { ++#ifdef CONFIG_KUSER_HELPERS + /* + * User space must never try to access this + * directly. Expect your app to break +@@ -89,6 +90,7 @@ static inline void set_tls(unsigned long + * entry-armv.S for details) + */ + *((unsigned int *)0xffff0ff0) = val; ++#endif + } + + } diff --git a/queue-3.14/arm-dra7-hwmod-add-dra74x-and-dra72x-specific-ocp-interface-lists.patch b/queue-3.14/arm-dra7-hwmod-add-dra74x-and-dra72x-specific-ocp-interface-lists.patch new file mode 100644 index 00000000000..be8613bb5bf --- /dev/null +++ b/queue-3.14/arm-dra7-hwmod-add-dra74x-and-dra72x-specific-ocp-interface-lists.patch @@ -0,0 +1,89 @@ +From f7f7a29bf0cf25af23f37e5b5bf1368b85705286 Mon Sep 17 00:00:00 2001 +From: Rajendra Nayak +Date: Wed, 27 Aug 2014 19:38:23 -0600 +Subject: ARM: DRA7: hwmod: Add dra74x and dra72x specific ocp interface lists + +From: Rajendra Nayak + +commit f7f7a29bf0cf25af23f37e5b5bf1368b85705286 upstream. + +To deal with IPs which are specific to dra74x and dra72x, maintain seperate +ocp interface lists, while keeping the common list for all common IPs. + +Move USB OTG SS4 to dra74x only list since its unavailable in +dra72x and is giving an abort during boot. The dra72x only list +is empty for now and a placeholder for future hwmod additions which +are specific to dra72x. + +Fixes: d904b38df0db13 ("ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss") +Reported-by: Keerthy +Signed-off-by: Rajendra Nayak +Signed-off-by: Lokesh Vutla +Tested-by: Nishanth Menon +[paul@pwsan.com: fixed comment style to conform with CodingStyle] +Signed-off-by: Paul Walmsley +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-omap2/omap_hwmod.c | 3 +++ + arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 22 ++++++++++++++++++++-- + 2 files changed, 23 insertions(+), 2 deletions(-) + +--- a/arch/arm/mach-omap2/omap_hwmod.c ++++ b/arch/arm/mach-omap2/omap_hwmod.c +@@ -3349,6 +3349,9 @@ int __init omap_hwmod_register_links(str + if (!ois) + return 0; + ++ if (ois[0] == NULL) /* Empty list */ ++ return 0; ++ + if (!linkspace) { + if (_alloc_linkspace(ois)) { + pr_err("omap_hwmod: could not allocate link space\n"); +--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c ++++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +@@ -35,6 +35,7 @@ + #include "i2c.h" + #include "mmc.h" + #include "wd_timer.h" ++#include "soc.h" + + /* Base offset for all DRA7XX interrupts external to MPUSS */ + #define DRA7XX_IRQ_GIC_START 32 +@@ -2707,7 +2708,6 @@ static struct omap_hwmod_ocp_if *dra7xx_ + &dra7xx_l4_per3__usb_otg_ss1, + &dra7xx_l4_per3__usb_otg_ss2, + &dra7xx_l4_per3__usb_otg_ss3, +- &dra7xx_l4_per3__usb_otg_ss4, + &dra7xx_l3_main_1__vcp1, + &dra7xx_l4_per2__vcp1, + &dra7xx_l3_main_1__vcp2, +@@ -2716,8 +2716,26 @@ static struct omap_hwmod_ocp_if *dra7xx_ + NULL, + }; + ++static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = { ++ &dra7xx_l4_per3__usb_otg_ss4, ++ NULL, ++}; ++ ++static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = { ++ NULL, ++}; ++ + int __init dra7xx_hwmod_init(void) + { ++ int ret; ++ + omap_hwmod_init(); +- return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); ++ ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); ++ ++ if (!ret && soc_is_dra74x()) ++ return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); ++ else if (!ret && soc_is_dra72x()) ++ return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); ++ ++ return ret; + } diff --git a/queue-3.14/arm-dts-dra7-evm-fix-spi1-mux-documentation.patch b/queue-3.14/arm-dts-dra7-evm-fix-spi1-mux-documentation.patch new file mode 100644 index 00000000000..32bd16d0cf2 --- /dev/null +++ b/queue-3.14/arm-dts-dra7-evm-fix-spi1-mux-documentation.patch @@ -0,0 +1,53 @@ +From 68e4d9e58dbae2fb178e8b74806f521adb16f0d3 Mon Sep 17 00:00:00 2001 +From: Nishanth Menon +Date: Thu, 4 Sep 2014 08:33:37 -0500 +Subject: ARM: dts: dra7-evm: Fix spi1 mux documentation + +From: Nishanth Menon + +commit 68e4d9e58dbae2fb178e8b74806f521adb16f0d3 upstream. + +While auditing the various pin ctrl configurations using the following +command: +grep PIN_ arch/arm/boot/dts/dra7-evm.dts|(while read line; +do + v=`echo "$line" | sed -e "s/\s\s*/|/g" | cut -d '|' -f1 | + cut -d 'x' -f2|tr [a-z] [A-Z]`; + HEX=`echo "obase=16;ibase=16;4A003400+$v"| bc`; + echo "$HEX ===> $line"; +done) +against DRA75x/74x NDA TRM revision S(SPRUHI2S August 2014), +documentation errors were found for spi1 pinctrl. Fix the same. + +Fixes: 6e58b8f1daaf1af ("ARM: dts: DRA7: Add the dts files for dra7 SoC and dra7-evm board") +Signed-off-by: Nishanth Menon +Signed-off-by: Tony Lindgren +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/dra7-evm.dts | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +--- a/arch/arm/boot/dts/dra7-evm.dts ++++ b/arch/arm/boot/dts/dra7-evm.dts +@@ -50,13 +50,13 @@ + + mcspi1_pins: pinmux_mcspi1_pins { + pinctrl-single,pins = < +- 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi2_clk */ +- 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi2_d1 */ +- 0x3ac (PIN_INPUT | MUX_MODE0) /* spi2_d0 */ +- 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ +- 0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs1 */ +- 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs2 */ +- 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs3 */ ++ 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */ ++ 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */ ++ 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */ ++ 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */ ++ 0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs1 */ ++ 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */ ++ 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */ + >; + }; + diff --git a/queue-3.14/arm-dts-dra7-fix-interrupt-cells-for-gpio.patch b/queue-3.14/arm-dts-dra7-fix-interrupt-cells-for-gpio.patch new file mode 100644 index 00000000000..fc0a40d8741 --- /dev/null +++ b/queue-3.14/arm-dts-dra7-fix-interrupt-cells-for-gpio.patch @@ -0,0 +1,103 @@ +From e49d519c456f4fb6f4a0473bc04ba30bb805fce5 Mon Sep 17 00:00:00 2001 +From: Nishanth Menon +Date: Mon, 25 Aug 2014 16:15:34 -0700 +Subject: ARM: dts: DRA7: fix interrupt-cells for GPIO + +From: Nishanth Menon + +commit e49d519c456f4fb6f4a0473bc04ba30bb805fce5 upstream. + +GPIO modules are also interrupt sources. However, they require both the +GPIO number and IRQ type to function properly. + +By declaring that GPIO uses interrupt-cells=<1>, we essentially do not +allow users of the nodes to use the interrupt property appropritely. + +With this change, the following now works: + +interrupt-parent = <&gpio6>; +interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + +Fixes: 6e58b8f1daaf ('ARM: dts: DRA7: Add the dts files for dra7 SoC and dra7-evm board') +Signed-off-by: Nishanth Menon +Signed-off-by: Tony Lindgren +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/dra7.dtsi | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +--- a/arch/arm/boot/dts/dra7.dtsi ++++ b/arch/arm/boot/dts/dra7.dtsi +@@ -178,7 +178,7 @@ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; +- #interrupt-cells = <1>; ++ #interrupt-cells = <2>; + }; + + gpio2: gpio@48055000 { +@@ -189,7 +189,7 @@ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; +- #interrupt-cells = <1>; ++ #interrupt-cells = <2>; + }; + + gpio3: gpio@48057000 { +@@ -200,7 +200,7 @@ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; +- #interrupt-cells = <1>; ++ #interrupt-cells = <2>; + }; + + gpio4: gpio@48059000 { +@@ -211,7 +211,7 @@ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; +- #interrupt-cells = <1>; ++ #interrupt-cells = <2>; + }; + + gpio5: gpio@4805b000 { +@@ -222,7 +222,7 @@ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; +- #interrupt-cells = <1>; ++ #interrupt-cells = <2>; + }; + + gpio6: gpio@4805d000 { +@@ -233,7 +233,7 @@ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; +- #interrupt-cells = <1>; ++ #interrupt-cells = <2>; + }; + + gpio7: gpio@48051000 { +@@ -244,7 +244,7 @@ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; +- #interrupt-cells = <1>; ++ #interrupt-cells = <2>; + }; + + gpio8: gpio@48053000 { +@@ -255,7 +255,7 @@ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; +- #interrupt-cells = <1>; ++ #interrupt-cells = <2>; + }; + + uart1: serial@4806a000 { diff --git a/queue-3.14/series b/queue-3.14/series index ddc236cb6ba..8b20ef62c21 100644 --- a/queue-3.14/series +++ b/queue-3.14/series @@ -105,3 +105,13 @@ iommu-fsl-fix-warning-resulting-from-adding-pci-device-twice.patch iommu-arm-smmu-fix-programming-of-smmu_cbn_tcr-for-stage-1.patch nfsv4-nfs4_state_manager-vs.-nfs_server_remove_lists.patch nfsv4-fix-another-bug-in-the-close-open_downgrade-code.patch +spi-omap-mcspi-fix-the-spi-task-hangs-waiting-dma_rx.patch +spi-dw-pci-fix-bug-when-regs-left-uninitialized.patch +arm-8128-1-abort-don-t-clear-the-exclusive-monitors.patch +arm-dra7-hwmod-add-dra74x-and-dra72x-specific-ocp-interface-lists.patch +arm-dts-dra7-fix-interrupt-cells-for-gpio.patch +arm-dts-dra7-evm-fix-spi1-mux-documentation.patch +arm-8133-1-use-irq_set_affinity-with-force-false-when-migrating-irqs.patch +arm-8148-1-flush-tls-and-thumbee-register-state-during-exec.patch +arm-8165-1-alignment-don-t-break-misaligned-neon-load-store.patch +arm-8178-1-fix-set_tls-for-config_kuser_helpers.patch diff --git a/queue-3.14/spi-dw-pci-fix-bug-when-regs-left-uninitialized.patch b/queue-3.14/spi-dw-pci-fix-bug-when-regs-left-uninitialized.patch new file mode 100644 index 00000000000..5f4c0bf731f --- /dev/null +++ b/queue-3.14/spi-dw-pci-fix-bug-when-regs-left-uninitialized.patch @@ -0,0 +1,34 @@ +From c9d5d6fe168fd45a4dfdd0116affe708789b4702 Mon Sep 17 00:00:00 2001 +From: Andy Shevchenko +Date: Wed, 27 Aug 2014 16:21:12 +0300 +Subject: spi: dw-pci: fix bug when regs left uninitialized + +From: Andy Shevchenko + +commit c9d5d6fe168fd45a4dfdd0116affe708789b4702 upstream. + +The commit 04f421e7 "spi: dw: use managed resources" changes drivers to use +managed functions, but seems wasn't properly tested in PCI case. The regs field +of struct dw_spi left uninitialized. Thus, kernel crashes when tries to access +to the SPI controller registers. This patch fixes the issue. + +Fixes: 04f421e7 (spi: dw: use managed resources) +Signed-off-by: Andy Shevchenko +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/spi/spi-dw-pci.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/spi/spi-dw-pci.c ++++ b/drivers/spi/spi-dw-pci.c +@@ -62,6 +62,8 @@ static int spi_pci_probe(struct pci_dev + if (ret) + return ret; + ++ dws->regs = pcim_iomap_table(pdev)[pci_bar]; ++ + dws->bus_num = 0; + dws->num_cs = 4; + dws->irq = pdev->irq; diff --git a/queue-3.14/spi-omap-mcspi-fix-the-spi-task-hangs-waiting-dma_rx.patch b/queue-3.14/spi-omap-mcspi-fix-the-spi-task-hangs-waiting-dma_rx.patch new file mode 100644 index 00000000000..93687fd7792 --- /dev/null +++ b/queue-3.14/spi-omap-mcspi-fix-the-spi-task-hangs-waiting-dma_rx.patch @@ -0,0 +1,31 @@ +From 3d0763c006f8da1b44a9f5f9a21187f5b8f674f4 Mon Sep 17 00:00:00 2001 +From: "Jorge A. Ventura" +Date: Sat, 9 Aug 2014 16:06:58 -0500 +Subject: spi/omap-mcspi: Fix the spi task hangs waiting dma_rx + +From: "Jorge A. Ventura" + +commit 3d0763c006f8da1b44a9f5f9a21187f5b8f674f4 upstream. + +The spi hangs waiting the completion of omap2_mcspi_rx_callback. + +Signed-off-by: Jorge A. Ventura +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/spi/spi-omap2-mcspi.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/spi/spi-omap2-mcspi.c ++++ b/drivers/spi/spi-omap2-mcspi.c +@@ -321,7 +321,8 @@ static void omap2_mcspi_set_fifo(const s + disable_fifo: + if (t->rx_buf != NULL) + chconf &= ~OMAP2_MCSPI_CHCONF_FFER; +- else ++ ++ if (t->tx_buf != NULL) + chconf &= ~OMAP2_MCSPI_CHCONF_FFET; + + mcspi_write_chconf0(spi, chconf);