From: Greg Kroah-Hartman Date: Sun, 8 Sep 2024 11:54:43 +0000 (+0200) Subject: 5.15-stable patches X-Git-Tag: v4.19.322~98 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=2c50c5819da2a3d6cee2ede5fdac602ecb2ad44c;p=thirdparty%2Fkernel%2Fstable-queue.git 5.15-stable patches added patches: can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch clk-qcom-clk-alpha-pll-fix-zonda-set_rate-failure-when-pll-is-disabled.patch clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch --- diff --git a/queue-5.15/can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch b/queue-5.15/can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch new file mode 100644 index 00000000000..8154f96e2ef --- /dev/null +++ b/queue-5.15/can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch @@ -0,0 +1,52 @@ +From 7dd9c26bd6cf679bcfdef01a8659791aa6487a29 Mon Sep 17 00:00:00 2001 +From: Simon Arlott +Date: Thu, 22 Aug 2024 08:25:07 +0100 +Subject: can: mcp251x: fix deadlock if an interrupt occurs during mcp251x_open + +From: Simon Arlott + +commit 7dd9c26bd6cf679bcfdef01a8659791aa6487a29 upstream. + +The mcp251x_hw_wake() function is called with the mpc_lock mutex held and +disables the interrupt handler so that no interrupts can be processed while +waking the device. If an interrupt has already occurred then waiting for +the interrupt handler to complete will deadlock because it will be trying +to acquire the same mutex. + +CPU0 CPU1 +---- ---- +mcp251x_open() + mutex_lock(&priv->mcp_lock) + request_threaded_irq() + + mcp251x_can_ist() + mutex_lock(&priv->mcp_lock) + mcp251x_hw_wake() + disable_irq() <-- deadlock + +Use disable_irq_nosync() instead because the interrupt handler does +everything while holding the mutex so it doesn't matter if it's still +running. + +Fixes: 8ce8c0abcba3 ("can: mcp251x: only reset hardware as required") +Signed-off-by: Simon Arlott +Reviewed-by: Przemek Kitszel +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/all/4fc08687-1d80-43fe-9f0d-8ef8475e75f6@0882a8b5-c6c3-11e9-b005-00805fc181fe.uuid.home.arpa +Signed-off-by: Marc Kleine-Budde +Signed-off-by: Greg Kroah-Hartman +--- + drivers/net/can/spi/mcp251x.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/can/spi/mcp251x.c ++++ b/drivers/net/can/spi/mcp251x.c +@@ -755,7 +755,7 @@ static int mcp251x_hw_wake(struct spi_de + int ret; + + /* Force wakeup interrupt to wake device, but don't execute IST */ +- disable_irq(spi->irq); ++ disable_irq_nosync(spi->irq); + mcp251x_write_2regs(spi, CANINTE, CANINTE_WAKIE, CANINTF_WAKIF); + + /* Wait for oscillator startup timer after wake up */ diff --git a/queue-5.15/clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch b/queue-5.15/clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch new file mode 100644 index 00000000000..6232cf85cc9 --- /dev/null +++ b/queue-5.15/clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch @@ -0,0 +1,33 @@ +From 2c4553e6c485a96b5d86989eb9654bf20e51e6dd Mon Sep 17 00:00:00 2001 +From: Satya Priya Kakitapalli +Date: Wed, 31 Jul 2024 11:59:09 +0530 +Subject: clk: qcom: clk-alpha-pll: Fix the pll post div mask + +From: Satya Priya Kakitapalli + +commit 2c4553e6c485a96b5d86989eb9654bf20e51e6dd upstream. + +The PLL_POST_DIV_MASK should be 0 to (width - 1) bits. Fix it. + +Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider") +Cc: stable@vger.kernel.org +Reviewed-by: Konrad Dybcio +Signed-off-by: Satya Priya Kakitapalli +Link: https://lore.kernel.org/r/20240731062916.2680823-2-quic_skakitap@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/clk-alpha-pll.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/qcom/clk-alpha-pll.c ++++ b/drivers/clk/qcom/clk-alpha-pll.c +@@ -38,7 +38,7 @@ + + #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) + # define PLL_POST_DIV_SHIFT 8 +-# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0) ++# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) + # define PLL_ALPHA_EN BIT(24) + # define PLL_ALPHA_MODE BIT(25) + # define PLL_VCO_SHIFT 20 diff --git a/queue-5.15/clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch b/queue-5.15/clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch new file mode 100644 index 00000000000..bb34cb7a6bd --- /dev/null +++ b/queue-5.15/clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch @@ -0,0 +1,37 @@ +From 4ad1ed6ef27cab94888bb3c740c14042d5c0dff2 Mon Sep 17 00:00:00 2001 +From: Satya Priya Kakitapalli +Date: Wed, 31 Jul 2024 11:59:10 +0530 +Subject: clk: qcom: clk-alpha-pll: Fix the trion pll postdiv set rate API + +From: Satya Priya Kakitapalli + +commit 4ad1ed6ef27cab94888bb3c740c14042d5c0dff2 upstream. + +Correct the pll postdiv shift used in clk_trion_pll_postdiv_set_rate +API. The shift value is not same for different types of plls and +should be taken from the pll's .post_div_shift member. + +Fixes: 548a909597d5 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs") +Cc: stable@vger.kernel.org +Signed-off-by: Satya Priya Kakitapalli +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20240731062916.2680823-3-quic_skakitap@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/clk-alpha-pll.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/clk/qcom/clk-alpha-pll.c ++++ b/drivers/clk/qcom/clk-alpha-pll.c +@@ -1362,8 +1362,8 @@ clk_trion_pll_postdiv_set_rate(struct cl + } + + return regmap_update_bits(regmap, PLL_USER_CTL(pll), +- PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, +- val << PLL_POST_DIV_SHIFT); ++ PLL_POST_DIV_MASK(pll) << pll->post_div_shift, ++ val << pll->post_div_shift); + } + + const struct clk_ops clk_alpha_pll_postdiv_trion_ops = { diff --git a/queue-5.15/clk-qcom-clk-alpha-pll-fix-zonda-set_rate-failure-when-pll-is-disabled.patch b/queue-5.15/clk-qcom-clk-alpha-pll-fix-zonda-set_rate-failure-when-pll-is-disabled.patch new file mode 100644 index 00000000000..958b1c9117d --- /dev/null +++ b/queue-5.15/clk-qcom-clk-alpha-pll-fix-zonda-set_rate-failure-when-pll-is-disabled.patch @@ -0,0 +1,37 @@ +From 85e8ee59dfde1a7b847fbed0778391392cd985cb Mon Sep 17 00:00:00 2001 +From: Satya Priya Kakitapalli +Date: Wed, 31 Jul 2024 11:59:11 +0530 +Subject: clk: qcom: clk-alpha-pll: Fix zonda set_rate failure when PLL is disabled + +From: Satya Priya Kakitapalli + +commit 85e8ee59dfde1a7b847fbed0778391392cd985cb upstream. + +Currently, clk_zonda_pll_set_rate polls for the PLL to lock even if the +PLL is disabled. However, if the PLL is disabled then LOCK_DET will +never assert and we'll return an error. There is no reason to poll +LOCK_DET if the PLL is already disabled, so skip polling in this case. + +Fixes: f21b6bfecc27 ("clk: qcom: clk-alpha-pll: add support for zonda pll") +Cc: stable@vger.kernel.org +Signed-off-by: Satya Priya Kakitapalli +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20240731062916.2680823-4-quic_skakitap@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/clk-alpha-pll.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/clk/qcom/clk-alpha-pll.c ++++ b/drivers/clk/qcom/clk-alpha-pll.c +@@ -1932,6 +1932,9 @@ static int clk_zonda_pll_set_rate(struct + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); + ++ if (!clk_hw_is_enabled(hw)) ++ return 0; ++ + /* Wait before polling for the frequency latch */ + udelay(5); + diff --git a/queue-5.15/clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch b/queue-5.15/clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch new file mode 100644 index 00000000000..93ee013c77f --- /dev/null +++ b/queue-5.15/clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch @@ -0,0 +1,63 @@ +From f4973130d255dd4811006f5822d4fa4d0de9d712 Mon Sep 17 00:00:00 2001 +From: Satya Priya Kakitapalli +Date: Wed, 31 Jul 2024 11:59:12 +0530 +Subject: clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL + +From: Satya Priya Kakitapalli + +commit f4973130d255dd4811006f5822d4fa4d0de9d712 upstream. + +The Zonda PLL has a 16 bit signed alpha and in the cases where the alpha +value is greater than 0.5, the L value needs to be adjusted accordingly. +Thus update the logic to handle the signed alpha val. + +Fixes: f21b6bfecc27 ("clk: qcom: clk-alpha-pll: add support for zonda pll") +Cc: stable@vger.kernel.org +Signed-off-by: Satya Priya Kakitapalli +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20240731062916.2680823-5-quic_skakitap@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/clk-alpha-pll.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +--- a/drivers/clk/qcom/clk-alpha-pll.c ++++ b/drivers/clk/qcom/clk-alpha-pll.c +@@ -39,6 +39,7 @@ + #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) + # define PLL_POST_DIV_SHIFT 8 + # define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) ++# define PLL_ALPHA_MSB BIT(15) + # define PLL_ALPHA_EN BIT(24) + # define PLL_ALPHA_MODE BIT(25) + # define PLL_VCO_SHIFT 20 +@@ -1913,6 +1914,18 @@ static void clk_zonda_pll_disable(struct + regmap_write(regmap, PLL_OPMODE(pll), 0x0); + } + ++static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l) ++{ ++ u64 remainder, quotient; ++ ++ quotient = rate; ++ remainder = do_div(quotient, prate); ++ *l = quotient; ++ ++ if ((remainder * 2) / prate) ++ *l = *l + 1; ++} ++ + static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) + { +@@ -1929,6 +1942,9 @@ static int clk_zonda_pll_set_rate(struct + if (ret < 0) + return ret; + ++ if (a & PLL_ALPHA_MSB) ++ zonda_pll_adjust_l_val(rate, prate, &l); ++ + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); + diff --git a/queue-5.15/series b/queue-5.15/series index afe9157bf2f..93d8022e6ed 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -77,3 +77,8 @@ mmc-sdhci-of-aspeed-fix-module-autoloading.patch mmc-cqhci-fix-checking-of-cqhci_halt-state.patch fuse-update-stats-for-pages-in-dropped-aux-writeback-list.patch fuse-use-unsigned-type-for-getxattr-listxattr-size-truncation.patch +clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch +clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch +clk-qcom-clk-alpha-pll-fix-zonda-set_rate-failure-when-pll-is-disabled.patch +clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch +can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch