From: Hongyu Wang Date: Tue, 28 Jul 2026 03:41:37 +0000 (+0800) Subject: i386: Merge duplicate preferred_for_speed attributes on QImode NDD patterns X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=2e21725efbdb11a87d98090af8bc2d1cb1012e6f;p=thirdparty%2Fgcc.git i386: Merge duplicate preferred_for_speed attributes on QImode NDD patterns Several QImode integer patterns has two separate attr "preferred_for_speed" set, one gating the NDD memory-form alternatives with TARGET_ENABLE_NDD_MEM, and the existing one is for !TARGET_PARTIAL_REG_STALL. The later one will make genattrtab regenerates the cond based on !PARTIAL_REG_STALL only and overrides the TARGET_ENABLE_NDD_MEM, so the NDD memory alternatives were always preferred for speed regardless of the X86_TUNE_ENABLE_NDD_MEM enabled or disabled. Combine both conditions into a single preferred_for_speed cond per pattern. For *ashlqi3_1 alternative 5 belongs to both sets, so it is gated on TARGET_ENABLE_NDD_MEM && !TARGET_PARTIAL_REG_STALL. gcc/ChangeLog: * config/i386/i386.md (*addqi_1): Merge the two preferred_for_speed attributes into one. (*andqi_1): Likewise. (*andqi_2_maybe_si): Likewise. (*qi_1): Likewise. (*notxorqi_1): Likewise. (*one_cmplqi2_1): Likewise. (*ashlqi3_1): Likewise. gcc/testsuite/ChangeLog: * gcc.target/i386/apx-ndd-mem-tune.c: New test. --- diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 230fcb576d0..0bfe52c08fa 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -7139,10 +7139,6 @@ } } [(set_attr "isa" "*,*,*,*,*,*,apx_ndd,apx_ndd,apx_ndd") - (set (attr "preferred_for_speed") - (cond [(eq_attr "alternative" "7,8") - (symbol_ref "TARGET_ENABLE_NDD_MEM")] - (symbol_ref "true"))) (set (attr "type") (cond [(eq_attr "alternative" "5") (const_string "lea") @@ -7160,7 +7156,9 @@ ;; Potential partial reg stall on alternatives 3 and 4. (set (attr "preferred_for_speed") (cond [(eq_attr "alternative" "3,4") - (symbol_ref "!TARGET_PARTIAL_REG_STALL")] + (symbol_ref "!TARGET_PARTIAL_REG_STALL") + (eq_attr "alternative" "7,8") + (symbol_ref "TARGET_ENABLE_NDD_MEM")] (symbol_ref "true")))]) ;; Alternative 1 is needed to work around LRA limitation, see PR82524. @@ -13577,10 +13575,6 @@ #" [(set_attr "type" "alu,alu,alu,alu,alu,alu,msklog") (set_attr "isa" "*,*,*,apx_ndd,apx_ndd,apx_ndd,*") - (set (attr "preferred_for_speed") - (cond [(eq_attr "alternative" "4,5") - (symbol_ref "TARGET_ENABLE_NDD_MEM")] - (symbol_ref "true"))) (set_attr "has_nf" "1") (set (attr "mode") (cond [(eq_attr "alternative" "2") @@ -13593,7 +13587,9 @@ ;; Potential partial reg stall on alternative 2. (set (attr "preferred_for_speed") (cond [(eq_attr "alternative" "2") - (symbol_ref "!TARGET_PARTIAL_REG_STALL")] + (symbol_ref "!TARGET_PARTIAL_REG_STALL") + (eq_attr "alternative" "4,5") + (symbol_ref "TARGET_ENABLE_NDD_MEM")] (symbol_ref "true")))]) ;; Alternative 1 is needed to work around LRA limitation, see PR82524. @@ -13841,10 +13837,6 @@ } [(set_attr "type" "alu") (set_attr "isa" "*,*,*,apx_ndd,apx_ndd,apx_ndd") - (set (attr "preferred_for_speed") - (cond [(eq_attr "alternative" "4,5") - (symbol_ref "TARGET_ENABLE_NDD_MEM")] - (symbol_ref "true"))) (set (attr "mode") (cond [(eq_attr "alternative" "3,4,5") (const_string "QI") @@ -13859,7 +13851,9 @@ ;; Potential partial reg stall on alternative 2. (set (attr "preferred_for_speed") (cond [(eq_attr "alternative" "2") - (symbol_ref "!TARGET_PARTIAL_REG_STALL")] + (symbol_ref "!TARGET_PARTIAL_REG_STALL") + (eq_attr "alternative" "4,5") + (symbol_ref "TARGET_ENABLE_NDD_MEM")] (symbol_ref "true")))]) (define_insn "*and_2" @@ -14679,10 +14673,6 @@ {b}\t{%2, %1, %0|%0, %1, %2} #" [(set_attr "isa" "*,*,*,apx_ndd,apx_ndd,apx_ndd,avx512f") - (set (attr "preferred_for_speed") - (cond [(eq_attr "alternative" "4,5") - (symbol_ref "TARGET_ENABLE_NDD_MEM")] - (symbol_ref "true"))) (set_attr "type" "alu,alu,alu,alu,alu,alu,msklog") (set_attr "has_nf" "1") (set (attr "mode") @@ -14696,7 +14686,9 @@ ;; Potential partial reg stall on alternative 2. (set (attr "preferred_for_speed") (cond [(eq_attr "alternative" "2") - (symbol_ref "!TARGET_PARTIAL_REG_STALL")] + (symbol_ref "!TARGET_PARTIAL_REG_STALL") + (eq_attr "alternative" "4,5") + (symbol_ref "TARGET_ENABLE_NDD_MEM")] (symbol_ref "true")))]) (define_insn_and_split "*notxorqi_1" @@ -14722,10 +14714,6 @@ } } [(set_attr "isa" "*,*,*,apx_ndd,apx_ndd,apx_ndd,avx512f") - (set (attr "preferred_for_speed") - (cond [(eq_attr "alternative" "4,5") - (symbol_ref "TARGET_ENABLE_NDD_MEM")] - (symbol_ref "true"))) (set_attr "type" "alu,alu,alu,alu,alu,alu,msklog") (set (attr "mode") (cond [(eq_attr "alternative" "2") @@ -14738,7 +14726,9 @@ ;; Potential partial reg stall on alternative 2. (set (attr "preferred_for_speed") (cond [(eq_attr "alternative" "2") - (symbol_ref "!TARGET_PARTIAL_REG_STALL")] + (symbol_ref "!TARGET_PARTIAL_REG_STALL") + (eq_attr "alternative" "4,5") + (symbol_ref "TARGET_ENABLE_NDD_MEM")] (symbol_ref "true")))]) ;; convert (sign_extend:WIDE (any_logic:NARROW (memory, immediate))) @@ -16047,10 +16037,6 @@ not{b}\t{%1, %0|%0, %1} #" [(set_attr "isa" "*,*,apx_ndd,apx_ndd,avx512f") - (set (attr "preferred_for_speed") - (cond [(eq_attr "alternative" "3") - (symbol_ref "TARGET_ENABLE_NDD_MEM")] - (symbol_ref "true"))) (set_attr "type" "negnot,negnot,negnot,negnot,msklog") (set (attr "mode") (cond [(eq_attr "alternative" "1") @@ -16063,7 +16049,9 @@ ;; Potential partial reg stall on alternative 1. (set (attr "preferred_for_speed") (cond [(eq_attr "alternative" "1") - (symbol_ref "!TARGET_PARTIAL_REG_STALL")] + (symbol_ref "!TARGET_PARTIAL_REG_STALL") + (eq_attr "alternative" "3") + (symbol_ref "TARGET_ENABLE_NDD_MEM")] (symbol_ref "true")))]) ;; Alternative 1 is needed to work around LRA limitation, see PR82524. @@ -17214,10 +17202,6 @@ } } [(set_attr "isa" "*,*,*,avx512dq,apx_ndd,apx_ndd") - (set (attr "preferred_for_speed") - (cond [(eq_attr "alternative" "5") - (symbol_ref "TARGET_ENABLE_NDD_MEM")] - (symbol_ref "true"))) (set (attr "type") (cond [(eq_attr "alternative" "2") (const_string "lea") @@ -17240,9 +17224,11 @@ (const_string "*"))) (set_attr "has_nf" "1") (set_attr "mode" "QI,SI,SI,QI,QI,QI") - ;; Potential partial reg stall on alternative 1. + ;; Potential partial reg stall on alternatives 1, 4 and 5. (set (attr "preferred_for_speed") - (cond [(eq_attr "alternative" "1,4,5") + (cond [(eq_attr "alternative" "5") + (symbol_ref "TARGET_ENABLE_NDD_MEM && !TARGET_PARTIAL_REG_STALL") + (eq_attr "alternative" "1,4") (symbol_ref "!TARGET_PARTIAL_REG_STALL")] (symbol_ref "true")))]) diff --git a/gcc/testsuite/gcc.target/i386/apx-ndd-mem-tune.c b/gcc/testsuite/gcc.target/i386/apx-ndd-mem-tune.c new file mode 100644 index 00000000000..5726390be89 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-ndd-mem-tune.c @@ -0,0 +1,53 @@ +/* Verify that the memory form of NDD instructions is guarded by the + X86_TUNE_ENABLE_NDD_MEM tune properly. The duplicated preferred_for_speed + attr will be true when partial_reg_stall enabled for qi patterns, and + override the ENABLE_NDD_MEM set at first, so there should be only one attr + remaining by combining the two conditions together. */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mapxf -march=x86-64 -O2 -mtune-ctrl=partial_reg_stall" } */ + +unsigned char gc; + +unsigned char +add_qi (unsigned char *p, unsigned char b) +{ + unsigned char r = *p + b; + gc = r; + return r; +} + +unsigned char +and_qi (unsigned char *p, unsigned char b) +{ + unsigned char r = *p & b; + gc = r; + return r; +} + +unsigned char +xor_qi (unsigned char *p, unsigned char b) +{ + unsigned char r = *p ^ b; + gc = r; + return r; +} + +unsigned char +not_qi (unsigned char *p) +{ + unsigned char r = ~*p; + gc = r; + return r; +} + +unsigned char +shl_qi (unsigned char *p, unsigned char c) +{ + unsigned char r = (unsigned char) (*p << c); + gc = r; + return r; +} + +/* None of the QImode ops above should use the NDD memory-source form + when partial_reg_stall && !enable_ndd_mem. */ +/* { dg-final { scan-assembler-not {b[ \t]+%[a-z0-9]+, \(%[a-z0-9]+\),} } } */