From: Thomas Perrot Date: Sun, 26 Jun 2022 18:15:19 +0000 (+0200) Subject: opensbi: Update to v1.1 X-Git-Tag: lucaceresoli/bug-15201-perf-libtraceevent-missing~3785 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=337da2a521b060c72375279dac20bc8e3878926e;p=thirdparty%2Fopenembedded%2Fopenembedded-core-contrib.git opensbi: Update to v1.1 This release has: * SBI PMU improvements * RISC-V AIA v0.3.0 draft support * Simple external interrupt handling framework * Xilinx UART-Lite driver * RISC-V privilege specification v1.12 support * RISC-V Svpbmt extension support * RISC-V Smstateen extension support * RISC-V Sstc extension support * RISC-V privilege specification version detection * Platform callback to populate HART extensions * Compile time C arrays support * Probing FDT based drivers using compile time C arrays * SBI HSM improvements * Allwinner D1 platform support * Trap redirection improvements related to [m|h]tinst CSR * SBI v1.0 specification support Overall, this release mainly adds support for various RISC-V ISA extensions ratified in December 2021 along with other improvements. Signed-off-by: Thomas Perrot Signed-off-by: Richard Purdie --- diff --git a/meta/recipes-bsp/opensbi/opensbi_1.0.bb b/meta/recipes-bsp/opensbi/opensbi_1.1.bb similarity index 96% rename from meta/recipes-bsp/opensbi/opensbi_1.0.bb rename to meta/recipes-bsp/opensbi/opensbi_1.1.bb index 8430f62543a..d3a62965336 100644 --- a/meta/recipes-bsp/opensbi/opensbi_1.0.bb +++ b/meta/recipes-bsp/opensbi/opensbi_1.1.bb @@ -8,9 +8,8 @@ require opensbi-payloads.inc inherit autotools-brokensep deploy -SRCREV = "ce4c0188d96b2c20c2e08d24646a5e517fe15a4b" -SRC_URI = "git://github.com/riscv/opensbi.git;branch=master;protocol=https \ - " +SRCREV = "4489876e933d8ba0d8bc6c64bae71e295d45faac" +SRC_URI = "git://github.com/riscv/opensbi.git;branch=master;protocol=https" S = "${WORKDIR}/git"