From: Greg Kroah-Hartman Date: Sun, 8 Sep 2024 11:54:24 +0000 (+0200) Subject: 5.4-stable patches X-Git-Tag: v4.19.322~100 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=33d261bddb0b0b6752e084a1a674d4bd22d2ebd3;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: clk-hi6220-use-clk_of_declare_driver.patch clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch reset-hi6220-add-support-for-ao-reset-controller.patch --- diff --git a/queue-5.4/clk-hi6220-use-clk_of_declare_driver.patch b/queue-5.4/clk-hi6220-use-clk_of_declare_driver.patch new file mode 100644 index 00000000000..0d89c75b516 --- /dev/null +++ b/queue-5.4/clk-hi6220-use-clk_of_declare_driver.patch @@ -0,0 +1,39 @@ +From f1edb498bd9f25936ae3540a8dbd86e6019fdb95 Mon Sep 17 00:00:00 2001 +From: Peter Griffin +Date: Tue, 1 Oct 2019 18:25:46 +0000 +Subject: clk: hi6220: use CLK_OF_DECLARE_DRIVER + +From: Peter Griffin + +commit f1edb498bd9f25936ae3540a8dbd86e6019fdb95 upstream. + +As now we also need to probe in the reset driver as well. + +Cc: Michael Turquette +Cc: Stephen Boyd +Cc: Allison Randal +Cc: Peter Griffin +Cc: linux-clk@vger.kernel.org +Signed-off-by: Peter Griffin +Signed-off-by: John Stultz +Link: https://lkml.kernel.org/r/20191001182546.70090-1-john.stultz@linaro.org +[sboyd@kernel.org: Add comment about reset driver] +Signed-off-by: Stephen Boyd +Cc: Yongqin Liu +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/hisilicon/clk-hi6220.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/clk/hisilicon/clk-hi6220.c ++++ b/drivers/clk/hisilicon/clk-hi6220.c +@@ -86,7 +86,8 @@ static void __init hi6220_clk_ao_init(st + hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao, + ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao); + } +-CLK_OF_DECLARE(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init); ++/* Allow reset driver to probe as well */ ++CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init); + + + /* clocks in sysctrl */ diff --git a/queue-5.4/clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch b/queue-5.4/clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch new file mode 100644 index 00000000000..6232cf85cc9 --- /dev/null +++ b/queue-5.4/clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch @@ -0,0 +1,33 @@ +From 2c4553e6c485a96b5d86989eb9654bf20e51e6dd Mon Sep 17 00:00:00 2001 +From: Satya Priya Kakitapalli +Date: Wed, 31 Jul 2024 11:59:09 +0530 +Subject: clk: qcom: clk-alpha-pll: Fix the pll post div mask + +From: Satya Priya Kakitapalli + +commit 2c4553e6c485a96b5d86989eb9654bf20e51e6dd upstream. + +The PLL_POST_DIV_MASK should be 0 to (width - 1) bits. Fix it. + +Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider") +Cc: stable@vger.kernel.org +Reviewed-by: Konrad Dybcio +Signed-off-by: Satya Priya Kakitapalli +Link: https://lore.kernel.org/r/20240731062916.2680823-2-quic_skakitap@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/clk-alpha-pll.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/qcom/clk-alpha-pll.c ++++ b/drivers/clk/qcom/clk-alpha-pll.c +@@ -38,7 +38,7 @@ + + #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) + # define PLL_POST_DIV_SHIFT 8 +-# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0) ++# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) + # define PLL_ALPHA_EN BIT(24) + # define PLL_ALPHA_MODE BIT(25) + # define PLL_VCO_SHIFT 20 diff --git a/queue-5.4/clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch b/queue-5.4/clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch new file mode 100644 index 00000000000..f912d15b901 --- /dev/null +++ b/queue-5.4/clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch @@ -0,0 +1,37 @@ +From 4ad1ed6ef27cab94888bb3c740c14042d5c0dff2 Mon Sep 17 00:00:00 2001 +From: Satya Priya Kakitapalli +Date: Wed, 31 Jul 2024 11:59:10 +0530 +Subject: clk: qcom: clk-alpha-pll: Fix the trion pll postdiv set rate API + +From: Satya Priya Kakitapalli + +commit 4ad1ed6ef27cab94888bb3c740c14042d5c0dff2 upstream. + +Correct the pll postdiv shift used in clk_trion_pll_postdiv_set_rate +API. The shift value is not same for different types of plls and +should be taken from the pll's .post_div_shift member. + +Fixes: 548a909597d5 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs") +Cc: stable@vger.kernel.org +Signed-off-by: Satya Priya Kakitapalli +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20240731062916.2680823-3-quic_skakitap@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/clk-alpha-pll.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/clk/qcom/clk-alpha-pll.c ++++ b/drivers/clk/qcom/clk-alpha-pll.c +@@ -1257,8 +1257,8 @@ clk_trion_pll_postdiv_set_rate(struct cl + } + + return regmap_update_bits(regmap, PLL_USER_CTL(pll), +- PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, +- val << PLL_POST_DIV_SHIFT); ++ PLL_POST_DIV_MASK(pll) << pll->post_div_shift, ++ val << pll->post_div_shift); + } + + const struct clk_ops clk_trion_pll_postdiv_ops = { diff --git a/queue-5.4/reset-hi6220-add-support-for-ao-reset-controller.patch b/queue-5.4/reset-hi6220-add-support-for-ao-reset-controller.patch new file mode 100644 index 00000000000..8ef2ca556ed --- /dev/null +++ b/queue-5.4/reset-hi6220-add-support-for-ao-reset-controller.patch @@ -0,0 +1,125 @@ +From 697fa27dc5fb4c669471e728e97f176687982f95 Mon Sep 17 00:00:00 2001 +From: Peter Griffin +Date: Fri, 6 Mar 2020 17:21:13 +0000 +Subject: reset: hi6220: Add support for AO reset controller + +From: Peter Griffin + +commit 697fa27dc5fb4c669471e728e97f176687982f95 upstream. + +This is required to bring Mali450 gpu out of reset. + +Cc: Peter Griffin +Cc: Enrico Weigelt +Signed-off-by: Peter Griffin +[jstultz: Added comment, Fix void return build issue +Reported-by: kbuild test robot ] +Signed-off-by: John Stultz +Signed-off-by: Philipp Zabel +Cc: Yongqin Liu +Signed-off-by: Greg Kroah-Hartman +--- + drivers/reset/hisilicon/hi6220_reset.c | 69 ++++++++++++++++++++++++++++++++- + 1 file changed, 68 insertions(+), 1 deletion(-) + +--- a/drivers/reset/hisilicon/hi6220_reset.c ++++ b/drivers/reset/hisilicon/hi6220_reset.c +@@ -33,6 +33,7 @@ + enum hi6220_reset_ctrl_type { + PERIPHERAL, + MEDIA, ++ AO, + }; + + struct hi6220_reset_data { +@@ -92,6 +93,65 @@ static const struct reset_control_ops hi + .deassert = hi6220_media_deassert, + }; + ++#define AO_SCTRL_SC_PW_CLKEN0 0x800 ++#define AO_SCTRL_SC_PW_CLKDIS0 0x804 ++ ++#define AO_SCTRL_SC_PW_RSTEN0 0x810 ++#define AO_SCTRL_SC_PW_RSTDIS0 0x814 ++ ++#define AO_SCTRL_SC_PW_ISOEN0 0x820 ++#define AO_SCTRL_SC_PW_ISODIS0 0x824 ++#define AO_MAX_INDEX 12 ++ ++static int hi6220_ao_assert(struct reset_controller_dev *rc_dev, ++ unsigned long idx) ++{ ++ struct hi6220_reset_data *data = to_reset_data(rc_dev); ++ struct regmap *regmap = data->regmap; ++ int ret; ++ ++ ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTEN0, BIT(idx)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_write(regmap, AO_SCTRL_SC_PW_ISOEN0, BIT(idx)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_write(regmap, AO_SCTRL_SC_PW_CLKDIS0, BIT(idx)); ++ return ret; ++} ++ ++static int hi6220_ao_deassert(struct reset_controller_dev *rc_dev, ++ unsigned long idx) ++{ ++ struct hi6220_reset_data *data = to_reset_data(rc_dev); ++ struct regmap *regmap = data->regmap; ++ int ret; ++ ++ /* ++ * It was suggested to disable isolation before enabling ++ * the clocks and deasserting reset, to avoid glitches. ++ * But this order is preserved to keep it matching the ++ * vendor code. ++ */ ++ ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTDIS0, BIT(idx)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_write(regmap, AO_SCTRL_SC_PW_ISODIS0, BIT(idx)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_write(regmap, AO_SCTRL_SC_PW_CLKEN0, BIT(idx)); ++ return ret; ++} ++ ++static const struct reset_control_ops hi6220_ao_reset_ops = { ++ .assert = hi6220_ao_assert, ++ .deassert = hi6220_ao_deassert, ++}; ++ + static int hi6220_reset_probe(struct platform_device *pdev) + { + struct device_node *np = pdev->dev.of_node; +@@ -117,9 +177,12 @@ static int hi6220_reset_probe(struct pla + if (type == MEDIA) { + data->rc_dev.ops = &hi6220_media_reset_ops; + data->rc_dev.nr_resets = MEDIA_MAX_INDEX; +- } else { ++ } else if (type == PERIPHERAL) { + data->rc_dev.ops = &hi6220_peripheral_reset_ops; + data->rc_dev.nr_resets = PERIPH_MAX_INDEX; ++ } else { ++ data->rc_dev.ops = &hi6220_ao_reset_ops; ++ data->rc_dev.nr_resets = AO_MAX_INDEX; + } + + return reset_controller_register(&data->rc_dev); +@@ -134,6 +197,10 @@ static const struct of_device_id hi6220_ + .compatible = "hisilicon,hi6220-mediactrl", + .data = (void *)MEDIA, + }, ++ { ++ .compatible = "hisilicon,hi6220-aoctrl", ++ .data = (void *)AO, ++ }, + { /* sentinel */ }, + }; + MODULE_DEVICE_TABLE(of, hi6220_reset_match); diff --git a/queue-5.4/series b/queue-5.4/series index de8f3bbe4e0..702df3d070a 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -32,3 +32,7 @@ mmc-dw_mmc-fix-idmac-operation-with-pages-bigger-than-4k.patch mmc-sdhci-of-aspeed-fix-module-autoloading.patch fuse-update-stats-for-pages-in-dropped-aux-writeback-list.patch fuse-use-unsigned-type-for-getxattr-listxattr-size-truncation.patch +reset-hi6220-add-support-for-ao-reset-controller.patch +clk-hi6220-use-clk_of_declare_driver.patch +clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch +clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch