From: Greg Kroah-Hartman Date: Fri, 27 Jan 2012 00:55:08 +0000 (-0800) Subject: 3.2-stable patches X-Git-Tag: v3.0.19~19 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=3411b2516bef00afbcc1a4bff7a621555990936e;p=thirdparty%2Fkernel%2Fstable-queue.git 3.2-stable patches added patches: m68k-fix-assembler-constraint-to-prevent-overeager-gcc-optimisation.patch x86-microcode_amd-add-support-for-cpu-family-specific-container-files.patch x86-uv-fix-uninitialized-spinlocks.patch x86-uv-fix-uv_gpa_to_soc_phys_ram-shift.patch --- diff --git a/queue-3.2/m68k-fix-assembler-constraint-to-prevent-overeager-gcc-optimisation.patch b/queue-3.2/m68k-fix-assembler-constraint-to-prevent-overeager-gcc-optimisation.patch new file mode 100644 index 00000000000..09ee7ff6772 --- /dev/null +++ b/queue-3.2/m68k-fix-assembler-constraint-to-prevent-overeager-gcc-optimisation.patch @@ -0,0 +1,161 @@ +From 2a3535069e33d8b416f406c159ce924427315303 Mon Sep 17 00:00:00 2001 +From: Andreas Schwab +Date: Mon, 9 Jan 2012 15:10:15 +0100 +Subject: m68k: Fix assembler constraint to prevent overeager gcc optimisation + +From: Andreas Schwab + +commit 2a3535069e33d8b416f406c159ce924427315303 upstream. + +Passing the address of a variable as an operand to an asm statement +doesn't mark the value of this variable as used, so gcc may optimize its +initialisation away. Fix this by using the "m" constraint instead. + +Signed-off-by: Andreas Schwab +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Greg Kroah-Hartman + +--- + arch/m68k/atari/config.c | 8 ++++---- + arch/m68k/kernel/process_mm.c | 4 ++-- + arch/m68k/kernel/process_no.c | 4 ++-- + arch/m68k/kernel/traps.c | 36 +++++++++++++++++------------------- + arch/m68k/mm/cache.c | 6 +++--- + 5 files changed, 28 insertions(+), 30 deletions(-) + +--- a/arch/m68k/atari/config.c ++++ b/arch/m68k/atari/config.c +@@ -414,9 +414,9 @@ void __init config_atari(void) + * FDC val = 4 -> Supervisor only */ + asm volatile ("\n" + " .chip 68030\n" +- " pmove %0@,%/tt1\n" ++ " pmove %0,%/tt1\n" + " .chip 68k" +- : : "a" (&tt1_val)); ++ : : "m" (tt1_val)); + } else { + asm volatile ("\n" + " .chip 68040\n" +@@ -569,10 +569,10 @@ static void atari_reset(void) + : "d0"); + } else + asm volatile ("\n" +- " pmove %0@,%%tc\n" ++ " pmove %0,%%tc\n" + " jmp %1@" + : /* no outputs */ +- : "a" (&tc_val), "a" (reset_addr)); ++ : "m" (tc_val), "a" (reset_addr)); + } + + +--- a/arch/m68k/kernel/process_mm.c ++++ b/arch/m68k/kernel/process_mm.c +@@ -189,8 +189,8 @@ void flush_thread(void) + current->thread.fs = __USER_DS; + if (!FPU_IS_EMU) + asm volatile (".chip 68k/68881\n\t" +- "frestore %0@\n\t" +- ".chip 68k" : : "a" (&zero)); ++ "frestore %0\n\t" ++ ".chip 68k" : : "m" (zero)); + } + + /* +--- a/arch/m68k/kernel/process_no.c ++++ b/arch/m68k/kernel/process_no.c +@@ -163,8 +163,8 @@ void flush_thread(void) + #ifdef CONFIG_FPU + if (!FPU_IS_EMU) + asm volatile (".chip 68k/68881\n\t" +- "frestore %0@\n\t" +- ".chip 68k" : : "a" (&zero)); ++ "frestore %0\n\t" ++ ".chip 68k" : : "m" (zero)); + #endif + } + +--- a/arch/m68k/kernel/traps.c ++++ b/arch/m68k/kernel/traps.c +@@ -552,13 +552,13 @@ static inline void bus_error030 (struct + + #ifdef DEBUG + asm volatile ("ptestr %3,%2@,#7,%0\n\t" +- "pmove %%psr,%1@" +- : "=a&" (desc) +- : "a" (&temp), "a" (addr), "d" (ssw)); ++ "pmove %%psr,%1" ++ : "=a&" (desc), "=m" (temp) ++ : "a" (addr), "d" (ssw)); + #else + asm volatile ("ptestr %2,%1@,#7\n\t" +- "pmove %%psr,%0@" +- : : "a" (&temp), "a" (addr), "d" (ssw)); ++ "pmove %%psr,%0" ++ : "=m" (temp) : "a" (addr), "d" (ssw)); + #endif + mmusr = temp; + +@@ -605,20 +605,18 @@ static inline void bus_error030 (struct + !(ssw & RW) ? "write" : "read", addr, + fp->ptregs.pc, ssw); + asm volatile ("ptestr #1,%1@,#0\n\t" +- "pmove %%psr,%0@" +- : /* no outputs */ +- : "a" (&temp), "a" (addr)); ++ "pmove %%psr,%0" ++ : "=m" (temp) ++ : "a" (addr)); + mmusr = temp; + + printk ("level 0 mmusr is %#x\n", mmusr); + #if 0 +- asm volatile ("pmove %%tt0,%0@" +- : /* no outputs */ +- : "a" (&tlong)); ++ asm volatile ("pmove %%tt0,%0" ++ : "=m" (tlong)); + printk("tt0 is %#lx, ", tlong); +- asm volatile ("pmove %%tt1,%0@" +- : /* no outputs */ +- : "a" (&tlong)); ++ asm volatile ("pmove %%tt1,%0" ++ : "=m" (tlong)); + printk("tt1 is %#lx\n", tlong); + #endif + #ifdef DEBUG +@@ -668,13 +666,13 @@ static inline void bus_error030 (struct + + #ifdef DEBUG + asm volatile ("ptestr #1,%2@,#7,%0\n\t" +- "pmove %%psr,%1@" +- : "=a&" (desc) +- : "a" (&temp), "a" (addr)); ++ "pmove %%psr,%1" ++ : "=a&" (desc), "=m" (temp) ++ : "a" (addr)); + #else + asm volatile ("ptestr #1,%1@,#7\n\t" +- "pmove %%psr,%0@" +- : : "a" (&temp), "a" (addr)); ++ "pmove %%psr,%0" ++ : "=m" (temp) : "a" (addr)); + #endif + mmusr = temp; + +--- a/arch/m68k/mm/cache.c ++++ b/arch/m68k/mm/cache.c +@@ -52,9 +52,9 @@ static unsigned long virt_to_phys_slow(u + unsigned long *descaddr; + + asm volatile ("ptestr %3,%2@,#7,%0\n\t" +- "pmove %%psr,%1@" +- : "=a&" (descaddr) +- : "a" (&mmusr), "a" (vaddr), "d" (get_fs().seg)); ++ "pmove %%psr,%1" ++ : "=a&" (descaddr), "=m" (mmusr) ++ : "a" (vaddr), "d" (get_fs().seg)); + if (mmusr & (MMU_I|MMU_B|MMU_L)) + return 0; + descaddr = phys_to_virt((unsigned long)descaddr); diff --git a/queue-3.2/series b/queue-3.2/series index e2317d666df..1cc5ee0133b 100644 --- a/queue-3.2/series +++ b/queue-3.2/series @@ -20,3 +20,7 @@ jbd-issue-cache-flush-after-checkpointing.patch crypto-sha512-make-it-work-undo-percpu-message-schedule.patch crypto-sha512-reduce-stack-usage-to-safe-number.patch tpm_tis-add-delay-after-aborting-command.patch +x86-uv-fix-uninitialized-spinlocks.patch +x86-uv-fix-uv_gpa_to_soc_phys_ram-shift.patch +x86-microcode_amd-add-support-for-cpu-family-specific-container-files.patch +m68k-fix-assembler-constraint-to-prevent-overeager-gcc-optimisation.patch diff --git a/queue-3.2/x86-microcode_amd-add-support-for-cpu-family-specific-container-files.patch b/queue-3.2/x86-microcode_amd-add-support-for-cpu-family-specific-container-files.patch new file mode 100644 index 00000000000..389895fa900 --- /dev/null +++ b/queue-3.2/x86-microcode_amd-add-support-for-cpu-family-specific-container-files.patch @@ -0,0 +1,72 @@ +From 5b68edc91cdc972c46f76f85eded7ffddc3ff5c2 Mon Sep 17 00:00:00 2001 +From: Andreas Herrmann +Date: Fri, 20 Jan 2012 17:44:12 +0100 +Subject: x86/microcode_amd: Add support for CPU family specific container files + +From: Andreas Herrmann + +commit 5b68edc91cdc972c46f76f85eded7ffddc3ff5c2 upstream. + +We've decided to provide CPU family specific container files +(starting with CPU family 15h). E.g. for family 15h we have to +load microcode_amd_fam15h.bin instead of microcode_amd.bin + +Rationale is that starting with family 15h patch size is larger +than 2KB which was hard coded as maximum patch size in various +microcode loaders (not just Linux). + +Container files which include patches larger than 2KB cause +different kinds of trouble with such old patch loaders. Thus we +have to ensure that the default container file provides only +patches with size less than 2KB. + +Signed-off-by: Andreas Herrmann +Cc: Borislav Petkov +Cc: +Link: http://lkml.kernel.org/r/20120120164412.GD24508@alberich.amd.com +[ documented the naming convention and tidied the code a bit. ] +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/kernel/microcode_amd.c | 24 ++++++++++++++++++++++-- + 1 file changed, 22 insertions(+), 2 deletions(-) + +--- a/arch/x86/kernel/microcode_amd.c ++++ b/arch/x86/kernel/microcode_amd.c +@@ -300,13 +300,33 @@ free_table: + return state; + } + ++/* ++ * AMD microcode firmware naming convention, up to family 15h they are in ++ * the legacy file: ++ * ++ * amd-ucode/microcode_amd.bin ++ * ++ * This legacy file is always smaller than 2K in size. ++ * ++ * Starting at family 15h they are in family specific firmware files: ++ * ++ * amd-ucode/microcode_amd_fam15h.bin ++ * amd-ucode/microcode_amd_fam16h.bin ++ * ... ++ * ++ * These might be larger than 2K. ++ */ + static enum ucode_state request_microcode_amd(int cpu, struct device *device) + { +- const char *fw_name = "amd-ucode/microcode_amd.bin"; ++ char fw_name[36] = "amd-ucode/microcode_amd.bin"; + const struct firmware *fw; + enum ucode_state ret = UCODE_NFOUND; ++ struct cpuinfo_x86 *c = &cpu_data(cpu); + +- if (request_firmware(&fw, fw_name, device)) { ++ if (c->x86 >= 0x15) ++ snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86); ++ ++ if (request_firmware(&fw, (const char *)fw_name, device)) { + pr_err("failed to load file %s\n", fw_name); + goto out; + } diff --git a/queue-3.2/x86-uv-fix-uninitialized-spinlocks.patch b/queue-3.2/x86-uv-fix-uninitialized-spinlocks.patch new file mode 100644 index 00000000000..bd5310f7891 --- /dev/null +++ b/queue-3.2/x86-uv-fix-uninitialized-spinlocks.patch @@ -0,0 +1,54 @@ +From d2ebc71d472020bc30e29afe8c4d2a85a5b41f56 Mon Sep 17 00:00:00 2001 +From: Cliff Wickman +Date: Wed, 18 Jan 2012 09:40:47 -0600 +Subject: x86/uv: Fix uninitialized spinlocks + +From: Cliff Wickman + +commit d2ebc71d472020bc30e29afe8c4d2a85a5b41f56 upstream. + +Initialize two spinlocks in tlb_uv.c and also properly define/initialize +the uv_irq_lock. + +The lack of explicit initialization seems to be functionally +harmless, but it is diagnosed when these are turned on: + + CONFIG_DEBUG_SPINLOCK=y + CONFIG_DEBUG_MUTEXES=y + CONFIG_DEBUG_LOCK_ALLOC=y + CONFIG_LOCKDEP=y + +Signed-off-by: Cliff Wickman +Cc: Dimitri Sivanich +Link: http://lkml.kernel.org/r/E1RnXd1-0003wU-PM@eag09.americas.sgi.com +[ Added the uv_irq_lock initialization fix by Dimitri Sivanich ] +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/platform/uv/tlb_uv.c | 2 ++ + arch/x86/platform/uv/uv_irq.c | 2 +- + 2 files changed, 3 insertions(+), 1 deletion(-) + +--- a/arch/x86/platform/uv/tlb_uv.c ++++ b/arch/x86/platform/uv/tlb_uv.c +@@ -1860,6 +1860,8 @@ static void __init init_per_cpu_tunables + bcp->cong_reps = congested_reps; + bcp->cong_period = congested_period; + bcp->clocks_per_100_usec = usec_2_cycles(100); ++ spin_lock_init(&bcp->queue_lock); ++ spin_lock_init(&bcp->uvhub_lock); + } + } + +--- a/arch/x86/platform/uv/uv_irq.c ++++ b/arch/x86/platform/uv/uv_irq.c +@@ -25,7 +25,7 @@ struct uv_irq_2_mmr_pnode{ + int irq; + }; + +-static spinlock_t uv_irq_lock; ++static DEFINE_SPINLOCK(uv_irq_lock); + static struct rb_root uv_irq_root; + + static int uv_set_irq_affinity(struct irq_data *, const struct cpumask *, bool); diff --git a/queue-3.2/x86-uv-fix-uv_gpa_to_soc_phys_ram-shift.patch b/queue-3.2/x86-uv-fix-uv_gpa_to_soc_phys_ram-shift.patch new file mode 100644 index 00000000000..fc2e492404c --- /dev/null +++ b/queue-3.2/x86-uv-fix-uv_gpa_to_soc_phys_ram-shift.patch @@ -0,0 +1,39 @@ +From 5a51467b146ab7948d2f6812892eac120a30529c Mon Sep 17 00:00:00 2001 +From: Russ Anderson +Date: Wed, 18 Jan 2012 20:07:54 -0600 +Subject: x86/uv: Fix uv_gpa_to_soc_phys_ram() shift + +From: Russ Anderson + +commit 5a51467b146ab7948d2f6812892eac120a30529c upstream. + +uv_gpa_to_soc_phys_ram() was inadvertently ignoring the +shift values. This fix takes the shift into account. + +Signed-off-by: Russ Anderson +Link: http://lkml.kernel.org/r/20120119020753.GA7228@sgi.com +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/include/asm/uv/uv_hub.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/x86/include/asm/uv/uv_hub.h ++++ b/arch/x86/include/asm/uv/uv_hub.h +@@ -318,13 +318,13 @@ uv_gpa_in_mmr_space(unsigned long gpa) + /* UV global physical address --> socket phys RAM */ + static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) + { +- unsigned long paddr = gpa & uv_hub_info->gpa_mask; ++ unsigned long paddr; + unsigned long remap_base = uv_hub_info->lowmem_remap_base; + unsigned long remap_top = uv_hub_info->lowmem_remap_top; + + gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | + ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val); +- gpa = gpa & uv_hub_info->gpa_mask; ++ paddr = gpa & uv_hub_info->gpa_mask; + if (paddr >= remap_base && paddr < remap_base + remap_top) + paddr -= remap_base; + return paddr;